Page 1 of 8 SPC 2314: Microprocessors and Interfacing Lecture Notes

Microprocessor architecture
 ⟹ a layout of the main functional units that make up a µp.
 All the functional units are connected to the system bus (data, address and control bus).
 A µp is mostly described in terms of the size (no. of bits ≡ no. of wires) of its data bus (aka data bus width/word
length) → it is the number of bits that can be carried to and from memory and I/O devices.

Description according to Data range (in dec) Data range (in hex)
data bus width
8-bit µp → 0 – 255 → 00 – FF
16-bit µp → 0 – 65,535 → 0000 – FFFF
32-bit µp → 0 – 4,294,967,295 → 00000000 – FFFFFFFF
64-bit µp (modern laptops
→ 0 – 18,446,744,073,709,551,615 → 0000000000000000 – FFFFFFFFFFFFFFFF
and desktops)
 Of importance also, is the size of a μp’s address bus, as it determines the number of addresses that a μp can
generate → the so-called address space.
The address space of a microprocessor has a direct bearing on the number of memory locations that a
microprocessor can access.
The address space of a microprocessor with a 16-bit address bus is 216 = 65,536 ⇒ the microprocessor can
access a maximum of 65,536 memory locations.

The Intel 8085 microprocessor architecture

 It’s an 8-bit μp.
Data bus width = 8 bits → data range from 00H to FFH.
 It has a 16-bit address bus → address space = 65,536, address range: 0000H to FFFFH.
 Main units:

NB: Supplement your learning from the lecture and lecture notes by independent study and discussions.
Page 2 of 8 SPC 2314: Microprocessors and Interfacing Lecture Notes

1. Storage unit
‒ Consists of registers → they act as temporary memory locations.
‒ Classified as,
i. General purpose registers → their functions are not defined in advance.
o B, C, D, E, H, L – all are 8-bit.
o Can be used to temporarily store 8-bit data or can be used in pairs (BC, DE, HL) to temporarily
store 16-bit data (the first register contains the higher-order byte while the second register
contains the lower-order byte).
o The HL register pair can also be used to hold a 16-bit address of a memory location → address
pointer.
o W and Z → 8-bit registers that are not accessible to a programmer (microprocessor registers).

ii. Special purpose registers → their functions are defined in advance.

Register Size Function

Stack pointer (SP) Holds the address of the top item in stack.
Stack → a reserved section of RAM that is used for storage
16-bit of temporary data and return address of subroutines.
Program counter (PC) Holds the memory address of the next instruction to be
executed.

2. Instruction decoding, timing and control unit

‒ Consists of:
i. An 8-bit register – the instruction register (IR) → holds part of the current instruction that specifies
the operation to be carried out → op code.
ii. Instruction decoder – decodes the op code.
iii. Timing & control signals generator → gives
o timing signals that synchronize operations to be performed by the various sections of a μp and
other devices in the μc system, and
o control signals that control flow of data.

At an appropriate time, the op code stored in the IR is fed to the instruction decoder, which decodes
it, and gives the decoded information (such as operation to be performed, source of data to be operated
on, etc.) to the timing and control unit.
The timing signals are generated by a clock generator circuit that is connected to an external quartz
crystal.
o Its function is to provide precise timing for synchronization of data transfers.

NB: Supplement your learning from the lecture and lecture notes by independent study and discussions.
Page 3 of 8 SPC 2314: Microprocessors and Interfacing Lecture Notes

o It is provided by an electronic clock circuit that produces pulses in form of square waves – a train
of binary pulses.
o The clock circuitry is normally connected external to the μP through the clock input pin (ϕ) of the
µp IC.

3. Processing unit
‒ Consists of:
i. An 8-bit arithmetic and logic unit (ALU) → performs 8-bit arithmetic (addition, subtraction, etc)
and logic (AND, OR, etc) operations.
ii. An 8-bit register – the accumulator (reg. A) → holds the initial data to operate upon, the
intermediate results, and the result of an operation.
iii. An 8-bit temporary data register → used internally by the μp, and cannot, therefore, be accessed by
a programmer.
iv. An 8-bit register – flag register (F reg.) → indicates the status of an operation (did the result yield
a zero, did it have a carry, etc.). Also called the status register.
Only five of its bits are used, the remaining three (marked as X in the figure below) are unused.
The five bits that are used are known as flags → they indicate the status of an operation. They are
abbreviated as shown below.

By default, or upon reset, all the bits are at logic state 0. Thus,

Their status change based upon the conditions as summarized below:

NB: Supplement your learning from the lecture and lecture notes by independent study and discussions.
Page 4 of 8 SPC 2314: Microprocessors and Interfacing Lecture Notes

Flag Status Condition

S flag ≡ sign flag Set (= 1) if the result of an operation (as contained in the
accumulator) is negative (-)

Z flag ≡ zero flag Set (= 1) if the result of an operation is zero

AC flag ≡ auxiliary carry flag Set (= 1) if there is a carry from the lower nibble to the higher nibble

Used in BCD operations.

P flag ≡ parity flag Set (= 1) if the result of an operation has an even number of 1s

CY flag ≡ carry flag Set (= 1) if an add operation generated a carry or a subtraction

operation generated a borrow

4. Interrupt control unit

‒ Allows and controls interrupts.
‒ An interrupt → a signal sent to the μp from a device that requires attention.
The μp responds by setting aside execution of its current task (main program) and attending to the
interrupting device through an interrupt service routine (sub-routine). When the interrupting device
has been dealt with, the μp continues with its original task as if it was never been interrupted.

5. Serial I/O control unit → allows and controls serial data transfer.

 Note: All the CPU registers can be as either general-purpose or special-purpose. The number of registers in a
CPU varies from one CPU to another.

NB: Supplement your learning from the lecture and lecture notes by independent study and discussions.
Page 5 of 8 SPC 2314: Microprocessors and Interfacing Lecture Notes

Programmer’s models for the 8085 microprocessor

 Programmer’s model → a layout of the μp registers that are available to a programmer including their
functions, sizes (no. of bits that a register that accommodate) and register combinations.

 Note: The PC (Program Counter) does not have much use in programming, but acts as an indicator to a
programmer – stores the address of the next instruction to be executed, thereby indicating the number of
instructions executed.

NB: Supplement your learning from the lecture and lecture notes by independent study and discussions.
Page 6 of 8 SPC 2314: Microprocessors and Interfacing Lecture Notes

 Detailed 8085 CPU architecture

Additional components:
o Increment/decrement address latch → a 16-bit register that increments/decrements contents of the PC
and SP registers.
o 8-bit unidirectional address buffer → drives (increasing the driving capacity of current) the higher order
address bus (A15 – A8).
o 8-bit bidirectional address/data buffer → drives multiplexed address/data bus, i.e. lower order address
bus (A7 – A0) and data bus (D7 – D0).

NB: Supplement your learning from the lecture and lecture notes by independent study and discussions.
Page 7 of 8 SPC 2314: Microprocessors and Interfacing Lecture Notes

The Intel 8085 microprocessor: pin-out diagram and pin description

Pin-out diagram Pin description

 Pins 1 and 2: X1 and X2 respectively –

connected to an exterior oscillator for
generating an appropriate clock signal.
 Pin 3: RESOUT (RESET OUT) - specifies
that the CPU has been rearranged with
RST IN.
 Pin 4: SOD (serial output data) - data on
this pin is sent out to the 7th-bit of the
accumulator whenever an instruction of
SIM (Set Interrupt Mask) is performed.
 Pin 5: SID (serial input data) – data on this
pin is uploaded into the 7th-bit of the
accumulator when RIM (Read Interrupt
Mask) instruction is performed.
 Pins 6 to 10: interrupt pins with TRAP (a
non-maskable → cannot be disallowed by
a program) being of the highest priority
and lowest priority being INTR (RST 5.5,
RST 6.5, RST 7.5, and INTR are maskable
→ may be disallowed by a program).
 Pin 11: INTA (Interrupt acknowledge) –
recognizes an interrupt signal.
 Pins 12 to 19: Address bus/data bus (AD0-
AD7) - applicable for the lower byte of the
address bus and data bus.
 Pin 20: GND – ground pin.
 Pins 21 to 28: A8 – A16 (Address bus) –
applicable for the higher byte of the
address bus.
 Pins 29 and 33: Status Signals (S0-S1) –
allows different functions based on their
status: S0S1=00→halt operation,
S0S1=01→read, S0S1=10→write,
S0S1=11→opcode fetch.
 Pin 30: ALE (Address Latch Enable) -
assists in demultiplexing the data bus as
well as low order address.
 Pin 31: WR (WRITE) - when low data is
written to I/O device or memory.

NB: Supplement your learning from the lecture and lecture notes by independent study and discussions.
Page 8 of 8 SPC 2314: Microprocessors and Interfacing Lecture Notes

 Pin 32: RD (READ) – when low data is

read from I/O device or memory.
 Pin 34: Input-output/memory (IO/M) -
resolves whether the address is intended
for memory or input/output. When high
then the address is used for I/= devices and
when low for memory.
 Pin 35: READY – when high it indicates
that a device is set for accepting or
transferring data.
 Pin 36: RESIN (RESET IN) - used for
resetting the program counter to zero and
resets the Interrupt Enable and HLDA
Flip-flops and makes address, data and
control lines tri-stated.
 Pin 37: CLK (clock output)- provides
clock input to all other peripherals or
digital ICs.
 Pin 38: HLDA (HOLD acknowledge) -
indicates that the CPU has received the
Hold request and that it will withdraw the
buses in the next clock cycle.
 Pin 39: HOLD - indicates that another
device is requesting the use of the address
and data buses.
 Pin 40: VCC and VSS - +5 V supply

 40-pin DIP package.

 LSI
 Based on NMOS technology.
 Requires a single +5V DC power supply.
 8-bit data bus.
 16-bit address bus
i.e. can address up to 216 = 65,536
memory locations.

NB: Supplement your learning from the lecture and lecture notes by independent study and discussions.