Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-1

LECTURE 29 – LOW POWER AND LOW NOISE OP AMPS

LECTURE ORGANIZATION
Outline
• Review of subthreshold operation
• Low power op amps
• Review of MOSFET noise modeling and analysis
• Low noise op amps
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
Pages 398-419

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-2

REVIEW OF SUBTHRESHOLD OPERATION

Subthreshold Operation
Most micropower op
amps use transistors in
the subthreshold region.
Subthreshold
characteristics:

The model that has been developed for the large signal sub-threshold operation is:
W vGS-VT vDS
iD = It L exp nV 1 + V  where vDS > 0 and VDS(sat) = VON = VGS -VT = 2nVt
 t  A
Small-signal model:
diD | W It vGS-VT vDS ID qID ID Cox
gm = =I exp 1 + = = =
dvGS Q t L nVt  nV t  V A nV t nkT Vt Cox+Cjs
diD | ID
gds = dv 
DS Q VA

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-3

Boundary Between Subthreshold and Strong Inversion

It is useful to develop a means of estimating when a MOSFET is making the transition
between subthreshold and strong inversion to know when to use the proper model.
The relationship developed is based on the following concept:
iD
We will solve for the value of vGS
(actually vGS -VT) and find the drain iD = K‘W( vGS-VT)2
2L
current where these two values are
equal [vGS(tran.) -VT)]. IW vGS-VT
i = t exp( ) D L nVt
The large signal expressions for each iD(tran.)
region are: vGS
070507-01 VT vGS(tran.)
Subthreshold-
W vGS-VT  iD   It(W/L)
iD ≈ It L exp nV   vGS-VT = nVt ln I (W/L) ≈ nVt 1 - i
  
 t   t   D 
if (ItW/L)/iD < 0.5.
Strong inversion-
K'W 2iD
iD = 2L vGS-VT2  vGS-VT = K'(W/L)
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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-4

Boundary Between Subthreshold and Strong Inversion - Continued

Equating the two large signal expressions gives,
 It(W/L) 2iD  It(W/L)2 2iD
nVt 1 - i =  n Vt 1 - i
2 2  =
 D  K'(W/L)  D  K'(W/L)
Expanding gives,
It2(W/L)2 2 It(W/L)  2iD
2 2
n Vt  -  2 2
+ 1 ≈ n Vt = K'(W/L) if (ItW/L)/iD < 0.5
2 i
 iD D 
Therefore we get,
K'W 2 2
iD(tran.) = n Vt
2L
For example, if K’ = 120µA/V2, W/L = 100, and n = 2, then at room temperature the
value of drain current at the transition between subthreshold and strong inversion is
120µA/V2100 2 = 16.22µA
iD(tran.) = 4·(0.026)
2
One will find for UDSM technology, that weak inversion or subthreshold operation can
occur at large currents for large values of W/L.

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-5

Extraction of Weak Inversion Model Parameters

Model:
W
 
vGS- VT  iD 
iD = It  L  exp nV (1+ vDS) and vGS = VT - nVt lnI (W/L)
   t  t 
Extraction circuit and results for low threshold NMOS:
ID

+ VDS
VBS VGS
-
111130-03

1.) Extraction of It (W/L=2.5).

W  L
Set VGS = VT to get ID = I L  which gives It = ID W = 204nA (0.4) = 81.6 nA

t
  
2.) Extraction of n:
Take the log of the current relationship to get,
 W
 
vGS- VT d(ln iD) 1 1  VGS2 - VGS1 
ln (iD) = ln It L  + nV → dv = nV → n = V ln(I ) - ln(I )
  t GS t t D2 D1 
1  0.14151-0.088567 
n = 0.0259 ln(223.38nA) - ln(52.966nA) = 1.418
 
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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-6

LOW POWER OP AMPS

Two-Stage, Miller Op Amp Operating in Weak Inversion
VDD

M6
M3 M4 Cc
vout

- M1 M2 CL
vin
+
+ M7
VBias M5
-
VSS Fig.7.4-1
Low frequency response:
 ro2ro4   ro6ro7  1 1
Avo = gm2gm6   = (No longer  )
 o2
r + ro4  o6
r + ro7 n n
2 6 (kT/q) 2 (  2 +  4 )( 6 +  7 ) I D
GB and SR:
ID1 ID5 ID1  kT

GB = and SR = =2 = 2GB n1  = 2GBn1Vt
(n1kT/q)C C C  q

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-7

Example 29-1 Gain and GB Calculations for Subthreshold Op Amp.

Calculate the gain, GB, and SR of the op amp shown above. The currents are ID5 =
200 nA and ID7 = 500 nA. The device lengths are 1 m. Values for n are 1.5 and 2.5 for
p-channel and n-channel transistors respectively. The compensation capacitor is 5 pF.
The channel length modulation parameters are N = 0.06V-1 and P = 0.08V-1. Assume
that the temperature is 27 C. If VDD = 1.5V and VSS = -1.5V, what is the power
dissipation of this op amp?
Solution
The low-frequency small-signal gain is,
1
Av = = 20,126 V/V
(1.5)(2.5)(0.026)2(0.06 + 0.08)(0.06 + 0.08)
The gain bandwidth is
100x10-9
GB = = 307,690 rps  49.0 kHz
2.5(0.026)(5x10-12)
The slew rate is
SR = (2)(307690)(2.5)(0.026) = 0.04 V/s
The power dissipation is,
Pdiss = 3(0.7µA) =2.1µW

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-8

Push-Pull Output Op Amp in Weak Inversion

First stage gain is, VDD
gm2 ID2n4Vt ID2n4
Avo = g = I n V = I n  1
m4 D4 2 t D4 2 M3 M4

M8 M6
Total gain is, vi2
M1 M2
gm1(S6/S4) (S6/S4) vout
Avo = =
(gds6 + gds7) (6 + 7)n1Vt Cc
At room temperature (Vt = 0.0259V) and + M5
VBias
for typical device lengths, gains of 60dB M9 M7
can be obtained. -
The GB is, VSS Fig. 7.4-2

gm1 S6 gm1b

GB =  =
C S4 C
where b is the current ratio between M4:M6 and M3:M8.

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-9

Increasing the Gain of the Previous Op Amp

1.) Can reduce the currents in M3 and M4 and introduce gain in the current mirrors.
2.) Use a cascode output stage (can’t use self-biased cascode, currents are too low).
VDD
+
M8 M3 M4 M6
VT+2VON
-
M13 M10
M14
vi2 vi1
M1 M2 vout
Cc
M5 I5
M12 M15 + M11
gm1+gm2 +
Av =  R VBias
VT+2VON
 2  out M9 M7
I5 - -
VSS Fig. 7.4-3A
2nnVt  I5   1 
 
I72n2 I72p2 2I7 nnVt2(nnn2+npp2)
= =
+
I7 I7
nnVt npVt
Can easily achieve gains greater than 80dB with power dissipation of less than 1µW.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-10

Increasing the Output Current for Weak Inversion Operation

A significant disadvantage of the weak inversion is that very small currents are available
to drive output capacitance so the slew rate becomes very small.
Dynamically biased differential amplifier input stage:

Note that the sinking current for M1 and M2 is

Isink = I5 + A(i2-i1) + A(i1-i2) where (i2-i1) and (i1-i2) are only positive or zero.
If vi1>vi2, then i2>i1 and the sinking current is increased by A(i2-i1).
If vi2>vi1, then i1>i2 and the sinking current is increased by A(i1-i2).
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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-11

Dynamically Biased Differential Amplifier - Continued

How much output current is available from this circuit if there is no current gain from the
input to output stage?
Assume transistors M18 through M21 are equal to M3 and M4 and that transistors M22
through M27 are all equal.
W28 W26 W29 W27
Let    
L28 = A  L26  and L29 = A  L27 
The output current available can be found by assuming that vin = vi1-vi2 > 0.
 i1 + i2 = I5 + A(i2-i1)
The ratio of i2 to i1 can be expressed as
i2  vin 
 
i1 = expnVt
If the output current is iOUT = b(i2-i1) then combining the above two equations gives,
  vin  
bI5expnV  - 1
  t  vin
iOUT =  iOUT =  when A = 2.16 and nV = 1
 vin  t
(1+A) - (A-1)exp 
nVt
where b corresponds to any current gain through current mirrors (M6-M4 and M8-M3).
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-12

Overdrive of the Dynamically Biased Differential Amplifier

The enhanced output current is 2
accomplished by the use of positive
feedback (M28-M2-M19-M28).
A=2
The loop gain is,
gm28gm19 gm19
LG =  g g =A
 m4  m26 gm4 = A A = 1.5

Note that as the output current increases, IOUT 1 A=1

the transistors leave the weak inversion I5
A = 0.3
region and the above analysis is no
longer valid. A=0

0
0 1 2
vIN nVt Fig. 7.4-5

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-13

Increasing the Output Current for Strong Inversion Operation

An interesting technique is to bias the output transistor of a current mirror in the active
region and then during large overdrive cause the output transistor to become saturated
causing a significant current gain.
Illustration:
530µA VGS

i1 i2

Current
i2 for W2/L2 = 5.3(W1/L1)
M1 M2 +
i2 for W2/L2 = W1/L1
+ Vds2
VGS 100µA VGS
- -
Volts
0.1Vds2(sat) Vds1(sat)=Vds2(sat)
070507-02

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-14

Example 29-2 Current Mirror with M2 operating in the Active Region

Assume that M2 has a voltage across the drain-source of 0.1Vds(sat). Design the
W2/L2 ratio so that I1 = I2 = 100µA if W1/L1 = 10. Find the value of I2 if M2 is
saturated.
Solution
Using the value of KN’ = 120µA/V2, we find that the saturation voltage of M2 is
2I1 200
Vds1(sat) = KN’ (W2/L2) = 120·10 = 0.408V
Now using the active equation of M2, we set I2 = 100µA and solve for W2/L2.
100µA = KN’(W2/L2)[Vds1(sat)·Vds2 - 0.5Vds22]
= 120µA/V2 (W2/L2)[0.408·0.0408 - 0.5·0.04082]V2 = 1.898x106(W2/L2)
Thus,
W2
100 =1.898(W2/L2) → L = 52.7 ≈ 53
2
Now if M2 should become saturated, the value of the output current of the mirror with
100µA input would be 530µA or a boosting of 5.3 times I1.
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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-15

Implementation of the Current Mirror Boosting Concept

VDD
M8
M17 M10
M7
M9 M18
M21 i1 i2 M22 M14
M13 vi1 vi2
M1 M2
M29 M30
ki1 ki2
vo1 M28 vo2
i1 i2 M27 M3 M4 i1 i2
ki2 ki1

M25 M26
+ i2 i1
M15 M23 VBias M5 M24 M16
M11 M20
M19 M12
- M6
VSS Fig.7.4-7

k = overdrive factor of the current mirror

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-16

A Better Way to Achieve the Current Mirror Boosting

It was found that when the current mirror boosting idea illustrated on the previous slide
was used that when the current increased through the cascode device (M16) that VGS16
increased limiting the increase of VDS12. This can be overcome by the following circuit.
VDD

iin+IB iin IB
kiin
M3
50/1

M5 M4
1/1 1/1

M1 M2
1/1 210/1

Fig. 7.4-7A

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-17

REVIEW OF MOSFET NOISE MODELING AND ANALYSIS

Transistor Noise Sources (Low-Frequency)
Drain current model:
D D
M1 M1
2
G G in1

M1 is M1 is
noisy S noiseless S Fig. 7.5-0A

2 8kTgm (KF)ID 2 8kTgm(1+) (KF)ID

in =  3 + 2  or in =  + 2  if vBS  0
 fC L
ox   3 fC L
ox 
gmbs
Recall that  = g
m
Gate voltage model assuming common source operation:
2 D D
2 i N  8kT KF  M1
2
en1
M1
en = 2 =  +  or
gm 3gm 2fCoxWLK’ G G *
2  8kT KF  M1 is M1 is
en =  + 2fC WLK’ if vBS  0 noiseless S
3g m (1+) ox 
noisy S
Fig. 7.5-0C

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-18

Minimization of Noise in Op Amps

1.) Maximize the signal gain as close to the input as possible. (As a consequence, only
the input stage will contribute to the noise of the op amp.)
2.) To minimize the 1/f noise:
a.) Use PMOS input transistors with appropriately selected dc currents and W and L
values.
b.) Use lateral BJTs to eliminate the 1/f noise.
c.) Use chopper stabilization to reduce the low-frequency noise.

Noise Analysis
1.) Insert a noise generator for each transistor that contributes to the noise. (Generally
ignore the current source transistor of source-coupled pairs.)
2.) Find the output noise voltage across an open-circuit or output noise current into a
short circuit.
3.) Reflect the total output noise back to the input resulting in the equivalent input noise
voltage.

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-19

LOW NOISE OP AMPS

A Low-Noise, Two-Stage, Miller Op Amp
VDD VDD
2
VSG7 en7
M10 M7 I5
M5 2
en1 2
en2 * M7

+ * M1 M2 *
vin eto2
2 2
-
M1 M2 Cc en8 M8 M9 en9
vout
M11 * *
VBias 2 VBias
+ en6
VBias M8 M9 2 2
- M6 en3 en4 M6
*
M3 M4 M3 * * M4

VSS VSS Fig. 7.5-1

2
The total output-noise voltage spectral density, eto, is as follows where gm8(eff)  1/rds1,
2  2 2  2 2 2 2 2 2 
eto = gm62RII2en6+en7 +RI2gm12en1+gm22en2+gm32en3+gm42en4 + (en8/rds12) + (en9/rds22)
2
Divide by (gm1RIgm6RII)2 to get the eq. input-noise voltage spectral density, eeq, as

2  gm32en3
2 eto
2
2en6
2 2 2
en8  2  gm32en32 
eeq = (g g R R )2 = g 2R 2 + 2en11+g   2  + 2 2en11+gm1  2 
 m1 e
m1 m6 I II m1 I g   n1 m12rds1 en1
2  en1
2 = e 2 , e 2 = e 2 , e 2 = e 2 and e 2 = e 2 and g R is large.
where en6 n7 n3 n4 n1 n2 n8 n9 m1 I
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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-20

1/f Noise of a Two-Stage, Miller Op Amp

Consider the 1/f noise:
Therefore the noise generators are replaced by,
2 B 2 2BK’Ii
eni = fW L (V2/Hz) and ini = fL 2 (A2/Hz)
i i i
Therefore, the approximate equivalent input-noise voltage spectral density is,
2 2  KN’BNL12
eeq = 2en1 1 +  K ’B L   (V2/Hz)
  P P  3 
Comments;
2
• Because we have selected PMOS input transistors, en1 has been minimized if we
choose W1L1 (W2L2) large.
• Make L1<<L3 to remove the influence of the second term in the brackets.

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-21

Thermal Noise of a Two-Stage, Miller Op Amp

Let us focus next on the thermal noise:
The noise generators are replaced by,
2 8kT 2 8kTgm
eni ≈ 3g 2
(V /Hz) and ini ≈ 3 (A2/Hz)
m
where the influence of the bulk has been ignored.
The approximate equivalent input-noise voltage spectral density is,

2 2  gm32 n3
 e
2
2  KNW3L1 
eeq = 2en11+g   2  = 2en1 1 +  (V2/Hz)
 KPW1L3 
  m1 en1
Comments:
• The choices that reduce the 1/f noise also reduce the thermal noise.
Noise Corner:
Equating the equivalent input-noise voltage spectral density for the 1/f noise and the
thermal noise gives the noise corner, fc, as
3gmB
fc = 8kTWL

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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-22

Example 29-3 Design of A Two-Stage, Miller Op Amp for Low 1/f Noise
Use the model parameters of KN’ = 120µA/V2, KP’ = 25µA/V2, and Cox = 6fF/µm2
along with the value of KF = 4x10-28 F·A for NMOS and 0.5x10-28 F·A for PMOS and
design the previous op amp with ID5 = 100µA to minimize the 1/f noise. Calculate the
corresponding thermal noise and solve for the noise corner frequency. From this
information, estimate the rms noise in a frequency range of 1Hz to 100kHz. What is the
dynamic range of this op amp if the maximum signal is a 1V peak-to-peak sinusoid?
Solution
1.) The 1/f noise constants, BN and BP are calculated as follows.
KF 4x10-28F·A
BN = = = 1.33x10-22 (V·m)2
2CoxKN’ 2·60x10 F/m ·120x10 A/V
-4 2 -6 2
and
KF 0.5x10-28F·A
BP = 2C K ’ = -4 2 -6 2 = 1.67x10-22 (V·m)2
ox P 2·60x10 F/m ·25x10 A/V
2.) Now select the geometry of the various transistors that influence the noise
performance.
2 small, let W = 100µm and L = 1µm. Select W = 10µm and L =
To keep en1 1 1 3 3
20µm and letW8 and L8 be the same as W1 and L1 since they little influence on the
noise.
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Example 29-3 - Continued

Of course, M1 is matched with M2, M3 with M4, and M8 with M9.
2 BP 1.67x10-22 1.67x10-12
 en1 = fW L = f·100µm·1µm = (V 2/Hz)
1 1 f
2 1.67x10-12  120·1.33  1  
 2 2 3.33x10-12 3.452x10-12 2
eeq = 2x 1 +      = 1.0365 = (V /Hz)
f   25·1.67  20  f f
Note at 100Hz, the voltage noise in a 1Hz band is  3.45x10-14V2(rms) or
0.186µV(rms).
3.) The thermal noise at room temperature is
2 8kT 8·1.38x10-23·300
en1 = 3g = -6 = 2.208x10-17 (V2/Hz)
m 3·500x10
which gives
2  120·10·1 
eeq = 2·2.208x10-171 +  = 4.416x10-17·1.155= 5.093x10-17 (V2/Hz)
 25·100·20 

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Example 29-3 - Continued

2
4.) The noise corner frequency is found by equating the two expressions for eeq to get
3.452x10-12
fc = = 67.8kHz
5.093x10-17
This noise corner is indicative of the fact that the thermal noise is much less than the 1/f
noise.
5.) To estimate the rms noise in the bandwidth from 1Hz to 100,000Hz, we will ignore
the thermal noise and consider only the 1/f noise. Performing the integration gives
105
3.452x10-12
Veq(rms) = 
2 df = 3.452x10 -12[ln(100,000) - ln(1)]
 f
1
= 0.408x10-10 Vrms2 = 6.39 µVrms
The maximum signal in rms is 0.353V. Dividing this by 6.39µV gives 55,279 or
94.85dB which is equivalent to more than 15 bits of resolution.
6.) Note that the design of the remainder of the op amp will have little influence on the
noise and is not included in this example.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-25

Low-Noise Op Amp using Lateral BJT’s at the Input

10
Experimental noise
performance: 8
Eq. input noise voltage of low-noise op amp
Noise (nV/ Hz)

4
Voltage noise of lateral BJT at 170 mA
2

0
10 100 1000 104 105
Frequency (Hz) Fig. 7.5-7
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-26

Summary of Experimental Performance for the Low-Noise Op Amp

Experimental Performance Value
Circuit area (1.2µm) 0.211 mm2
Supply Voltages ±2.5 V
Quiescent Current 2.1 mA
-3dB frequency (at a gain of 20.8 dB) 11.1 MHz
en at 1Hz 23.8 nV/ Hz
en (midband) 3.2 nV/ Hz
fc(en) 55 Hz
in at 1Hz 5.2 pA/ Hz
in (midband) 0.73 pA/ Hz
fc(in) 50 Hz
Input bias current 1.68 µA
Input offset current 14.0 nA
Input offset voltage 1.0 mV
CMRR(DC) 99.6 dB
PSRR+(DC) 67.6 dB
PSRR-(DC) 73.9 dB
Positive slew rate (60 pF, 10 k load) 39.0 V/µS
Negative slew rate (60 pF, 10 k load) 42.5 V/µS
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-27

Chopper-Stabilized Op Amps - Doubly Correlated Sampling (DCS)

Illustration of the use of chopper stabilization to remove the undesired signal, vu, form
the desired signal, vin.
Vu(f) Clock
+1
Vin(f) t
-1
f
vu T =1
fc
f vA vB vC vout
vin A1 A2
VA(f)

f
0 fc 2fc 3fc
VB(f)

f
0 fc 2fc 3fc
VC(f)

f
0 fc 2fc 3fc Fig. 7.5-8

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-28

Chopper-Stabilized Amplifier

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-29

Example of a Two-Stage, Chopper-Stablized Op Amp

VDD
clkb clkb
M3 M4 M6
vnn clk clkb vnp
vnp Cc vout vnn
clk clkb clk clk
clk clk
vnn M1 M2 vnp
VDD VDD
vnp vnn
VNB1 M5
M7
clkb clkb
070507-03

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-30

Experimental Noise Response of the Chopper-Stabilized Amplifier

1000
Without chopper

With chopper
fc = 16kHz
nV/ Hz

100
With chopper fc = 128kHz

10
0 10 20 30 40 50
Frequency (kHz) Fig. 7.5-11
Comments:
• The switches in the chopper-stabilized op amp introduce a thermal noise equal to kT/C
where k is Boltzmann’s constant, T is absolute temperature and C are capacitors
charged by the switches (parasitics in the case of the chopper-stabilized amplifier).
• Requires two-phase, non-overlapping clocks.
• Trade-off between the lowering of 1/f noise and the introduction of the kT/C noise.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-31

Improved Chopper Operation

In some cases, there are spurious signals in the neighborhood of the chopping
frequencies and its harmonics. These spurious signals such as common-mode
interference can mix to the baseband since the chopper amplifier is a time variant system
and therefore inherently nonlinear.
fc
A bandpass filter centered at the
Input Output
clock frequency can be used to Amplifier Amplifier
eliminate the aliasing of the spurious vin vout
signals and achieve a reduction in
Input fo Output
effective offset.
Modulator Bandpass Filter Modulator
fc - fo 041006-03
Let  = f and  be a given bound
o
of . It can be shown† that the achievable effective offset reduction, EOR, and the
optimum Q for the bandpass filter, Qopt, is
8Q
EOR = ,  <<1 and Qopt = 1/ 8
(1 + 8Q2)
Improvements of 14dB reduction in effective offset are possible for  = 0.8%.

† C. Menolfi and Q. Huang, “A Fully Integrated, Untrimmed CMOS Instrumentation Amplifier with Submicrovolt Offset,” IEEE J. of Solid-State
Circuits, vol. 34, no.8, March 1999, pp. 415-420.
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Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-32

SUMMARY
• Operation of transistors for low power op amps is generally in weak inversion
• Boosting techniques are needed to get output sourcing and sinking currents that are
larger than that available during quiescent operation
• Be careful about using circuits at weak inversion, i.e. the self-biased cascode will
cause the resistor to be too large
• Primary sources of noise for CMOS circuits is thermal and 1/f
• Noise analysis:
1.) Insert a noise generator for each transistor that contributes to the noise.
(Generally ignore the current source transistor of source-coupled pairs.)
2.) Find the output noise voltage across an open-circuit or output noise current into a
short circuit.
3.) Reflect the total output noise back to the input resulting in the equivalent input
noise voltage.
• Noise is reduced in op amps by making the input stage gain as large as possible and
reducing the noise of this stage as much as possible.
• The input stage noise can be reduced by using lateral BJTs (particularily the 1/f noise)
• Doubly correlated sampling can transfer the noise at low frequencies to the clock
frequency (this technique is used to achieve low input offset voltage op amps).
CMOS Analog Circuit Design © P.E. Allen - 2016