Design and Programming Embedded Multicore Architectures

Prof. Dr.-Ing. Diana Göhringer

Hardware Modelling and Simulation

Exercise 2
Chair of Adaptive Dynamic Systems

1) Nine-valued Logic
In the VHDL standard IEEE-1164 the 9-valued logic base type std_ulogic is defined.

a) What is the meaning of the letter ‘u‘ in the word std_ulogic?

b) Explain the values ’Z’, ’U’ and ’X’ from the type std_ulogic.

c) Which values of the type std_ulogic can occur at the output of an CMOS inverter?

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The following schematics of a pull-up resistor and an open-drain buffer are given:
yODB

Pull-Up Open-Drain
Resistor Buffer
VDD

xODB
1
RPU

VSS
yPU

d) What is the constant value of type std_ulogic that is read at yPU?

e) Fill in the following table for the output yODB depending on the input xODB of the open-
drain buffer.
xODB U X 0 1 Z W L H -
yODB

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Now a combination of the pull-up resistor (PUR) and the open-drain buffer (ODB) is given:
VDD

RPU

x1 1 x2 1

VSS VSS

f) Fill in the nine-valued logic truth table for the output y of the given design.
X1
Y
U X 0 1 Z W L H -

U U U U/0 U U U U/0 U U

X U

0 U/0

1 U

X2 Z U

W U

L U/0

H U

- U

g) Which Boolean function is realized by the design from problem (f) ?

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2) Timing in VHDL
The three signals a, b and c were derived from a single common source signal i using the three delay
models defined in VHDL. Different delay times were used.

1
a
0 t/ns
5 10 15 20 25 30
1
b
0 t/ns
5 10 15 20 25 30
1
c
0 t/ns
5 10 15 20 25 30
1
i
0 t/ns
5 10 15 20 25 30

Figure 1: Timing diagram with delayed signals

a) Which signal belongs to which delay model? Insert the correct signal names.

___ <= TRANSPORT i AFTER t;

___ <= i AFTER u;

___ <= REJECT v INERTIAL i AFTER w;

b) Determine the delay times t, u, v and w. Each of the values 2 ns, 3 ns, 4 ns and
5 ns was used exactly once.

t := ____ ns;
u := ____ ns;
v := ____ ns;
w := ____ ns;

c) Determine the shape of the source signal i and draw the waveform in the diagram above.

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3) Events and Delta Cycles

The following behavioral description in VHDL is given:

ENTITY fred IS
END fred;

ARCHITECTURE behavior OF fred IS

SIGNAL a, b : bit := '0' ;
BEGIN

PROCESS(a)
BEGIN
IF a='1' THEN b <= '1' AFTER 1 ns;
ELSE b <= NOT b;
END IF;
END PROCESS;

PROCESS(b)
BEGIN
IF b='0' THEN a <= '1';
ELSE a <= NOT a AFTER 1 ns;
END IF;
END PROCESS;

END behavior;

a) Determine for a time span from t = 0 ns through 2 ns the event lists of the signals a and b.
Take care of delta cycles. Remember that for each delta cycle Δ, new values are at first
scheduled only and will be assigned at the end of the delta cycle.

a
+1∆ +2∆ +3∆ +1∆ +2∆ +3∆ +1∆ +2∆ +3∆
0 1 2 t / ns

b
+1∆ +2∆ +3∆ +1∆ +2∆ +3∆ +1∆ +2∆ +3∆
0 1 2 t / ns
Figure 2: Event lists for signals a and b

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4) Fault Simulation
The following circuit is to be examined for stuck-at faults. It can be assumed that there will be only one
stuck-at fault at a given time.

A
a E
≥1 y
B
b
& D
c
C

a) Determine the truth table for the output y for the fault-free case and for exactly one stuck-
at-0 or stuck-at-1 fault on each of the wires A to E respectively.
Input y y with stuck-at fault
values
a b c fault A/0 B/0 C/0 D/0 E/0 A/1 B/1 C/1 D/1 E/1
free
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

b) Are there redundant faults? Give reasons for your answer!

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c) Group equivalent faults into fault classes.

Fault class Fault

f0
f1
f2
f3
f4
f5
f6

d) Set up a coverage table by marking which test pattern allows discovering which fault clas-
ses. Graphically determine an irredundant minimal coverage of test patterns that allows
verifying the circuit to be fault-free.

Input Fault class

values
a b c f0 f1 f2 f3 f4 f5 f6
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1