CSE360-Computer Interfacing

BRAC University

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 Communication Protocol
• A communication protocol is a system of rules that allow two or more
entities of a communication system to transmit information via any
kind of variation of a physical quantity.

• The protocol defines the rules, syntax, semantics

and synchronization of communication and possible error recovery
methods. Protocols may be implemented by hardware, software, or a
combination of both.
• Examples: SPI, I2C, UART, USB etc.

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.

Serial Peripheral Interface (SPI)

SPI stands for Serial Peripheral Interface
Used for moving data simply and quickly from one device to another
Master-Slave(Multiple Slaves, Single Master)
Synchronous transmission
Synchronous- Data clocked with Clock Signal
Data Rate-10mbps
Full Duplex Protocol
Low power than I2C (no need of Pull ups)
Supports Single master and multiple slaves
No hardware slave acknowledgement

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.

Master – Slave Protocol

Simple SPI Protocol Specifies 4 Signal Wires

1. Master Out Slave In (MOSI)
2. Master In Slave Out (MISO)
3. Serial Clock (SCLK)
4. Slave Select (SS)

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.

Master – Slave Protocol

SPI is a Master-Slave protocol

The Master device controls the clock (SCK)
No data is transferred unless a clock signal is present
All slaves are controlled by the master clock
The slave devices may not manipulate the clock
Master Set Slave Select low
Master Generates Clock

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.

How SPI Works

Single master – single slave

Timing diagram
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.

How SPI Works

Single master – Multiple slaves

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.

How SPI Works

Single master – Multiple slaves

Although the system becomes more simple, the time taken for the data
to travel to the destined node increases. 8
.

How SPI Works

In summary the steps of SPI:
1. The master outputs the clock signal
2. The master switches the SS/CS pin to a low voltage state, which
activates the slave
3. The master sends the data one bit at a time to the slave along the MOSI
line. The slave reads the bits as they are received
4. If a response is needed, the slave returns data one bit at a time to the
master along the MISO line. The master reads the bits as they are received

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.

SPI
Advantages:
Full duplex protocol. Separate MISO and MOSI lines, so data can be sent
and received at the same time
No start and stop bits, so the data can be streamed continuously without
interruption
No complicated slave addressing system like I2C
Higher data transfer rate than I2C (almost twice as fast)
Not Limited to 8 bit words in case of bit transferring
Arbitrary choice of message size, content and Purpose
Low Power

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.

SPI
Disadvantages:
Requires more pins than I2C
No hardware flow control
No Slave Acknowledgement
Multi Master Difficult to Implement
No form of error checking like the parity bit in UART
It usually requires separate SS lines to each slave, which can be
problematic if numerous slaves are needed.

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.

SPI
SPI Peripherals:
Converters (ADC, DAC)
Memories (EEPROM, RAM’s, Flash)
Sensors (Temperature, Humidity, Pressure)
Real Time Clocks
Misc.- Potentiometers, LCD controllers, UART’s, USB controller, CAN
controller, amplifiers

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.

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.

UART
Introduction:
Universal Asynchronous Receiver/Transmitter
It also called Serial Communication Interface(SCI)
Full-duplex communication.
Asynchronous communication.
Compatible with PC .
The Standard bit rates are: 100, 200, 300, 1200, 2400, 4800, 9600,
19200, 38400, 57600, 115200 bps.
Example: Connecting GPS modules, Bluetooth modules, and RFID card
reader modules to Raspberry Pi, Arduino, or other microcontrollers.

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.

UART
A UART’s main purpose is to transmit and receive serial data.
One of the best things about UART is that it only uses two wires to
transmit data between devices

Why UART?
A UART may be used when:-
• High speed is not required
• An inexpensive communication link between two devices is required.
UART communication is very cheap:-
• Single wire for each direction(and ground wire).
• Simple hardware.

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.

UART
In UART communication, two UARTs communicate directly with each
other. Data flows from the Tx pin of the transmitting UART to the Rx pin
of the receiving UART:

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.

UART

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.

UART
The transmitting UART converts parallel data from a controlling device
like a CPU into serial form, transmits it in serial to the receiving UART,
which then converts the serial data back into parallel data for the
receiving device.

The UART that is going to transmit data receives the data from a data
bus. The data bus is used to send data to the UART by another device like
a CPU, memory, or microcontroller. Data is transferred from the data bus
to the transmitting UART in parallel form. After the transmitting UART
gets the parallel data from the data bus, it adds a start bit, a parity bit,
and a stop bit, creating the data packet.

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.

UART
Next, the data packet is output serially, bit by bit at the Tx pin. The
receiving UART reads the data packet bit by bit at its Rx pin. The
receiving UART then converts the data back into parallel form and
removes the start bit, parity bit, and stop bits. Finally, the receiving UART
transfers the data packet in parallel to the data bus on the receiving end.
When the receiving UART detects a start bit, it starts to read the
incoming bits at a specific frequency known as the baud rate. Baud rate
is a measure of the speed of data transfer, expressed in bits per second
(bps).
Both UARTs must operate at about the same baud rate. The baud rate
between the transmitting and receiving UARTs can only differ by about
10% before the timing of bits gets too far off.

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.

How UART Communicate?

START BIT: The UART data transmission line is normally held at a high voltage level when it’s
not transmitting data.
• To start the transfer of data, the transmitting UART pulls the transmission line from high to
low for one clock cycle.
• When the receiving UART detects the high to low voltage transition, it begins reading the
bits in the data frame at the frequency of the baud rate.

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.

How UART Communicate?

DATA FRAME: The data frame contains the actual data being transferred. It can be 5 bits up to 8 bits long if a
parity bit is used.
If no parity bit is used, the data frame can be 9 bits long. In most cases, the data is sent with the least
significant bit first.

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.

How UART Communicate?

PARITY: Parity describes the evenness or oddness of a number.

• The parity bit is a way for the receiving UART to tell if any data has changed during transmission(Bits
can be changed by electromagnetic radiation, mismatched baud rates, or long distance data
transfers).
• After the receiving UART reads the data frame, it counts the number of bits with a value of 1 and
checks if the total is an even or odd number.
• If the parity bit is a 0 (even parity), the 1 bits in the data frame should total to an even number. If the
parity bit is a 1 (odd parity).
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.

How UART Communicate?

STOP BITS: To signal the end of the data packet, the sending UART drives the data transmission line from a
low voltage to a high voltage for at least two bit durations

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STEPS OF UART TRANSMISSION

• The transmitting UART receives data in parallel from the data bus.

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.

STEPS OF UART TRANSMISSION

• The transmitting UART adds the start bit, parity bit, and the stop bit(s)
to the data frame.

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.

STEPS OF UART TRANSMISSION

• The entire packet is sent serially from the transmitting UART to the
receiving UART. The receiving UART samples the data line at the
pre-configured baud rate.

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.

STEPS OF UART TRANSMISSION

• The receiving UART discards the start bit, parity bit, and stop bit from
the data frame.

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.

STEPS OF UART TRANSMISSION

• The receiving UART converts the serial data back into parallel and
transfers it to the data bus on the receiving end.

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UART
ADVANTAGES
• Only uses two wires
• No clock signal is necessary
• Has a parity bit to allow for error checking
• The structure of the data packet can be changed as long as both sides are set up for it
• Well documented and widely used method

DISADVANTAGES
• The size of the data frame is limited to a maximum of 9 bits
• Doesn’t support multiple slave or multiple master systems

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(Inter-Integrated Circuit)
 I2C Bus
• I2C is not only used on single boards but also to connect
components which are linked via cable. Simplicity and flexibility are
key characteristics that make this bus attractive to many
applications.
Most significant features include:
• Only two bus lines are required: SDA (Serial Data), SCL (Serial
Clock)
• No strict baud rate requirements like for instance with RS232, the
master generates a bus clock
• Simple master/slave relationships exist between all components
Each device connected to the bus is software-addressable by a
unique address
• I2C is a true multi-master bus providing arbitration and collision
detection
Timing Diagram of I2C data transmission
 I2C Bus
I2C Protocol (Basics) Messages are broken up into two types of
frame:
• Address frame: The master indicates the slave to which the
message is being sent
• Data frame: These are 8-bit data messages passed from master to
slave or vice versa.
Data is placed on the SDA line after SCL goes low, and is sampled
after the SCL line goes high.
 I2C Bus
Start Condition
• To initiate the address frame, the master device leaves SCL high
and pulls SDA low.
• This puts all slave devices on notice that a transmission is about to
start.
• If two master devices wish to take ownership of the bus at one
time, whichever device pulls SDA low first wins the race and gains
control of the bus.
• It is possible to issue repeated starts, initiating a new
communication sequence without relinquishing control of the bus
to other masters
 I2C Bus
Address Frame
• The address frame is always first in any new communication
sequence.
• For a 7-bit address, the address is clocked out most significant bit
(MSB) first, followed by a R/W bit indicating whether this is a read
(1) or write (0) operation.
 I2C Bus
NACK/ACK bit
• It is the 9th bit of the frame
• This is the case for all frames (data or address).
• Once the first 8 bits of the frame are sent, the receiving device is
given control over SDA.
• If the receiving device does not pull the SDA line low before the
9th clock pulse, it can be inferred that the receiving device either
did not receive the data or did not know how to parse the message.
• In that case, the exchange halts, and it’s up to the master of the
system to decide how to proceed.
 I2C Bus
Data Frames
• After the address frame has been sent, data can begin being transmitted.
• The master will simply continue generating clock pulses at a regular interval,
and the data will be placed on SDA by either the master or the slave, depending
on whether the R/W bit indicated a read or write operation.
Stop condition
• Once all the data frames have been sent, the master will generate a stop
condition.
• Stop conditions are defined by a 0->1 (low to high) transition on SDA after a
0->1 transition on SCL, with SCL remaining high.
• During normal data writing operation, the value on SDA should not change
when SCL is high, to avoid false stop conditions.
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 STEPS OF I2C DATA TRANSMISSION
1. The master sends the start condition to every connected slave by switching
the SDA line from a high voltage level to a low voltage level before switching the
SCL line from high to low.
2. The master sends each slave the 7 or 10 bit address of the slave it wants to
communicate with, along with the read/write bit.
3. Each slave compares the address sent from the master to its own address. If
the address matches, the slave returns an ACK bit by pulling the SDA line low for
one bit. If the address from the master does not match the slave’s own address,
the slave leaves the SDA line high.
4. The master sends or receives the data frame.
5. After each data frame has been transferred, the receiving device returns
another ACK bit to the sender to acknowledge successful receipt of the frame.
6. To stop the data transmission, the master sends a stop condition to the slave
by switching SCL high before switching SDA high.
Single Master – Multiple Slave Multiple Master – Multiple Slave
 Advantages
• I2C communication or protocol has a significant edge over its peers such as serial
port communication and SPI. Let us have a look into the various advantages that
renders the I2C protocol so effective for short distance intra-board
communication.
• 1. Flexibility – The I2C protocol supports multi-master, multi-slave
communication, which implies you can add a lot of functionality to your design.
More than one master IC controlling and communicating with the slave ICs can
speed things up and add functionalities to the embedded system.
• 2. Addressing feature – Yet another advantage of the I2C protocol lies in its
inherent ability to use chip addressing. It means that you can easily add
components to the bus without any complexity. It eliminates the necessity of SS
(Slave select) lines.
• 3. Simplicity – I2C protocol doesn’t complicate the design. It requires only two
bidirectional signal lines to establish communication among multiple devices.
Further, the pin count is low as well.
• 4. Better error handling mechanism – To improve the error detection and
correction mechanism, the I2C protocol relies on ACK/NACK feature, which is a
robust error correction feature. ACK stands for Acknowledgement whereas NACK
means No Acknowledgement.
• 5. Adaptable – The I2C protocol is adaptable in the sense that it can work well
with both slow ICs and fast ICs.
Disadvantages
1. Conflicts – Due to chip addressing, there’s always a possibility of an
address conflict.
2. Slower speeds – Slower data transfer rate than SPI
3. Requires more space – More complicated hardware needed to
implement than SPI
4. Size of Data Frame - Limited to 8 bits.
.

Thank You
For Your Attention

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 STM32 Microcontroller

Prepared by Md. Khalilur Rahman PhD, Professor and Umme Jannat Taposhi, Lecturer
Department of Computer Science and Engineering, BRAC University
STM32 Nucleo Board
● 144 pin board
STM32 Nucleo Board
● 64 pin board
STM32F446RE

ARM Cortex-M4 Microprocessor

STM32F446RE Board
Why ARM processor?
● Engineering
● IoT research
● Economy of Bangladesh
● Industry machinery
● Program almost all machine around us
● High level hardware (ARM processor building - Trillion $ market)
ARM Cortex-M4
● 32 bit microprocessor with FPU [Floating Point Unit] core
● Flash Memory & RAM associated (on-board)
● Peripheral port/devices

Word: data of 32-bit length.

Half-word: data of 16-bit length.

Byte: data of 8-bit length.

Double word: data of 64-bit length.

Key Features of the ARM Cortex-M4 Core in STM32F446RE
1. Core Architecture

ARM Cortex-M4: A 32-bit RISC processor core designed for high performance and low power
consumption.

DSP Instructions: The Cortex-M4 includes a set of digital signal processing (DSP) instructions that
enhance its performance in applications requiring complex mathematical computations.

Floating Point Unit (FPU): Supports single-precision floating-point operations, which is beneficial for
applications involving arithmetic operations with real numbers.
Key Features of the ARM Cortex-M4 Core in STM32F446RE
2. Performance
Clock Speed: Can operate at up to 180 MHz, providing high processing power for complex
applications.
Harvard Architecture: Features separate instruction and data buses, allowing simultaneous access
to memory and instructions.

3. Memory
Flash Memory: 512 KB of on-chip Flash memory for program storage.
SRAM: 128 KB of SRAM for data storage.
Memory Protection Unit (MPU): Enhances security by allowing control over memory access
permissions.
Key Features of the ARM Cortex-M4 Core in STM32F446RE
4. Interrupt System

Nested Vectored Interrupt Controller (NVIC): Supports efficient handling of interrupts

SysTick Timer: A dedicated timer for generating system ticks, useful for real-time operating systems

5. Peripherals

Timers: Multiple general-purpose timers, advanced-control timers, and basic timers for timing and
counting applications.

Analog Peripherals: Includes ADCs (Analog-to-Digital Converters), DACs (Digital-to-Analog

Converters), and comparators.
Key Features of the ARM Cortex-M4 Core in STM32F446RE
7. Communication Interfaces:

UART/USART: For asynchronous and synchronous serial communication.

SPI: For synchronous serial communication with peripherals like sensors and memory devices.

I2C: For communication with low-speed peripherals.

CAN: For automotive and industrial communication networks.

USB: Supports both Host and Device modes.

GPIO: General-purpose input/output pins for interfacing with external components.

Key Features of the ARM Cortex-M4 Core in STM32F446RE
8. Debug and Trace

Embedded Trace Macrocell (ETM): Provides real-time trace capabilities for debugging complex
applications.

Serial Wire Debug (SWD): A two-pin protocol for debugging, offering a reduced pin count compared
to JTAG.
STM32F446RE Block Diagram of the System Architecture

For better view click

on this.

peripheral.jpg
System Architecture [Simplified - Only AHB1]
• DMA: Direct Memory Access
• AHB: Advanced High-performance Bus
• APB: Advanced Peripheral Bus
• RCC: Reset and Clock Control
• CRC: Cyclic Redundancy Check
• PWM: Pulse width Modulation
• USART: universal synchronous/
asynchronous receiver/transmitter
• SPI: Serial Peripheral Interface
• I2C: Inter-Integrated Circuit
• ADC: Analog to Digital Converter
Memory & Bus Architecture
● I-bus: This bus connects the Instruction bus of the Cortex M4 with FPU core to the
Bus Matrix. Fetches instructions from memory to the CPU.

● D-bus: This bus connects the databus of the Cortex M4 with FPU core to the Bus
Matrix. Handles data read/write operations between CPU and memory.The target
of this bus is a memory containing code or data.

● S-bus: This bus connects the system bus of the Cortex M4 with FPU core to the Bus
Matrix. This bus is used to access data located in a peripheral or in SRAM. Accesses
system-level resources, peripherals, and control register (less efficient than I-bus).
Memory & Bus Architecture
● DMA, Flash MEM, External MEM, SRAM
● AHB Bus Matrix
● APB Buses: The two APB bridges, APB1 and APB2, provide full synchronous connections
between the AHB and the two APB buses, allowing flexible selection of the peripheral
frequency. After each device reset, all peripheral clocks are disabled (except for the SRAM and
Flash memory interface). Before using a peripheral you have to enable its clock in the
RCC_AHBxENR or RCC_APBxENR register.
CRC & RCC
Cyclic Redundancy Check (CRC)
The CRC calculation unit is used to get a CRC code from a 32-bit data word and a
fixed generator polynomial. Among other applications, CRC-based techniques are
used to verify data transmission or storage integrity.
Reset and Clock Control (RCC)
There are three types of reset
1. System Reset
2. Power Reset
3. Backup domain Reset
To use different IO ports, NEED TO CONFIGURE DIFFERENT REGISTERS

● RCC AHB Peripheral Clock Enable Register

● GPIO Registers
○ Four configuration registers
○ Two data registers
○ Set/reset register
○ Locking register
○ Two alternate function selection
RCC AHB Peripheral Clock Enable Register [RCC->AHB1ENR]
● 32 bit register
● Can enable port any digital I/O port [A-H]
● Can enable DMAs
● Can enable CRC
RCC AHB Peripheral Clock Enable Register [RCC->AHB1ENR]

BIT 0 - GPIOA EN: I/O port A clock enable Example:

0: IO port A clock disabled RCC->AHB1EN |= 1<<0 [Port A activated]
1: IO port A clock enabled

BIT 1 - GPIOB EN: I/O port B clock enable

RCC->AHB1EN |= 1<<3 [Port D activated]
0: IO port B clock disabled
1: IO port B clock enabled

…….. and so on
General Purpose I/0 [GPIO]
Each general-purpose I/O port has -
● A four 32-bit configuration registers
● GPIOx_MODER: Mode Register
● GPIOx_OTYPER : Output Type Register
● GPIOx_OSPEEDR : Output Speed Register
● GPIOx_PUPDR) : Pull-up, Pull-Down Register
● Two 32-bit data registers
● GPIOx_IDR: Input Data Register
● GPIOx_ODR: Output Data Register
● A 32-bit set/reset register (GPIOx_BSRR),
● A 32-bit locking register (GPIOx_LCKR)
● Two 32-bit alternate function selection
● GPIOx_AFRH: Alternetive Register High
● GPIOx_AFRL : Alternetive Register Low
Main features of GPIO
● Up to 16 I/Os under control
● Output states: push-pull or open drain + pull-up/down
● Output data from output data register (GPIOx_ODR) or peripheral (alternate function output)
● Speed selection for each I/O
● Input states: floating, pull-up/down, analog
● Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
● Bit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR
● Locking mechanism (GPIOx_LCKR) provided to freeze the I/O configuration
● Analog function
● Alternate function input/output selection registers (at most 16 AFs per I/O)
● Fast toggle capable of changing every two clock cycles
● Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several periphe
functions
Internal Interfacing Unit of each GPIO PORT
 GPIO

Alternate
Input Output
Function

Communic
Digital Analog Digital Time
ation
Input Input Output (PWM)
Protocol

Speed
Input Input Input-pull-d (Low,
USART SPI I2C CAN
floating pull-up own Medium,
Fast, High)

Push Pull Open Drain

No pull
Pull-up Pull-down
up/down
1. GPIO Configuration Registers (IO Mode Register)
GPIOx_MODER ( x = A..H ) : These bits configure the I/O direction mode.

• 00: Input (reset state)

• 01: General purpose output mode
• 10: Alternate function mode
• 11: Analog mode

Bit [0..31]: MODERy[1:0]: Port x configuration bits (y = pin = 0...15)

1. GPIO Configuration Registers (Output Type Register)
GPIOx_OTYPER (x=A..H):These bits are written by software to configure the output type of the I/O port.

● 0: Output push-pull (reset state)

● 1: Output open-drain

Bits 31:16 - Reserved

Bits 15:0 - OTy: Port x configuration bits (y = 0..15)
1. GPIO Configuration Registers (Output Speed Register)
GPIOx_OSPEEDR (x=A..H): These bits are to configure the I/O output speed.

● 00: Low speed

● 01: Medium speed
● 10: Fast speed
● 11: High speed

OSPEEDRy[1:0]: Port x configuration bits (y = 0..15)

1. GPIO Configuration Registers (Pull-up Pull-down Register)
GPIOx_PUPDR (x=A..H): These bits are written to configure the I/O input pull-up or pull-down

● 00: No pull-up, pull-down

● 01: Pull-up
● 10: Pull-down
● 11: Reserved

Bits[0..31] - PUPDRy[1:0]: Port x configuration bits (y = 0..15)

2. Data Registers (Input Data Register)
GPIOx_IDR (x=A..H): These bits are read-only. They contain the input value of the corresponding I/O port.

Bits 31:16 - Reserved

Bits 15:0 - IDRy: Port input data (y = 0..15)

2. Data Registers (Output Data Register)
GPIOx_ODR (x=A..H): These bits can be read and written

Bits 31:16 - Reserved

Bits 15:0 - ODRy: Port output data (y = 0..15)

Note: For atomic bit set/reset, the ODR bits can be individually set and
reset by writing to the GPIOx_BSRR register (x = A..H).
 3. Set/Rest Register (Bit Set Reset Register)
GPIOx_BSRR (x=A..H): These bits are write-only and can be accessed in word, half-word or byte mode.

Bits 15:0 - BSy: Port x set bit y (y= 0..15)

Bits 31:16 - BRy: Port x reset bit y (y = 0..15)
• 0: No action on the corresponding ODRx bit
• 0: No action on the corresponding ODRx bit
• 1: Sets the corresponding ODRx bit
• 1: Resets the corresponding ODRx bit

Note: If both BSx and BRx are set, BSx has priority.
4. Locking register Register
GPIOx_LCKR: (x=A..H): Using this register, you can freeze the GPIO configurations. Once you do the proper lock
key write sequence, it will lock the GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL, and
GPIOx_AFRH registers.
Bits [15:0] – LCKy: Port Set Bit, (y = 0 … 15)
● 0 – Port configuration is not locked
● 1 – Port configuration is locked
Bits [16] – LCKK: Lock Key
● 0 – Port configuration lock key is not active
● 1 – Port configuration lock key is not active
5. Alternate function selection Register
GPIOx_AFRL: (x=A..H) , GPIOx_AFRH: (x=A..H): Each GPIO pin has around sixteen alternative
functions like SPI, I2C, UART, etc. So we can tell the STM32 to use our required functions.

● GPIOx_AFRL 32-bit register is grouped by 4 bits. So This GPIOx_AFRL register is used to select the
alternate functions of Pin 0 to Pin 7
● GPIOx_AFRH 32-bit register is also grouped by 4 bits. So This GPIOx_AFRH register is used to select
the alternate functions of Pin 8 to Pin 15

● 0000: AF0 (Alternate Function 0)

● 0001: AF1 (Alternate Function 1)

● 0010: AF2 (Alternate Function 2)

● 0011: AF3 (Alternate Function 3)

● .

● .
THANK YOU!