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8086 S01 - Internal Architecture

The document provides an overview of the 8086 microprocessor, detailing its features such as being a 16-bit processor with a 20-bit address bus and the ability to access up to 1 MB of memory. It describes the internal architecture, which includes the Bus Interface Unit (BIU) and Execution Unit (EU), along with their respective functions and components. Additionally, it outlines the general-purpose registers and their roles in data processing and instruction execution.

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Mir Mashrafi Ahasan
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37 views33 pages

8086 S01 - Internal Architecture

The document provides an overview of the 8086 microprocessor, detailing its features such as being a 16-bit processor with a 20-bit address bus and the ability to access up to 1 MB of memory. It describes the internal architecture, which includes the Bus Interface Unit (BIU) and Execution Unit (EU), along with their respective functions and components. Additionally, it outlines the general-purpose registers and their roles in data processing and instruction execution.

Uploaded by

Mir Mashrafi Ahasan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Embedded Systems

And Interfacing

Introduction to 8086 Microprocessor


Features of 8086

● Designed by Intel during 1976 to 1978


● 16-bit microprocessor
● 16-bit data bus
● 20-bit address bus
● Available in 3 versions based on the frequency of operation
○ 8086 → 5MHz
○ 8086-2 → 8MHz
○ (c)8086-1 → 10MHz
● Byte addressable memory
● Can access up to 1 Mb of memory
● Fourteen 16-bit registers
● Multiplexed address and data bus (AD0-AD15 and A16-A19)
Computer Bus
Internal Architecture of 8086
Internal Architecture of 8086

● 8086 CPU is divided into two


independent functional parts:
○ Bus Interface Unit (BIU)
○ Execution Unit (EU)
Internal Architecture of 8086
● Bus Interface Unit (BIU)
○ It generates the 20-bit physical address for memory access.
○ It fetches instructions from the memory.
○ It transfers data to and from the memory and I/O.
○ Maintains the 6-byte pre-fetch instruction queue(supports
pipelining).

BIU mainly contains the 4 Segment registers, the Instruction Pointer, a pre-
fetch queue, and an Address Generation Circuit.

● Execution Unit (EU)


○ Tells BIU where to fetch instructions/data from
○ Decodes instructions
○ Executes instructions
The BUS Interface Unit (BIU)
The BUS Interface Unit (BIU)
The
Queue
The BUS Interface Unit (BIU)
The QUEUE
● BIU fetches upto six instruction bytes for the successive
instructions into the queue
● Fetching the next instruction while the current instruction
executes is called pipelining
The BUS Interface Unit (BIU)
Segment Registers
The BUS Interface Unit (BIU)
Segment Registers

16 0
Extra Segment ES
Code Segment CS

SS
Stack Segment
DS
Data Segment
The BUS Interface Unit (BIU)
Segment Registers
The BUS Interface Unit (BIU)
Special Purpose Registers

Instruction Pointer IP
The BUS Interface Unit (BIU)
Special Purpose Registers

Instruction Pointer IP

● IP - the instruction pointer:


○ Always points to next instruction to be executed
○ Offset address relative to CS
The BUS Interface Unit (BIU) -
Address Generation Circuit
The Execution Unit (EU)
The Execution Unit (EU)

● The main components of the EU are General purpose registers,


the ALU, Special purpose registers, the Instruction Register and
Instruction Decoder, and the Flag/Status Register.
The Execution Unit (EU)
The Execution Unit (EU)
Instruction
Decoder
The Execution Unit (EU)
Instruction
Decoder

ALU
The Execution Unit (EU)

● Instruction Decoder translates instructions fetched from


memory into a series of actions
● ALU performs addition, subtraction, AND, OR, XOR, increment,
decrement, complement, and shift
● Registers holds significant information (data or address)
The Execution Unit (EU)
Instruction
Decoder

ALU

Registers
The Execution Unit (EU)
Flag Register
The Execution Unit (EU)
General Purpose Registers
The Execution Unit (EU)
General Purpose Registers
16 8/7
0
AH AL
AX
BH BL
BX
CH CL
CX
DH DL
DX
16 0
Stack Pointer SP

Base Pointer BP

Source Index SI

Destination Index DI
The Execution Unit (EU)
General Purpose Registers
● AX - the accumulator register (divided into AH / AL):
○ Arithmetic, logic and data transfer
○ One number must be in AL or AX
○ Multiplication & Division
○ Input & Output

● BX - the base address register (divided into BH / BL).


The Execution Unit (EU)
General Purpose Registers
● CX - the count register (divided into CH / CL):
○ Iterative code segments using the LOOP instruction
○ Repetitive operations on strings with the REP command
○ Count (in CL) of bits to shift and rotate

● DX - the data register (divided into DH / DL):


○ DX:AX concatenated into 32-bit register for some MUL and DIV operations
○ Specifying ports in some IN and OUT operations
The Execution Unit (EU)
General Purpose Registers
● SP - stack pointer:
○ Always points to top item on the stack
○ Offset address relative to SS
○ An empty stack will have SP = FFFEh

● BP - base pointer:
○ Primarily used to access parameters passed via the stack
○ Offset address relative to SS
The Execution Unit (EU)
General Purpose Registers
● SI - source index register:
○ Can be used for pointer addressing of data
○ Used as source in some string processing instructions
○ Offset address relative to DS

● DI - destination index register:


○ Can be used for pointer addressing of data
○ Used as destination in some string processing instructions
○ Offset address relative to ES
Resources

● Architecture of 8086 - GeeksforGeeks


● Barry B Brey - Chapter 2

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