Lab 2 AXI Peripherals

Objective
After completing this lab, you will be able to:
 Use the IP Packager feature of Vivado to create a custom peripheral
 Modify the functionality of the IP
 Add the custom peripheral to your design
 Add pin location constraints
 Add block memory to the system
Create a Custom IP using the Create and Package IP Wizard

1. Open Vivado by selecting Start > All Programs > Xilinx Design Tools > Vivado 2020.2 >
Vivado 2020.2

2. Click Manage IP and select New IP Location and click Next in the New IP Locationwindow
3. Select VHDL as the Target Language, Mixed as the Simulator language, and for IP location,
type
{labs}\led_ip and click Finish (leave other settings as defaults and click OK if prompted to
create the directory)

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Run the Create and Package IP Wizard
1. Select Tools > Create and Package IP
2. In the window, click Next
3. Select Create a new AXI4 peripheral, and click Next
4. Fill in the details for the IPName: led_ip
Display Name: led_ip_v1_0
(Fill in a description, Vendor Name, and URL)

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5. Click Next
6. Change the Name of the interface to S_AXI
7. Leave the other settings as default and click Next (Lite interface, Slave mode, DataWidth: 32,
Number of Registers: 4)

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8. Select Edit IP and click Finish (a new Vivado Project will open)

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 Create an interface to the LEDs
1. In the sources panel, double-click the led_ip_v1_0.vhd file.
This file contains the HDL code for the interface(s) selected above. The top level file contains a
module which implements the AXI interfacing logic, and an example design to write and to read from
the number of registers specified above. This template can be used as a basis for creating custom IP. A
new parameterized output port to the LEDs will be created at the top level of the design, and the AXI
write data in the sub-module will be connected back up to the external LED port.
Scroll down to line 7 where a user parameters space is provided.
2. Add the line:

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3. Go to line 18 and add the line:

4. Insert the following at line ~53:

5. Insert the following at line ~58:

6. Insert the following at line ~89:

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7. Insert the following at line ~93:

8. Save the file by selecting File > Save File

9. Expand led_ip_v1_0 in the sources view if necessary, and open led_ip_v1_0_S_AXI.vhd

10. Add the LED parameter and port to this file too, at lines 7 and 18 (done in steps 2 ands 3)
11. Scroll down to ~line 387 and insert the following code to instantiate the user logic for theLED
IP (This code can be typed directly, or copied from the user_logic_instantiation.txt file in the
lab3 source folder.)

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 12. Save the file by selecting File > Save File
13. Click Run Synthesis and Save if prompted. (This is to check the design synthesizes
correctly before packaging the IP. If this was your own design, you would simulate it and verify
functionality before proceeding)
14. Check the Messages tab for any errors and correct if necessary before moving to the next
step
15. When Synthesis completes successfully, click Cancel.
Package the IP
1. Click on the Edit Package IP – led_ip tab

Package IP

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Skip the next two steps (2 and 3) if you see /Basic_Elements under the Categories section, (like the one
shown in figure)

2. For the IP to appear in the IP catalog in particular categories, the IP must be configured to be
part of those categories. To change which categories the IP will appear in the IP catalog click
Blue Plus (Red box shown in the figure) in the Categories section. This opens the Choose IP
Categories window
3. For the purpose of this exercise, uncheck the AXI Peripheral box and check the Basic Elements
and click OK.
4. Select Compatibility. This shows the different Xilinx FPGA Families that the IP supports. The
value is inherited from the device selected for the project.
5. Click the Blue Plus then Add Family Explicitly… from the menu.
6. Select the Artix-7 family as we will be using this IP on the AC701 Dev Kit, and click OK. You
will get something like this:

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 Compatibility under Package IP
7. You can also customize the address space and add memory address space using the IP
Addressing and Memory category. We won’t make any changes.
8. Click on File Groups and click Merge changes from File Groups Wizard

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 9. Click on Customization Parameters and again Merge changes from Customization Parameters
Wizard Notice that the Ports and Interfaces view now shows the user createdLED port
10. Select Customization Parameters, expand Hidden Parameters, right-click on LED_WIDTH,
and select Import IP Parameters… and click OK.
11. Select Customization GUI and notice that the Led Width is visible.

Customization GUI under Package IP

12. Select Review and Package, and notice the path where the IP will be created.
13. Click Package IP. Click Yes and the project will close when complete.
14. In the original Vivado window click File > Close Project.
Create Testbench
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1. Create a new project by File > New Project > Next
2. Change the project name and click Next
3. Choose RTL project and click Next.

4.

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5. In the next screen, change “target language” to “verilog” and click Next.
6. On “Add constraint screen”, click Next
7. In the “default part screen”, click Board and type Arty A7 in the search. Then, selectArty A7
board and click Next.

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8. To finish creating new project, click on “Finish”.Create the SystemVerilog testbench

9. In “Flow Navigator”, click on “settings” to add the IP to the project. Expand theIP catalog and
select repository.

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10. Add the folder that we have created our IPs and click OK.

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11. In “Flow navigator”, click on “Create block Design” then select “OK”. A new board design is
created.

12. Add “AXI Verification IP” and our LED IP by right click and choose “add IP”.

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 13. Customize “AXI Verification IP” by double click on AXI Verification IP and change the
interface mode to master then click OK.

14. Right click on aclk of AXI Verification IP and choose “Make External”. Repeat this for aresetn pin.
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15. Connect the master AXI interface to the LED IP slave interface by clicking on the M_AXI port
and hold the mouse then connect to the S_AXI port. Repeat for s_axi_aclk and s_axi_aresetn.

16. In the address editor, click on “Audo Assign Address button” and change the address of the LED
IP to 0xC0000000.

17. Right click on “design_1” in the design sources, and choose “Create HDL wrapper” and click
“OK”.

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18. Add a SystemVerilog source file by clicking on “Source” tab, right click on Sim_1 and choose
“add source file”

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19. Choose “add or create simulation source” and click Next.

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20. Create a new file “led_ip_tb.sv” and select OK.

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21. Click on Finsh to create the file.

In the “Define Module” window, click on “OK” to create the testbench.

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Click on “led_ip_tb.sv” on the simulation source and change it as the following.

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/10/2021 06:36:23 PM
// Design Name:
// Module Name: led_ip_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
import axi_vip_pkg::*;
import design_1_axi_vip_0_0_pkg::*;

module led_vip_sim(

);
bit aclk = 0;
bit aresetn = 0;
xil_axi_ulong addr1=32'hC0000000, addr2=32'hC0000004;
xil_axi_prot_t prot = 0;
bit [31:0] data_wr1=32'h01234567, data_wr2=32'h89ABCDEF;

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 bit [31:0] data_rd1, data_rd2;
xil_axi_resp_t resp;

always #5ns aclk = ~aclk;

design_1_wrapper DUT (.aclk_0(aclk), .aresetn_0(aresetn));

design_1_axi_vip_0_0_mst_t master_agent;

initial begin
//Create an agent
master_agent = new("master vip
agent",DUT.design_1_i.axi_vip_0.inst.IF);

// set tag for agents for easy debug

master_agent.set_agent_tag("Master VIP");

// set print out verbosity level.

master_agent.set_verbosity(400);

//Start the agent

master_agent.start_master();

#50ns
aresetn = 1;
#20ns
master_agent.AXI4LITE_WRITE_BURST(addr1,prot,data_wr1,resp);

#20ns
master_agent.AXI4LITE_WRITE_BURST(addr2,prot,data_wr2,resp);

#70ns
master_agent.AXI4LITE_READ_BURST(addr1,prot,data_rd1,resp);

#20ns
master_agent.AXI4LITE_READ_BURST(addr2,prot,data_rd2,resp);
#200ns
if((data_wr1 == data_rd1)&&(data_wr2 == data_rd2))
$display("Data match, test succeeded");
else
$display("Data do not match, test failed");

$finish;
end
endmodule

Click File > Save

Run simulation using XSIM in Vivado

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Click on “Run simulation” in the Flow Navigator to start the simulation using XSIM.

Run Simulation with Questasim

Change the simulator in the project settings. Click on Setting >> simulation >> selectQuestasim
Advanced Simulator. A warning pops up choose Yes and OK.

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Compile Xilinx simulation library using Questasim by clicking on Tools >> Compile Simulation Library

Change the family to Artix-7 and click on “compile”.

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Wait until all the libraries are compiled.
After the compilation completes, choose “run simulation” to start the simulation inquestasim.

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Fix bugs for Windows

May encounter errors in later labs if you are using a Windows machine.
1. Browse to open the file
{labs}\led_ip\ip_repo\led_ip_1.0\drivers\led_ip_v1_0\src\Makefile
2. Change line 12 ~ 14 to
INCLUDEFILES=ledip.h
LIBSOURCES=ledip.c ledip_selftest.c
OUTS = ledip.o ledip_selftest.o
3. Save and close the file.
Modify the Project Settings.

1. Start the Vivado if necessary and open the project that you created in the previous lab.

2. Select File > Project > Save As… to open the Save Project As dialog box. Enter lab4 as the project
name. Make sure that the Create Project Subdirectory option is checked, the project directory
path is {labs} and click OK.

3. Click Settings in the Flow Navigator pane.

4. Select IP > Repository in the left pane of the Project Settings form.

5. Click on the Blue Plus button, browse to {labs}\led_ip and click Select. The led_ip_v1.0 IP will
appear the IP in the Selected Repository window.
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Launch the Vistis
1. Click File > Export > Export Hardware.
2. Click on the checkbox of Include the bitstream and click Finish.
3. Select Tools > Launch Vitis IDE and click OK.
4. Select File > New > Application Project. Click Next to skip the welcome page if necessary.
5. In the Platform Selection window, select Create a new platform from hardware (XSA) and
browse to select the {labs}\lab4\**_wrapper.xsa file exported before.
6. Enter lab4platform** as the _Platform name, click **Next.
7. Enter lab4 as the Project Name. Click Next.
8. Select the domain with name standalone, click Next.
9. Click Next, and select Empty Application(C) and click Finish.
10. Expand lab4 in the project view and right-click in the src folder and select Import Sources….
11. Browse to select the sources\lab4 folder, click Open Folder.
12. Select lab4.c and click Finish to add the file to the project. (Ignore any errors for now).
13. Open lab4_platform > platform.spr from the Explorer.
14. Click Board Support Package under standalone.
15. Click on Documentation link corresponding to buttons peripheral under the Peripheral Drivers
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 section to open the documentation in a default browser window. As our led_ip is very similar to
GPIO, we look at the mentioned documentation.
16. Use the Helloworld.c file and follow this below code.
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* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
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* all copies or substantial portions of the Software.
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* (a) running on a Xilinx device, or
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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******************************************************************************/

/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud rate 9600.
* PS7 UART (Zynq) is not initialized by this application, since
* bootrom/bsp configures it to baud rate 115200
*
* ------------------------------------------------
* | UART TYPE BAUD RATE |
* ------------------------------------------------
* uartns550 9600
* uartlite Configurable only in HW design
* ps7_uart 115200 (configured by bootrom/bsp)
*/
#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "ledip.h"
#include "xgpio.h"
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#include "xparameters.h"

XGpio bt, sw;

XGpio_Config *gpio_config;
XGpio gpio;

void bt_init(){

gpio_config = XGpio_LookupConfig(XPAR_AXI_GPIO_0_DEVICE_ID);
int status = XGpio_CfgInitialize(&bt,gpio_config, gpio_config ->BaseAddress);
if(status == XST_SUCCESS)
xil_printf("Button INIT SUCCESSFUL\n");
else
xil_printf("Button INIT FAILED\n");
}

int main()
{
int i, bt_check;
init_platform();
bt_init ();

XGpio_SetDataDirection(&bt, 1, 0xffffffff);

while (1)
{
bt_check = XGpio_DiscreteRead(&bt, 1);
xil_printf("Push Buttons Status %x\r\n", bt_check);

// output dip switches value on LED_ip device

LEDIP_mWriteReg(XPAR_LEDIP_0_S_AXI_BASEADDR, 0, bt_check);

for (i=0; i<9999999; i++);

}
cleanup_platform();
return 0;
}
17. Save the file and build the project.

Exercise

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