International Journal of Computer Applications (0975 – 8887)

International Conference on Quality Up-gradation in Engineering Science and Technology, 2016

Design of 16-bit Vedic Multiplier for Convolutional

Encoder using VHDL
Bhagyashree V. Dagamwar R. N. Mandavgane D. M. Khatri
Student Mtech(VLSI) Associate Professor Assistant Professor
BDCE, Sevagram, INDIA BDCE, Sevagram, INDIA BDCE, Sevagram, INDIA

ABSTRACT 2. VEDIC MATHEMATICS SUTRA

In general, multiplication plays an vital role in the Vedic Mathematics deals with Sixteen Sutras. Only one Sutra
development of processors, DSP applications, image “Urdhva Tiryakbhyam” has been discussed here.
processing etc. So, designing of high speed multiplier is a
neccesary choice. In this research, design of 4, 8 and 16-bit 2.1 Urdhva Tiryakbhyam
multiplier based on vedic mathematics has been presented.
This sutra is based on “Vertically and Crosswise” technique.
These multipliers further will be used in the design of
It makes almost all the numeric computations faster and
convolutional encoder. Here, Urdhava Tiryakbhyam sutra is
easier. The advantage of multiplier based on this sutra over
used for multiplication. It eliminates unwanted multiplication
the others is that with the increase in number of bits, area and
steps and follows a fast multiplication process and achieves a
delay increases in comparison to others. Here is the example
significantly less computation complexity over its
of urdhva tiryakbhyam sutra for binary number system. In
conventional counterparts. All the modules are coded in
Fig.1, this method is illustrated with the multiplication of two
VHDL and simulation done in Xilinx ISE 14.5i.
decimal numbers 325 and 738. The numbers of steps in the
Keywords process depend upon the number of the digits being used.
Digits on the two ends of the lines are multiplied and resultant
Convolution encoder, Multiplier, Urdhava Tiryakbhyam,
is added to the carry from previous step. When the number of
Vedic mathematics
crossing lines in a single step is greater than one then they all
1. INTRODUCTION are added along with the previous carry. After this, only the
Vedic multipliers are based on Vedic Sutras. In Sanskrit word least significant digit of the resulting number is taken as
‘Veda’ stands for ‘knowledge’. Vedic mathematics is believed product digit and rest are considered as carry digits. Initial
to be reconstructed from Vedas by Sri Bharti Krishna Tirathaji carry is taken as zero.
between the years 1911 to 1918. The Vedic mathematics has
been divided into sixteen different Sutras which can be
applied to any branch of mathematics like algebra,
trigonometry, geometry etc. Its methods reduce the complex
calculations into simpler ones because they are based on
methods similar to working of human mind thereby making
them easier. An encoder is a device that converts information
from one format or code to another for the purpose of speed.
Convolutional encoding is one of the forward error correction
scheme. Error correction technique plays a very important role
in communication systems. The error correction technique
improves the capacity by adding redundant information for
the source data transmission. It provides an alternative
approach to block codes for transmission over a noisy
channel. Convolutional codes are characterized by code rate
and memory of the encoder (n,k,K). The code rate is typically
given as n/k, where n is the input data rate and k is output Fig 1: Multiplication of two decimal numbers using
symbol rate.The memory is called the “constraint length” ‘K’ Urdhva Tiryakbhyam [7]
where the output is a function of the previous K-1 inputs.
Convolutional codes were introduced in 1965 by Peter Elias. Another technique for the calculation of Urdhva Tiryakbhyam
Convolutional codes are used extensively in numerous method is shown in Figure 2. In this technique, the numbers to
application in order to achieve reliable data transfer, including be multiplied let us say 5498 and 2314 are written on the
digital video, radio, mobile communication and satellite consecutive sides of the square table. On partitioning the
communication. Convolution encoding is a process of adding square into rows and columns, each row/ column belongs to
redundancy to the information sequence which is going to be one of the digit of the two numbers to be multiplied such that
transmitted over the channel. Redundancy means introducing every digit of one number has a small square common to the
some extra symbols to the information sequence so that the digit of other number. These small squares are further divided
output bit pattern generated makes the transmitted data more into two equal parts by crosswise lines. Now the each digit of
immune to the noise in the channel. A convolution encoder one number is multiplied with every digit of second number
processes the information serially. and two digit products are placed in their corresponding
square. The digits on crosswise line are added with previous
carry. Digits on dotted significant digit of the resulting

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 International Journal of Computer Applications (0975 – 8887)
International Conference on Quality Up-gradation in Engineering Science and Technology, 2016

number are taken as product digit and rest are considered as Similar to the previous design of 4x4 multiplier, we need 4
carry digits. Initial carry is assumed to be zero here also. such 4x4 multipliers to develop 8x8 multipliers. Here we need
to first design 8bit and 12 bit adders and by proper
instantiating of the module and connections as shown in the
fig 4 we have designed a 8x8 bit multiplier

Fig 2: Alternative way to calculate the Urdhva

Tiryakbhyam [6]

3. DESIGN OF VEDIC MULTIPLIER

Fig 5: Design of 16x16 multiplier

Using 4 such 8x8 multipliers and 3 adders we can built 16x16

multiplier as shown in the fig 5.

4. EXPERIMENTAL RESULTS
4.1 RTL SCHEMATICS

Fig 3: Design of 4x4 multiplier

Using 4 such 2x2 multipliers and 3 adders we can built 4x4 bit
multipliers as shown in fig. 3

Fig 6: RTL Schematic of 4-Bit Vedic Multiplier

Fig 4: Design of 8x8 multiplier

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 International Journal of Computer Applications (0975 – 8887)
International Conference on Quality Up-gradation in Engineering Science and Technology, 2016

Fig 8: RTL Schematic of 16-Bit Vedic Multiplier

Fig 7: RTL Schematic of 8-Bit Vedic Multiplier

4.2 SIMULATION RESULT

Fig 9: Simulation Result of 4-Bit Vedic Multiplier

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 International Journal of Computer Applications (0975 – 8887)
International Conference on Quality Up-gradation in Engineering Science and Technology, 2016

Fig 10: Simulation Result of 8-Bit Vedic Multiplier

Fig 11: Simulation Result of 16-Bit Vedic Multiplier

Table 1. Synthesis Results VHDL and simulated with Xilinx 14.5i. In future work, this
multiplier will be used in convolution encoder. The
Vedic advantages of this proposed architecture is efficient in speed.
multipliers 4 Bit 8 Bit 16 Bit The multiplier can be extended upto 32-bit, 64-bit etc.

6. REFERENCES
Delay 11.393ns 19.790ns 30.534ns [1] Yogita Bansal, Charu Madhu, PardeepKaur,” High speed
vedic multiplier designs-A review”, Proceedings of 2014
RAECS UIET Panjab University Chandigarh, 06 – 08
The delay observed in the table 1 are software (simulation) March, 2011
delay i.e., as we increase the bits of operation delay also
increases. [2] Honey Durga Tiwari, Ganzorig Gankhuyag , Chan Mo
Kim, Yong Beom Cho, “Multiplier design based on
5. CONCLUSION ancient Indian Vedic Mathematics,” 978-1-4244-2599-
In this paper, we have presented the design and simulation of 0/08 2008 IEEE.
4-bit, 8-bit and 16-bit vedic multiplier.As the size of
multiplier increases delay also increases. Here, Urdhava
Tiryakbhyam sutra is used for multiplication because it [3] Ms.G.S. Suganya, Ms. G.kavya, RTL Design and VLSI
eliminates unwanted multiplication steps and follows a fast Implementation of an efficient Convolutional Encoder
multiplication process. The design has been achieved using

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 International Journal of Computer Applications (0975 – 8887)
International Conference on Quality Up-gradation in Engineering Science and Technology, 2016

and Adaptive Viterbi Decoder, 978-1-4673-4866- [6] Tiwari, H.D., Gankhuyag, G., Kim, M., and Cho, B.:
9/13/2013 IEEE. “Multiplier design based on ancient Indian Vedic
Mathematics,” IEEE Proc. International SoC Design
[4] V.Kavinilavu1, S. Salivahanan, V. S. Kanchana Conference, ISOCC, Busan, 2008, pp. II-65 - II-68.
Bhaaskaran2, Samiappa Sakthikumaran, B. Brindha and
C. Vinoth, Implementation of Convolutional Encoder and [7] Kunchigi, V., Kulkarni, L. and Kulkarni. S.: “High speed
Viterbi Decoder using Verilog HDL, 978-1-4244-8679- and area efficient Vedic multiplier,” Proc. IEEE
3/11/2011 IEEE. International Conference on Devices, Circuits and
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[5] G.Ganesh Kumar, V.Charishma, “Design of High Speed
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International Journal of Scientific and Research Mathematics or Sixteen Simple Sutras from the Vedas”,
Publications, Volume 2, Issue 3, March 2012 Motilal Banarsidas, Varanasi (India), 1986.

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