Encoding of Machine Instructions :

Instruction Format in Computer Architecture

You must be conscious that a program written in a high-level language cannot be executed directly
by the CPU. As a result, each software is first converted to binary format. The high-level program is
translated by the compiler into its corresponding low-level instruction, which contains the numbers
0 and 1. These commands are computer-organized machine orders that the processor can carry out
immediately.

The operating system loads the RAM with the machine commands. These instructions are fetched
one by one by the CPU to begin the processing. The instruction registers contain these received
instructions. The bits in machine instructions are categorized according to the format of the
command. The CPU can decode a particular piece of information from each bit. Information required
by the CPU contains the address of the data and the operation to be done.

A rectangular box that represents the instruction bits in memory words or a control register is used
to represent the instruction structure. Three sections make up the collection of bits:
  Addressing Mode: The addressing mode indicates how the data is represented.

 Opcode: The opcode part indicates the operation type on the data.

 Operand: The operand part indicates either the data or the address of the data.

 Operational codes, operands, an opcode, and an addressing method are all included in an
instruction.

 The most basic problem with the format design is the instruction length. The time required
to receive an instruction will increase with its length.

 The range of the memory is directly proportional to the number of bits. In other words, the
wider the range needed, the more number bits will be needed.

 The memory range that the instruction must target will be greater than the physical memory
if a system supports virtual memory.

 The instruction duration should be the same as the data bus length or a multiple of it.

Instruction Format
The forms for the instructions are a series of bits (0 and 1). When these pieces are combined, they
form fields. The CPU receives precise information about the operation and location of the data from
each field of the machine.

The bit configuration for an instruction is also specified by the instruction format. It may have a
variety of locations and be of varying lengths. The address elements in the instruction format change
depending on how the CPU’s registers are set up. The CPU’s supported file formats rely on the
Instructions Set Architecture the processor has put in place.
Depending on the multiple address fields, the instruction is categorized as follows:

 Zero address instruction

 One address instructions

 Two address instruction

 Three address instruction

Data that is stored in memory or processor registers is used to carry out the tasks defined by a
computer instruction. A CPU register’s operands are identified by an address. A binary integer with k
bits called the registered address designates one of the 2k registers in the CPU. Therefore, a CPU
with 16 CPUs will have a four-bit register address field and registers R0 through R15.

Example of Instruction format: The binary number 0011 will designate register R3.

Computer instructions can be any length and comprise any number of addresses. The internal layout
of a computer’s registers determines how many address spaces it has. The majority of computers fit
into one of three categories:
  Single accumulator organization.

 General register organization.

 Stack organization.

Single Accumulator Organization

An implied accumulator register is used in every action on a system. This type of computer utilizes
one address field for the instruction format.

For instance, the assembly language command ‘ADD’ defines the instruction for arithmetic addition.
The action is produced by the ADD instruction, where X is the address of the operand.

AC ← AC + M*X+.

AC is the accumulator register, and M[X] symbolizes the memory word located at address X.

General Register Organization

In their command format, general register-type computers use two or three address fields. Each
address column identifies a memory or a processor register. The procedure R1 R + M [X] is specified
by an instruction with the symbol ADD R1, X.
The memory address X and register R1 are the two address elements for this instruction.

Stack Organization

The PUSH and POP commands on a computer with a stack organization need an address field. As a
result, the word at address X is pushed to the head of the stack by the instruction PUSH X. The stack
pointer immediately updates. Since the operation is done on the top two items of the stack, stack-
organized computers don’t need an address field for the operation type instructions.

Types of Instruction Format in Computer Architecture

Below are the types of instruction format in Computer Architecture.

Zero Address Instruction

The location of the operands is tacitly represented because this instruction lacks an operand field.
These commands are supported by the stack-organized computer system. It is necessary to translate
the arithmetic expression into a reverse polish notation in order to assess it.

Example of Zero address instruction: Consider the actions below, which demonstrate how the
expression X = (A + B) (C + D) will be formatted for a stack-organized computer.

TOS: Top of the Stack

PUSH A TOS ← A

PUSH B TOS ← B

ADD TOS ← (A + B)

PUSH C TOS ← C

PUSH D TOS ← D

ADD TOS ← (C + D)

MUL TOS ← (C + D) ∗ (A + B)

POP X M *X+ ← TOS

One Address Instruction

This instruction performs data manipulation tasks using an implied accumulator. A register that the
CPU uses to carry out logical processes is called an accumulator. The accumulator is inferred in one
address instruction, so it doesn’t need an explicit reference. A second register is required for
addition and subtraction. Instead, we’ll ignore the second register in this case and presume that the
accumulator already holds the outcomes of all the operations.

Example of One address instruction: The program to evaluate X = (A + B) ∗ (C + D) is as follows:

LOAD A AC ← M *A+

ADD B AC ← A *C+ + M *B+

STORE T M *T+ ← AC

LOAD C AC ← M *C+

ADD D AC ← AC + M *D+

MUL T AC ← AC ∗ M [T]

STORE X M *X+ ← AC

All actions involve a memory operand and the accumulator (AC) register.
Any memory address is M[].
M[T] points to a temporary memory spot where the interim outcome is kept.

There is only one operand space in this instruction format. To transfer data, this address field
employs two unique instructions, namely:

 LOAD: This is used to transfer the data to the accumulator.

  STORE: This is used to move the data from the accumulator to the memory.

Two Address Instructions

The majority of commercial computers use this command. There are three operand fields in this
address command format. Registers or memory addresses can be used in the two address sections.

Example of Two address instruction: The program to evaluate X = (A + B) ∗ (C + D) is as follows:

MOV R1, A R1 ← M *A+

ADD R1, B R1 ← R1 + M *B+

MOV R2, C R2 ← M *C+

ADD R2, D R2 ← R2 + M *D+

MUL R1, R2 R1 ← R1∗R2

MOV X, R1 M *X+ ← R1

The MOV command moves the operands from the processor registers to the memory. sensors R1,
R2.

Three Address Instruction

A three-address command must have three operand elements in its format. These three fields could
either be registers or memory locations.

Example of Three address instruction: The assembly language program X = (A + B) * (C + D) Take a

look at the instructions that follow, which describe the register transfer procedure for each
instruction.

ADD R1, A, B R1 ← M *A+ + M *B+

ADD R2, C, D R2 ← M *C+ + M *D+

MUL X, R1, R2 M *X+ ← R1 ∗ R2

R1 and R2 are the two CPU registers.

The operand at the memory location represented by A is indicated by the symbol M [A]. The data or
location that the CPU will use is contained in operands 1 and 2. The address of the output is in
operand 3.
What is Instruction Pipeline in Computer Architecture?

In addition to the data stream, the command stream can also undergo pipeline processing.
In order to perform tasks like fetching, decoding, and executing instructions, the majority of digital
processors with complicated instructions need an instruction pipeline.
Each command must generally be processed by the machine in the order listed below.

 Fetch instructions from memory.

 Decode the instruction.

 Calculate the effective address.

 Fetch the operands from memory.

 Execute the instruction.

 Store the result in the proper place.

Each phase is carried out in its own segment, and occasionally various segments may require varying
amounts of time to process the incoming data. Additionally, there are instances when two or more
segments may need to access memory simultaneously, necessitating one section to wait until the
other is done. If the instruction cycle is split into equal-length parts, the structure of an instruction
pipeline will be more effective. A four-segment instruction pipeline is among the most prevalent
instances of this form of organization.
In a four-segment instruction chain, two or more distinct segments are combined to form a single
segment. For instance, the decoding of the command and determining the effective location can
both be done in one section.