H. K. E.

Society’s
Sir M. Visvesvaraya College of
Engineering
(Affiliated to VTU, Approved by AICTE, Accredited by NAAC)
Yeramarus Camp, Raichur-584135.
Department of Electronics and Communication
Question Bank
Subject Name with Code: Microcontrollers (BEC405A) Academic Year: 2024-25

Name of the Faculty: Prof. Smita C. Chetti

Module-1:
Qn. CO RBT
Question
No. Mapped Level
1 Differentiate microprocessor and microcontroller. CO-1 L1
Differentiate Harvard and Princeton Architecture/RISC and
2 CO-1 L1
CISC.
3 List the Features of 8051 microcontroller. CO-1 L1
With neat diagram explain the architecture of 8051
4 CO-1 L1
microcontroller.
Explain Internal memory organization of 8051
5 CO-1 L1
microcontroller.
6 With neat diagram explain how ROM and RAM is interfaced CO-1 L1
What is addressing mode. Explain different types of
7 CO-1 L1
addressing modes
8 Draw neat labelled pin diagram of 8051 and explain. CO-1 L1

9 Explain all the flags in PSW. CO-1 L1

Module-2:
CO RBT
Qn. No. Question
Mapped Level
1 Explain Data transfer instruction with example CO-2 L1

2 Explain Rotate instructions with examples CO-2 L1

3 Explain arithmetic instruction with example CO-2 L1

4 Explain Logical instruction with example CO-2 L1

5 Explain bit manipulation instruction with example CO-2 L1

6 With neat diagram explain the range of JUMP instructions CO-2 L1

7 Explain DAA instruction with example CO-2 L1

Define assembler directives and explain all the assembler
8 CO-2 L1
directives supported by 8051 microcontroller.
Write an ALP
9 CO-2 L2
for____________________________________________
10 Explain the following instruction------------------------ CO-2 L2
Module-3:
CO
Qn. No. Question RBT Level
Mapped
Define the following with necessary diagrams-
a. Rise time
b. Fall time
c. Edge rate
1 d. Propagation delay CO-2 L1,L2,L3
e. Contamination delay
f. Effective resistance
g. Effective capacitance
h. Diffusion capacitance
What does RC delay model represent? Also explain the L1,L2,L3
2 CO-2
Elmore delay model.
3 Explain Linear delay model with necessary equations. CO-3 L1,L2,L3

Define Logical effort. Explain the calculation with an

4 CO-2 L1,L2,L3
example circuit.
5 What is Parasitic delay? Explain with example. CO-2 L1,L2,L3
In Static CMOS explain Bubble pushing and Input ordering
6 CO-2 L1,L2,L3
delay effect.
What is Skewing? Explain the two types of Skewing with
7 CO-2 L1,L2,L3
NAND/NOR as an example.
What is Pseudo-NMOS logic/ list the various kinds of
8 CO-3 L1,L2,L3
improvisations that can be done on Pseudo-NMOS circuits.
9 Explain CVSL with generic diagram and an example. CO-3 L1,L2,L3
How are dynamic circuits different from Ratioed Logic L1,L2,L3
10 circuits? Also discuss the disadvantages of Dynamic CO-3
circuits.
Draw a circuit for Domino Logic, Dual Rail Domino logic L1,L2,L3
11 CO-3
and Multiple Output Domino logic.
L1,L2,L3
12 Explain the concept of PTL and CPTL. CO-3

Module-4:
CO
Qn. No. Question RBT Level
Mapped
Starting from basic latch to most advanced latches, explain CO-3
1 L1,L2,L3
all the conventional CMOS latches.
Explain the working of conventional CMOS flip-flops
2 along with Transmission gate, NORA and 2-Phase CO-3 L1,L2,L3
clocking.
What is the difference between Pulse-generator and Partovi CO-3 L1,L2,L3
3
Pulse-latch?
Explain the techniques of incorporating both set and reset CO-3
4 L1,L2,L3
signals.
Write a note on the following-
a. Klass Semi-dynamic Flip-Flop CO-3
5 L1,L2,L3
b. Differential Flip-Flop
c. TSPC Flip-Flop
Explain the basic principle of Pass transistor circuit as latch
for transfer of- CO-3
6 L1,L2,L3
Logic ‘0’ and logic ‘1’, Charge storage and Charge leakage
with necessary equations.
 With an example application, explain the working of
7 CO-3 L1,L2,L3
synchronous dynamic circuits.
Explain the implementation of Boolean logic in Dynamic CO-4 L1,L2,L3
8
CMOS circuits using pre-charge and Evaluate.
CO-4 L1,L2,L3
9 List the steps involved in Sub-system level design.
Differentiate between Pass Transistor Logic and CO-3 L1,L2,L3
10
Transmission gate logic.
How to restore a degraded logic level using inverter? CO-3 L1,L2,L3
11
Explain with an example.
Explain the following with an example-
a. Pseudo-NMOS logic
CO-3 L1,L2,L3
12 b. Dynamic logic
c. C2MOS logic
d. n-p CMOS logic
CO-3 L1,L2,L3
13 Briefly explain the design of Parity generator.
CO-3 L1,L2,L3
14 Design and explain with neat layout, a Data Selector.
CO-3 L1,L2,L3
15 What is PLA? Explain.

Module-5:
CO
Qn. No. Question RBT Level
Mapped
1 Give the detailed classification of semiconductor memories. CO-4 L1,L2,L3
Draw the equivalent circuit for various kinds of L1,L2,L3
2 CO-4
semiconductor memories.
3 Explain the organisation of RAM in a system. CO-4 L1,L2,L3

What are the various configurations of DRAM? Explain the

4 CO-4 L1,L2,L3
operation of each of them.
Differentiate between synchronous and asynchronous
5 CO-4 L1,L2,L3
DRAM.
What are the various configurations of SRAM? Explain the
6 operation of each of them. CO-4 L1,L2,L3

Explain SRAM read modes with timing diagram. L1,L2,L3

7 CO-4
List the various levels at which testing can be done. L1,L2,L3
8 CO-5
With neat functional diagram, explain logic verification. L1,L2,L3
9 CO-5
Also list the typical defects.

Briefly explain various Logic verification principles. CO-5 L1,L2,L3

10
Write a note on the following-

a. Fault models
b. Observability and Controllability
c. Fault coverage an delay fault testing CO-5 L1,L2,L3
11
d. ATPG
e. Ad-hoc testing
f. Scan test
g. BIST

List the different timing considerations in a system. CO-5 L1,L2,L3

12
 Compare the different memory elements with respect to L1,L2,L3
13 CO-5
their design aspects.

Explain the design and working of 1T and 3T RAM cells. CO-5 L1,L2,L3
14
What is a Pseudo-static RAM cell? Explain its working. CO-5 L1,L2,L3
15
Explain read and write operations in 4T dynamic and 6T L1,L2,L3
16 CO-5
static CMOS memory cells.

List the different levels of chip testing. CO-5 L1,L2,L3

17