Kabylake-H/LP - Intel® Management

Engine Firmware 11.7

Consumer Firmware Bring Up Guide

July 2017

Revision 1.7

Intel Confidential
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Table of Contents
1 Introduction............................................................................................... 6
1.1 Related Documentation ................................................................................. 6
1.2 Intel® ME FW Features .................................................................................. 6
1.3 Prerequisites ................................................................................................ 6
1.4 Acronyms and Definitions .............................................................................. 7
1.4.1 General ............................................................................................. 7
1.4.2 Intel® Management Engine .................................................................. 8
1.4.3 System States and Power Management ................................................. 9
1.5 Reference Documents ................................................................................... 9
1.6 Format and Notation ..................................................................................... 9
1.7 Kit Contents............................................................................................... 11
1.8 External Hardware Requirements for Bring Up ................................................ 15

2 Image Creation: Intel® Flash Image Tool ................................................ 16

2.1 Start Intel®FIT ........................................................................................... 16
2.2 Step-by-Step Guide to Build SPI Flash Image with Intel® FIT Interface .............. 16

3 Programming SPI Flash Devices and Checking Firmware Status ............ 124
3.1 Flash Burner/Programmer...........................................................................124
3.1.1 In-Circuit SPI Flash Programming for CRB ...........................................124
3.2 Flash Programming Tool (Intel® FPT) ...........................................................124
3.2.1 Intel® FPT Windows* Version ............................................................125
3.3 Checking Intel® ME Firmware Status ............................................................126
3.4 Common Bring Up Issues and Troubleshooting Table ......................................128

A Appendix — Flash Configurations ........................................................... 129

B Appendix — Intel® ICCS SKU Support Matrix.......................................... 132

B.1 Intel® ICCS SKU Matrix - KBP-LP .................................................................132
B.2 Intel® ICCS SKU Matrix - KBP-H ..................................................................133
B.3 How to configure CLKREQ# parameters ........................................................134

C Appendix — Boot Guard Configuration ................................................... 139

C.1 Boot Guard Profiles ....................................................................................139
C.2 Enforcement Policies ..................................................................................139
C.3 OEM Profile Parameters ..............................................................................140

D Appendix — Intel® Platform Trust Technology ....................................... 141

D.1 Intel® Platform Trust Technology.................................................................141

E Appendix — Settings for RVP CRBs (B)................................................... 142

F Appendix — Integrated Sensor Hub (ISH) Public Key Settings ............... 145

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Figures
Tables
1-1 Number Format Notation ............................................................................. 10
1-2 Data Format Notation.................................................................................. 10
1-3 Kit Contents............................................................................................... 11
2-1 Intel® FIT - Initial Screen Layout .................................................................. 17
2-2 Intel® FIT - Build Settings ........................................................................... 24
2-3 Intel® FIT - Flash Layout ............................................................................. 25
2-4 Intel® FIT - Flash Settings ........................................................................... 31
2-5 Intel® FIT - Intel® ME Kernel ....................................................................... 40
2-6 Intel® FIT - Intel® AMT ............................................................................... 46
2-7 Intel® FIT - Intel® Platform Protection .......................................................... 53
2-8 Intel® FIT - Integrated Clock Controller ......................................................... 58
2-9 Intel® FIT - Intel® Networking & Connectivity................................................ 78
2-10 Intel® FIT - Flex I/O ................................................................................... 83
2-11 Intel® FIT - Internal PCH Buses .................................................................... 96
2-12 Intel® FIT - GPIO ......................................................................................107
2-13 Intel® FIT - Power .....................................................................................110
2-14 Intel® FIT - Integrated Sensor Hub ..............................................................112
2-15 Intel® FIT - Debug.....................................................................................115
2-16 Intel® FIT - CPU Straps ..............................................................................119
2-17 Intel® FIT - Build Image .............................................................................123
3-1 Common Bring Up Issues and Troubleshooting Table ......................................128
B-1 Intel® ICCS SKU Matrix - KBP-LP.................................................................. 132
B-2 Intel® ICCS SKU Matrix - KBP-H.................................................................. 133
B-3 How to configure CLKREQ# parameters via FIT Tool....................................... 136
C-1 Profile Description..................................................................................... 139
C-2 Enforcement Policy Description.................................................................... 139
C-3 Profile Parameters Description..................................................................... 140
D-1 Intel® Platform Trust Technology Configuration table...................................... 141
E-1 Kabylake-LP RVP Board Settings.................................................................. 142
E-2 Kabylake-H RVP Board Settings................................................................... 143
F-1 ISH Public Key Settings.............................................................................. 145

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 Revision Description Date

1.5 Beta Release: See change bars on the left side of the page January 2017
1.6 Removed RPMC references March 2017
Removed M3 Power Rail setting.
1.7 Changed Post Manufacturing NVAR Configuration Enabled default July 2017

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Introduction

1 Introduction

This document covers the Intel® Management Engine Firmware (Intel® ME) 11.7 -
Consumer Firmware bring up procedure. Intel® ME is tied to essential platform
functionality — this dependency cannot be avoided for engineering reasons.

The bring up procedure primarily involves building a Serial Peripheral Interface (SPI)
Flash image that will contain:
• [required] Descriptor region — Contains sizing information for all other SPI Flash
image regions, SPI settings (including Vendor Specific Configuration - or VSCC -
tables, SPI device parameters), and region access permissions.
• [required] BIOS region — Contains firmware for the processor (or host) and/or
Embedded Controller (EC).
• [required] Intel® ME FW region — Contains firmware for the Intel® Management
Engine.
• [optional] GbE region — Contains firmware for Intel LAN solution.

For more details on SPI Flash layout, see the document Kabylake-H / LP SPI
Programming Guide SPI Programming Guide and Appendix A. Once the SPI Flash
image is built, it will be programmed to the target based platform and the platform will
be booted. This document also covers any tests and checks required to ensure that this
boot process is successful and that Intel® ME Consumer FW is operating as expected.

1.1 Related Documentation

VIP: Kit# 106913 - Intel® Ethernet Network Connections (20.1 OEM Gen) - LAN
Software Production Candidate 20.1

CDI # 559465 Intel® Ethernet Connection i219 [Jacksonville]

1.2 Intel® ME FW Features

This firmware release includes the following applications:
• Platform Clocks – Tune clock silicon to the parameters of a specific board, configure
clocks at run time, and power management clocks. Benefit: Allows extensive
customizability and soft control of “Third generation” clock solution and makes
clocks available before CPU powers up.
• Silicon Workaround Capability – Intel® ME FW will have limited capabilities to
perform targeted workarounds for silicon issues. Benefit: Allows Intel® ME FW to
address some issues that otherwise would require a new silicon stepping.

1.3 Prerequisites
Before this document is read and utilized, it is essential that the reader first review the
Consumer FW Release Notes (included with this Intel® ME Consumer FW kit).

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 Introduction

This document is constructed so that the reader can complete the bring up steps as
given for the Intel Customer Reference Board (CRB). However, in the case that bring up
is being performed on a different Intel® x based platform, this document will highlight
any changes that must be imposed onto the bring up steps accordingly.

This document makes only the following limited assumptions regarding hardware:
• The platform is Kabylake LP/H based
• The platform is equipped with one or more SPI Flash devices with a total capacity
sufficient for storing all relevant firmware images.

1.4 Acronyms and Definitions

1.4.1 General

Acronym or Term Definition

BIOS Basic Input Output System

DIMM Dual In-line Memory Module

DMI Direct Media Interface

EC Embedded Controller

FPF Field Programmable Fuses

FW Firmware

GbE Gigabit Ethernet

HECI Host Embedded Controller Interface (aka Intel® MEI)

Intel® ICCS Intel® Integrated Clock Controller Service

Intel® ME Intel® Management Engine (Intel®ME)

®
Intel MEI Intel® Management Engine Interface (Intel® MEI) (renamed from HECI)

Intel® PTT Intel® Platform Trusted Technology (Intel® PPT)

®
Intel MSS Intel® Management and Security Status Application

KVM Keyboard, Video, Mouse

LAN Local Area Network

MCP Multi-Chip Package (Central Processing Unit / Platform Controller Hub)

NVM Non-Volatile Memory

OOB Out-of-Band

OS Operating System

PAVP Protected Audio and Video Path

PCI Peripheral Component Interconnect

PCIe* Peripheral Component Interconnect Express

PHY Physical Layer (Networking)

RTC Real Time Clock

SBT Intel® Small Business Technology

SMBus System Management Bus

SPI Flash Serial Peripheral Interface Flash

TPM Trusted Platform Module

VSCC Vendor Specific Configuration

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Introduction

1.4.2 Intel® Management Engine

Acronym or Term Definition

3PDS 3rd Party Data Storage

Agent Software that runs on a client PC with OS running

End User The person who uses the computer (either Desktop or Mobile). In
corporate, the user usually does not have administrator privileges.

Host or Host CPU The processor that is running the operating system. This is different
than the management processor running the Intel® Management
Engine Firmware.

Host Service/Application An application that is running on the host CPU

INF An information file (.inf) used by Microsoft* operating systems that

supports the Plug & Play feature. When installing a driver, this file
provides the OS the necessary information about driver filenames,
driver components, and supported hardware.

Intel® Management Engine Interface between the Management Engine and the Host system
Interface (Intel® MEI)

Intel® MEI driver Intel® ME host driver that runs on the host and interfaces between ISV
Agents and the Intel® ME HW.

IT User Information Technology User. Typically very technical and uses a

management console to ensure functionality of multiple PCs on a
network.

LMS Local Management Service: A SW application which runs on the host

machine and provide a secured communication between the ISV agent
and the Intel® Management Engine Firmware.

Intel® ME Intel® Management Engine: The embedded processor residing in the

chipset MCP

MECI ME-VE Communication Interface

NVM Non-Volatile Memory: A type of memory that will retain its contents
even if power is removed. In the Intel® AMT current implementation,
this is achieved using a FLASH memory device.

OOB Interface Out Of Band interface: This is WSMAN interface over secure or non-
secure TCP protocol.

OS not Functional The Host OS is considered non-functional in Sx power state and any one
of the following cases when system is in S0 power state:
• OS is hung
• After PCI reset
• OS watch dog expires
• OS is not present

System States Operating System power states such as S0. See detailed definitions in
System States and Power Management section.

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 Introduction

1.4.3 System States and Power Management

Acronym or Term Definition

G3 A system state of Mechanical Off where all power is disconnected from

the system. G3 power state does not necessarily indicate that RTC
power is removed.

CM0 Intel® Management Engine firmware power state where all hardware
power planes are activated. The host power state is S0.

CM3 Intel® Management Engine power state where the host is in Sx. The
processor DRAM Controller is turned off and DRAM power stays in off/
self refresh mode. There is no UMA usage in CM3 state. Less than 1MB
of SRAM used for code and data. Code is executed off of flash takes
~1mS.

CM0-PG Core Well Powered; Intel® ME Well Powered; (Intel® ME core not
consuming power) DRAM available.

CM3-PG An Intel® ME Firmware power state where no power is applied to the

Management Engine subsystem. (Intel® ME firmware is shut down).

OS Hibernate System state where the OS state is saved on the hard drive.

S0 A system state where power is applied to all HW devices and the system
is running normally.

S1, S2, S3 A system state where the host CPU is halted but power remains
available to the memory system (memory is in self-refresh mode).

S4 A system state where the host CPU and memory are not active.

S5 A system state where all power to the host system is off, however the
power cord (and/or battery in mobile designs) is still connected.

Shut Down Equivalent to the S5 state.

Snooze Mode Intel® Management Engine activities are mostly suspended to save
power. The Intel® Management Engine monitors HW activities and can
restore its activities depending on the HW event.

Standby System state where the OS state is saved in memory and resumed from
the memory when mouse/keyboard is clicked.

Sx All S states which are different than S0.

1.5 Reference Documents

Doc Number/
Document
Location*

Kabylake Intel® Management Engine (Intel® ME) and Embedded Controller Interaction 549024 / CDI
Product Specification Revision 0.5

Intel® Management Engine BIOS Writers Guide TBD / *

®
Intel Management Engine (Intel® ME) 11 SKU Firmware Consumer Compliance Guide for 547408/ CDI
Kabylake PCH-H/LP Chipset Family - Kabylake Platform Compliancy and Testing Guide -
Revision 1.1

Note: * Unless specified otherwise, a document can be ordered by providing its reference number to your
Intel Field Applications Engineer.

1.6 Format and Notation

The formats and notations used within this document model are those typically used by
BIOS vendors. This section describes the formatting and the notations that will be
followed in this document.

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Introduction

Table 1-1. Number Format Notation

Number Format Notation Example

Decimal (default) d 14d. Note that any number without an explicit suffix can be
assumed to be decimal.

Binary b 1110b

Hex h 0Eh

Hex 0x 0x0E

Table 1-2. Data Format Notation

Data Type Notation Size

Bit b Smallest unit, 0 or 1

Byte B 8 bits

Word W 16 bits or 2 bytes

Double-word DW 32 bits or 4 bytes

Quad-word QW 8 bytes or 4 words

Kilobyte KB 1024 bytes

Megabit Mb 1,048,576 bits or 128 KB

Megabyte MB 1,048,576 bytes or 1024 KB

Gigabit Gb 1,073,741,824 bits

Gigabyte GB 1024 MB

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 Introduction

1.7 Kit Contents

The Intel® ME Consumer FW kit can be downloaded from VIP
(https://platformsw.intel.com/). The contents of this kit are detailed below (Note that
only key files are listed).

Table 1-3. Kit Contents (Sheet 1 of 4)

File or [Directory] Content Description

[root] Root directory

Consumer FW Bring Up Guide.pdf This document

Kabylake-H Client SPI Programming Guide.pdf How to program SPI device parameters and
descriptor region details. Also contains a
complete SPI Flash softstrap reference.

Kabylake-LP Client SPI Programming Guide.pdf How to program SPI device parameters and
descriptor region details. Also contains a
complete SPI Flash softstrap reference.

[Image Components]

[BIOS]

PreProduction_KBLX085_0184_02_RomImages_Release BIOS image only for Intel CRB.

Build.rom

Production_KBLX085_0184_02_RomImages_ReleaseBui BIOS image only for Intel CRB.

ld.rom

[Certificates]

[HDCP]

HDCP Wireless Receiver Device Key

Provisioning.pdf

IntelProvisioning_Root_PublicKey.cer

SklDeviceProvCertProd.cer

HDCP Wireless Receiver Device Key Provisioning.pdf

IntelProvisioning_Root_PublicKey.cer

SklDeviceProvCertPreprod.cer

SklDeviceProvCertProd.cer

[GbE]

n7_spt_h_lm_non_lan_sw_0.8.bin Intel® LAN PHY LPT-H firmware image.

n7_spt_lp_lm_non_lan_sw_1.3.bin Intel® LAN PHY LPT-LP firmware image.

[ME]

ME_11.7_Consumer_C0_H.bin Intel® ME firmware image (Non Production

FW) - supports unfused Kabylake PCH-LP
Platform I/O MCP steppings:
• Unfused (Super SKU)

Note: For PAVP Testing, you must match

Production FW with Production Part and Non
Production FW with Non Production Parts.

ME_11.7_Consumer_D0_H_Production.bin

[Installers]

Intel®_ME SW Installation Guide.pdf Intel® ME Software installation Guide.

[ME_SW_MSI]

IntelMEFWVer.dll

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Introduction

Table 1-3. Kit Contents (Sheet 2 of 4)

File or [Directory] Content Description

MUP XML file

SetupME

WixLicenseNote.txt

[MEI-Only Installer MSI]

IntelMEFWVer.dll

MEISetup

MUP XML file

[Tools]

[ICC_Tools]

Intel® ME Firmware Integrated Clock Control (ICC) Tools ICC Tools User Guide
User Guide.pdf

[CCT]

cct Exe file

cct Ini file

cctDll.dll

cctWin Exe file

[EFI]

cct.efi CCT for EFI

[System Tools]

Open Watcom Public License.pdf Sybase Open Watcom Public License version 1.0
document.

System Tools User Guide.pdf System Tools User Guide

[Flash Image Tool]

fit.exe Intel® Flash Image Tool (Intel® FIT)

newfiletmpl.xml FITC Configuration XML file

vsccommn.bin Binary containing the supported SPI parts

VSCCommn_bin Content.pdf Documentation listing the SPI parts supported

by vscccommn.bin

[Flash Programming Tool]

[DOS]

fparts.txt List of supported SPI Flash devices with specific

Flash parameters

fpt.exe Intel® FPT for DOS

[EFI64]

fparts.txt List of supported SPI Flash devices with specific

Flash
parameters

fpt.efi Intel® FPT for EFI

[Windows]

fparts.txt List of supported SPI Flash devices with specific

Flash parameters

fptw.exe Intel® FPT for Windows*

Idrvdll.dll

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 Introduction

Table 1-3. Kit Contents (Sheet 3 of 4)

File or [Directory] Content Description

Pmxdll.dll

[Windows64]

fparts.txt List of supported SPI Flash devices with specific

Flash parameters

fptw64.exe Intel® FPT for Windows* (64-bit) OS

Idrvdll32e.dll

Pmxdll32e.dll

[FWUpdate]

[EFI64]

FWUpdLcl.efi FW Update Tool (EFI version)

[DOS]

FWUpdLcl.exe FW Update Tool (DOS version)

[Win]

FWUpdLcl.exe FW Update Tool (Windows* version 32bit)

[Win64]

FWUpdLcl64.exe FW Update Tool (Windows* version 64bit)

[Manifest Extension Utility]

[Win]

meu.exe Intel®Manifest Extension Utility (MEU)

executable file that allows input of FW binary
and outputs and independent updatable
partition that is compressed and signed.

[MEInfo]

[DOS]

MEInfo.exe Intel®ME Information Tool (DOS version)

[EFI64]

MEInfo.efi Intel®ME Information Tool (EFI version)

[Windows]

MEInfoWin.exe Intel®ME Information Tool (Windows* version

32bit)

Idrvdll.dll

Pmxdll.dll

ISHLib.dll

[Windows64]

MEInfoWin64.exe Intel®ME Information Tool (Windows* version

64bit)

Idrvdll32e.dll

ISHLib.dll

Pmxdll32e.dll

[MEManuf]

[DOS]

MEManuf.exe Intel®ME Manufacturing Tool (DOS version)

vsccommn.bin Binary containing the supported SPI parts

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Introduction

Table 1-3. Kit Contents (Sheet 4 of 4)

File or [Directory] Content Description

VSCCommn_bin Content.pdf Documentation listing the SPI parts supported

by vscccommn.bin

[EFI64]

VSCCommn_bin Content.pdf Documentation listing the SPI parts supported

by vscccommn.bin

MEManuf.efi Intel®ME Manufacturing Tool (EFI version)

vsccommn.bin Binary containing the supported SPI parts

[Windows]

Idrvdll.dll

MEManufWin.exe Intel®ME Manufacturing Tool (Windows*

version 32bit)

Pmxdll.dll

ISHLib.dll

vsccommn.bin Binary containing the supported SPI parts

VSCCommn_bin Content.pdf Documentation listing the SPI parts supported

by vscccommn.bin

[Windows64]

Idrvdll32e.dll

ISHLib.dll

MEManufWin64.exe Intel®ME Manufacturing Tool (Windows*

version 64bit)

Pmxdll32e.dll

vsccommn.bin Binary containing the supported SPI parts

VSCCommn_bin Content.pdf Documentation listing the SPI parts supported

by vscccommn.bin

(empty)

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 Introduction

1.8 External Hardware Requirements for Bring Up

Acquire the following hardware tools before moving on to the next step.

Windows* OS System Flash Burner DOS Bootable USB Key

Equipment: Equipment: Equipment:

• Laptop or desktop that • (Optional) For platforms that • A DOS Bootable USB Key
supports win32 applications don’t boot, a Flash Chip (Size > 512 MB)
Programmer will be required
Purpose: • For platforms that can boot to Purpose:
• Will run firmware image DOS or Windows*, a Intel® • Acting as a bootable device
assembly and build process FPT is provided in this kit and will be used to run Intel®
software. FPT (fpt.exe) directly on the
Purpose: system that is undergoing
• Will burn firmware images Bring Up process.
onto the target system Flash • Or will be used to transfer a
device(s). firmware image onto a Flash
burner.

§§

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Image Creation: Intel® Flash Image Tool

2 Image Creation: Intel® Flash

Image Tool

Intel® Flash Image Tool (Intel® FIT) can be used to generate either a full SPI Flash
binary image with Descriptor, GbE, BIOS, and Intel® ME Regions. Additionally, it can be
used to create a simple image containing only the Intel® ME Region only for use with
custom SPI Flash binary image assembly solutions. Use the steps shown in following
sections.

After this image has been created, it will need to be burned onto the target platform’s
SPI Flash device(s). Section 3, “Programming SPI Flash Devices and Checking
Firmware Status” later in this document provides steps to do this.

Note: The Flash Image Tool may be updated throughout the release cycles. As a general rule,
please ensure you use the tools, images and other content from the same kit and
refrain from using different version tools.

2.1 Start Intel®FIT

1. Invoke Intel® Flash Image Tool. Using Explorer*, navigate to
[root]\Tools\System Tools\Flash Image Tool. Verify that the directory
contents are correct (see Section 1.7). Double-click FIT.exe.
2. NOTE: In the tables below, where default settings are listed for KBL LP/H, if the
value is the same one value will be listed. If there is a different default value when
the program loads with either platform, both values will be listed to show the
difference.

2.2 Step-by-Step Guide to Build SPI Flash Image with

Intel® FIT Interface

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 Image Creation: Intel® Flash Image Tool

Table 2-1. Intel® FIT - Initial Screen Layout (Sheet 1 of 7)

# Label Contents

This button labeled ‘New’ on rollover allows opening of a new session with default
1 New
values

2 Open This button labeled ‘Open’ on rollover allows opening of an xml or bin file

3 Save This button labeled ‘Save’ on rollover allows saving of xml file

4 Clear Console This button labeled ‘Clear Console’ clears the console area (see page 23)

This button labeled ‘Build Settings’ brings up the build settings popup Window see
5 Build Settings
(Table 2-2)

6 Build Image This button labeled ‘Build Image’ on rollover allows build of the image

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Image Creation: Intel® Flash Image Tool

Table 2-1. Intel® FIT - Initial Screen Layout (Sheet 2 of 7)

# Label Contents

7 Drop Down Selector This drop down allows selection of platform

8 Drop Down Selector This drop down allows selection of SKU within platform selected

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 Image Creation: Intel® Flash Image Tool

Table 2-1. Intel® FIT - Initial Screen Layout (Sheet 3 of 7)

# Label Contents

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Image Creation: Intel® Flash Image Tool

Table 2-1. Intel® FIT - Initial Screen Layout (Sheet 4 of 7)

# Label Contents
Flash Layout which contains (see Table 2-3):
• Regions
9 Descriptor Region
GBE Region
Flash Layout Tab Intel® ME Region
PDR Region
EC Region
BIOS Region
Flash Settings which contains (see Table 2-4):
• Flash Components
10 • Host CPU/ BIOS Master Access
• Intel® ME Master Access
Flash Settings Tab • GBE Master Access
• EC Master Access
• Flash Configuration
• VSCC Table - VSCC Entry
• BIOS Configuration
Intel® ME Kernel which contains (see Table 2-5):
• Processor
11 • Intel® ME Firmware Update
• Intel® Services Configuration
Intel® ME Kernel Tab
• Image Identification
• MCTP Configuration
• Firmware Diagnostics
• Post Manufacturing Lock
• Reserved

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 Image Creation: Intel® Flash Image Tool

Table 2-1. Intel® FIT - Initial Screen Layout (Sheet 5 of 7)

# Label Contents

Intel® AMT which contains (see Table 2-6):

• Intel® AMT Configuration
12 • KVM Configuration
• Provisioning Configuration
Intel® AMT Tab
• OEM Customizable Certificates (1, 2, 3)
• OEM Default Certificates (1, 2, 3, 4, 5)
• Redirection Configuration
• TLS Configuration
Platform Protection which contains (see Table 2-7):
• Content Protection
13 • Graphics uController
Platform Protection Tab • Hash Key Configuration for Bootguard / ISH
• Boot Guard Configuration
• Intel® PTT Configuration
• TPM Over SPI Bus Configuration
Integrated Clock Controller which contains (see Table 2-8):

Integrated Clock • Integrated Clock Controller Policies

14 Controller Tab • Profiles

Networking & Connectivity which contains (see Table 2-9):

Networking & • Wired LAN Configuration

15 Connectivity Tab • Wireless LAN Configuration
• Intel® NFC Configuration

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Image Creation: Intel® Flash Image Tool

Table 2-1. Intel® FIT - Initial Screen Layout (Sheet 6 of 7)

# Label Contents

Flex I/O which contains (see Table 2-10):

• Intel® RST for PCIe Configuration
16 • PCIe Lane Reversal Configuration
• PCIe Port Configuration
Flex I/O Tab
• SATA / PCIe Combo Port Configuration
• SATA / PCIe Combo Port Select Polarity
• USB3 Port Configuration
• XHCI Port Configuration
Internal PCH Buses which contains (see Table 2-11):
• OPI Configuration
17 Internal PCH Buses Tab
• DMI Configuration
• eSPI Configuration
• PCH Timer Configuration
• SMBus / SMLink Configuration
GPIO which contains (see Table 2-12):
• LAN / GPIO Select
18 GPIO Tab • WLAN / GPIO Select
• Platform Power / GPIO
• ME Feature Pins
Power which contains (see Table 2-13):
• Platform Power
19 Power Tab
• Intel® ME Power Configuration
• Deep Sx

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 Image Creation: Intel® Flash Image Tool

Table 2-1. Intel® FIT - Initial Screen Layout (Sheet 7 of 7)

# Label Contents

Integrated Sensor Hub which contains (see Table 2-14):

Integrated Sensor Hub • Integrated Sensor Hub

20 Tab • ISH Image
• ISH Data
Debug which contains (see Table 2-15):
• Intel® ME Firmware Debugging Overrides
21 Debug Tab
• Direct Connection Interface Configuration
• Intel® Trace Hub Technology
CPU Straps which contain a detailed list of parameters (see Table 2-16)

CPU Straps Tab

22
Displays opening messages, log file entries, and build activity messages

Console Window Area

23

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Image Creation: Intel® Flash Image Tool

Table 2-2. Intel® FIT - Build Settings (Sheet 1 of 2)

Click on Build Button in the top menu bar> Build Settings window pop up is displayed:

# Parameter CRB Values

Output Path Double click to the right of outimage.bin and click to get browse button to
specify path and name of file to create for the build - default is

1 outimage.bin in the same folder as Intel® FIT tool

Generate Intermediate Yes Yes/No - Yes is default

Files
2
Enable Boot Guard Yes Yes/No - Yes is default
warning message at
3 build time

Enable Intel(R) Yes Yes/No - Yes is default

Platform Trust
4 Technology warning
message at build time

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 Image Creation: Intel® Flash Image Tool

Table 2-2. Intel® FIT - Build Settings (Sheet 2 of 2)

Click on Build Button in the top menu bar> Build Settings window pop up is displayed:
# Parameter CRB Values
Region Order

5
$WorkingDir and $DestDir can be left at the default ‘.’
Click on $SourceDir Value field and type in path where the Image
6 Components are located for the Manageability Engine kit

Table 2-3. Intel® FIT - Flash Layout (Sheet 1 of 6)

Click on Flash Layout in the left tabs menu> Descriptor Region is expanded by default:

# Parameter Platform Settings

Descriptor Region - Length KBL-Y 0
KBL-U 0
1 Values: Leave this at zero. Allows Intel® FIT to auto-size the descriptor region
length.
KBL-H
KBL-S
0
0
HEDT 0
OEM Section Binary
This loads the OEM Section binary that will be merged into the output image
generated by the Intel® FIT tool.
Click on Flash Layout in the left tabs menu> Gbe Region is expanded by default:

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Image Creation: Intel® Flash Image Tool

Table 2-3. Intel® FIT - Flash Layout (Sheet 2 of 6)

# Parameter Platform Settings
GbE Region - Length KBL-Y
0
Note: This value will be automatically populated by Intel® FIT during image build. KBL-U 0
KBL-H 0
2 KBL-S 0
0
HEDT
GbE Binary File KBL-Y gbeimage.bin
Navigate to your Source Directory (as specified in Table 2-2) and switch to the KBL-U gbeimage.bin
GbE subdirectory. Choose the appropriate Intel GbE LAN Firmware binary image. If KBL-H gbeimage.bin
not using Intel LAN then load the GbE image before disabling the region
KBL-S gbeimage.bin
along with changing additional settings below. This loads the Intel®
integrated LAN binary that will be merged into the output image generated by the HEDT gbeimage.bin
Intel® FIT tool.
Note: If loading gbeimage.bin file, check that the GbE region is enabled in tool
before building image.
GbE Region Enable KBL-Y Enabled
Values: Enabled/Disabled - This option allows the user to enable or disable the KBL-U Enabled
Gigabit Ethernet Region. KBL-H Enabled
NOTE: If choosing a configuration that does not include the GbE LAN the KBL-S Enabled
following settings need to be adjusted:
HEDT Enabled

These additional settings are under the Networking & Connectivity tab > Wired LAN Configuration. In the GPIO > LAN /
GPIO Select ensure the value is set correctly for board type.
Image Id - This displays Image ID of the currently loaded Intel® Integrated LAN
binary.
Major Version - This displays Major revision number of the currently loaded
Intel® Integrated LAN binary.
Minor Version - This displays Minor revision number of the currently loaded
Intel® Integrated LAN binary.

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 Image Creation: Intel® Flash Image Tool

Table 2-3. Intel® FIT - Flash Layout (Sheet 3 of 6)

Click on Flash Layout in the left tabs menu> Intel® ME Region is expanded by default:

# Parameter Platform Settings

Intel® ME Region - Length KBL-Y 0
KBL-U 0
3 KBL-H 0
KBL-S 0
HEDT
Intel® ME Binary File KBL-Y meimage.bin
Navigate to your Source Directory (as specified in Table 2-2) and switch to the ME KBL-U meimage.bin
subdirectory. Choose the appropriate Intel ME Firmware binary image. This loads KBL-H meimage.bin
the Intel® ME binary that will be merged into the into the output image generated
KBL-S meimage.bin
by the Intel® FIT tool.
HEDT meimage.bin
Note: You may choose to build the Intel® ME Region only. To do so, the Number
of Flash Components in Flash Settings> Flash Components must be set to 0.
Note: If loading meimage.bin file, check that the ME region is enabled in tool
before building image.
Major Version - This displays Major revision number of the currently loaded
Intel® ME binary.
Minor Version - This displays Minor revision number of the currently loaded
Intel® ME binary.
Hotfix Version - This displays Hot-Fix revision number of the currently loaded
Intel® ME binary.
Build Version - This displays Build version number of the currently loaded Intel®
ME binary.
Chipset Initialization Binary - This loads the Chipset Initialization binary that will
be merged into the output image generated by the Intel® FIT. If specified, this will
override the version contained in the Intel® ME binary.
Chipset Initialization Version - This displays the current Chipset Initialization
version contained in the currently loaded Intel® ME binary.
ChipsetInit Override Version - This displays the version of the Chipset
Initialization Binary override if specified.
Intel® Trace Hub Binary - This loads the Intel® Trace Hub binary that will be
merged into the output image generated by the Intel® FIT tool.

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Image Creation: Intel® Flash Image Tool

Table 2-3. Intel® FIT - Flash Layout (Sheet 4 of 6)

Click on Flash Layout in the left tabs menu> PDR Region is expanded by default:

# Parameter Platform Settings

PDR Region - Length KBL-Y 0
Region is disabled by default. Displays Region size information when Binary input KBL-U 0
4 file is specified. KBL-H 0
KBL-S 0
HEDT 0
PDR Binary File KBL-Y -
Navigate to path to load pdrimage.bin file if required and available. This loads the KBL-U -
Platform Data region binary that will be merged into the output image generated by KBL-H -
the Intel® FIT tool.
KBL-S -
HEDT -
PDR Region Enable KBL-Y Disabled
Values: Enabled/Disabled - This option allows the user to enable or disable the KBL-U Disabled
Platform Data Region. KBL-H Disabled
Note: If loading PDR.bin file, check that the PDR region is enabled in tool before KBL-S Disabled
building image.
HEDT Disabled
Click on Flash Layout in the left tabs menu> Ec Region is expanded by default:

# Parameter Platform Settings

EC Region - Length KBL-Y 0
KBL-U 0
5 KBL-H 0
KBL-S 0
HEDT 0
EC Binary File KBL-Y -
Navigate to path to load EC bin file. This loads the Embedded Controller binary used KBL-U -
for eSPI that will be merged into the output image generated by the Intel® FIT KBL-H -
tool.
KBL-S -
HEDT -

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 Image Creation: Intel® Flash Image Tool

Table 2-3. Intel® FIT - Flash Layout (Sheet 5 of 6)

EC Region Enable KBL-Y Disabled
Values: Enabled/Disabled KBL-U Disabled
This option allows the user to enable or disable the Embedded Controller data KBL-H Disabled
region. KBL-S Disabled
HEDT Disabled
EC Region Pointer File KBL-Y -
This loads a binary file containing the 16 byte Embedded Controller pointer value at KBL-U -
the start of the flash descriptor KBL-H -
KBL-S -
HEDT -

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Image Creation: Intel® Flash Image Tool

Table 2-3. Intel® FIT - Flash Layout (Sheet 6 of 6)

Click on Flash Layout in the left tabs menu> BIOS Region is expanded by default:

# Parameter Platform Settings

BIOS Region - Length KBL-Y 0
KBL-U 0
6 KBL-H
KBL-S
0
0
HEDT 0
BIOS Binary File KBL-Y biosimage.bin
Navigate to path to load bios.rom file. This loads the BIOS binary that will be KBL-U biosimage.bin
merged into the output image generated by the Intel® FIT tool. KBL-H biosimage.bin
KBL-S biosimage.bin
HEDT biosimage.bin
BIOS Region Enable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This option allows the user to enable or disable the BIOS region. KBL-H Enabled
Note: After loading bios.rom file, check that the BIOS region is enabled in tool KBL-S Enabled
before building image. HEDT Enabled

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 Image Creation: Intel® Flash Image Tool

Table 2-4. Intel® FIT - Flash Settings (Sheet 1 of 9)

Click on Flash Settings in the left tabs menu> Flash Components is expanded by default:

# Parameter Platform Settings

Flash Components

1
Number of Components KBL-Y 1
Values: 0, 1, 2 - This setting configures the total number of flash components for KBL-U 1
the platform. Note: Choosing a selection of '0' part will cause the Intel® FIT tool to KBL-H 1
build an output image containing only the Intel® ME region.
KBL-S 1
HEDT 1
Flash component 1 Size KBL-Y 8MB
Values: 512KB, 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB - This setting KBL-U 16MB
determines the size of Flash component 1 for the platform image. KBL-H 16MB
KBL-S 16MB
HEDT 16MB
Flash component 2 Size KBL-Y 8MB
Values: 512KB, 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB - This setting KBL-U 8MB
determines the size of Flash component 2 for the platform image. Note: This setting KBL-H 8MB
is only applicable when the Number of Flash Components option is set to '2'.
KBL-S 8MB
HEDT 8MB
SPI Voltage Select KBL-Y 3.3 Volts
Values: 1.8 Volts, 3.3 Volts - This strap sets the internal control signal on the pad KBL-U 3.3 Volts
for either 1.8 or 3.3 volts. See Kabylake H / LP SPI Programming Guide for further KBL-H 3.3 Volts
details.
KBL-S 3.3 Volts
HEDT 3.3 Volts
Click on Flash Settings in the left tabs menu> Host CPU/BIOS Master Access is expanded by default:

# Parameter Platform Settings

Host CPU / BIOS Master Access

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Image Creation: Intel® Flash Image Tool

Table 2-4. Intel® FIT - Flash Settings (Sheet 2 of 9)

# Parameter Platform Settings
Host CPU / BIOS Write Access KBL-Y 0xFFF
Values: 0xFFF, 0x00A, 0x01A, 0x10A, 0x11A - This setting determines write KBL-U 0xFFF
access control for the BIOS region. KBL-H 0xFFF
0xFFF = Debug/Manufacturing KBL-S 0xFFF
0x00A = Production HEDT 0xFFF
0x01A = Production with access to PDR (should ONLY be used if PDR region is
implemented).
0x10A = Production with access to EC
0x11A = Production with access to EC and PDR
For further details on Region Access Control see Kabylake H / LP SPI Programming
guide further details.
Host CPU / BIOS Read Access KBL-Y 0xFFF
Values: 0xFFF, 0x00F, 0x01F, 0x10F, 0x11F - This setting determines read KBL-U 0xFFF
access control for the BIOS region. KBL-H 0xFFF
0xFFF = Debug/Manufacturing KBL-S 0xFFF
0x00F = Production HEDT 0XFFF
0x01F = Production with access to PDR (should ONLY be used if PDR region is
implemented).
0x10F = Production with access to EC
0x11F = Production with access to EC and PDR
For further details on Region Access Control see Kabylake H / LP SPI Programming
guide.
Click on Flash Settings in the left tabs menu> Intel® ME Master Access is expanded by default:

# Parameter Platform Settings

Intel® ME Master Access

3
Intel® ME Write Access KBL-Y 0xFFF
Values: 0xFFF, 0x004 - This setting determines write access control for the ME KBL-U 0xFFF
region. KBL-H 0xFFF
0xFFF = Debug/Manufacturing KBL-S 0xFFF
0x004 = Production HEDT 0XFFF
For further details on Region Access Control see Kabylake H / LP SPI Programming
guide further details.
Intel® ME Read Access KBL-Y 0xFFF
Values: 0xFFF, 0x00D - This setting determines read access control for the ME KBL-U 0xFFF
region. KBL-H 0xFFF
0xFFF = Debug/Manufacturing KBL-S 0xFFF
0x00D = Production HEDT 0XFFF
For further details on Region Access Control see Kabylake H / LP SPI Programming
guide further details.
Click on Flash Settings in the left tabs menu> GbE Master Access is expanded by default:

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 Image Creation: Intel® Flash Image Tool

Table 2-4. Intel® FIT - Flash Settings (Sheet 3 of 9)

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Image Creation: Intel® Flash Image Tool

Table 2-4. Intel® FIT - Flash Settings (Sheet 4 of 9)

# Parameter Platform Settings
GbE Master Access

4
GbE Write Access KBL-Y 0xFFF
Values: 0xFFF, 0x008 - This setting determines write access control for the Gigabit KBL-U 0xFFF
Ethernet Region. KBL-H 0xFFF
0xFFF = Debug/Manufacturing KBL-S 0xFFF
0x008 = Production HEDT 0XFFF
For further details on Region Access Control see Kabylake H / LP SPI Programming
guide further details.
GbE Read Access KBL-Y 0xFFF
Values: 0xFFF, 0x009 - This setting determines read access control for the Gigabit KBL-U 0xFFF
Ethernet Region. KBL-H 0xFFF
0xFFF = Debug/Manufacturing KBL-S 0xFFF
0x009 = Production HEDT 0XFFF
For further details on Region Access Control see Kabylake H / LP SPI Programming
guide further details.
Click on Flash Settings in the left tabs menu> EC Master Access is expanded by default:

# Parameter Platform Settings

EC Master Access

5
# Parameter Platform Settings
EC Write Access KBL-Y 0xFFF
Values: 0xFFF, 0x100 - This setting determines write access control for the KBL-U 0xFFF
Embedded Controller Region. KBL-H 0xFFF
0xFFF = Debug/Manufacturing KBL-S 0xFFF
0x100 = Production HEDT 0XFFF
For further details on Region Access Control see Kabylake H / LP SPI Programming
guide further details.
EC Read Access KBL-Y 0xFFF
Values: 0xFFF, 0x101, 0x103 - This setting determines read access control for the KBL-U 0xFFF
Embedded Controller Region. KBL-H 0xFFF
0xFFF = Debug/Manufacturing KBL-S 0xFFF
0x101 = Production HEDT 0XFFF
0x103 = Production with EC BIOS Read Access
For further details on Region Access Control see Kabylake H / LP SPI Programming
guide further details.

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 Image Creation: Intel® Flash Image Tool

Table 2-4. Intel® FIT - Flash Settings (Sheet 5 of 9)

Click on Flash Settings in the left tabs menu> Flash Configuration is expanded by default:

# Parameter Platform Settings

Flash Configuration

6
Dual I/O Read Enabled KBL-Y No
Values: Yes/No - This setting allows the customer to enable support for Dual I/O KBL-U No
Read capabilities for flash components. See Kabylake H / LP SPI Programming guide KBL-H No
for further details.
KBL-S No
HEDT No
Dual Output Read Enabled KBL-Y Yes
Values: Yes/No - This setting allows the customer to enable support for Dual KBL-U Yes
Output Read capabilities for flash components. See Kabylake H / LP SPI KBL-H Yes
Programming guide for further details.
KBL-S Yes
HEDT Yes

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Image Creation: Intel® Flash Image Tool

Table 2-4. Intel® FIT - Flash Settings (Sheet 6 of 9)

# Parameter Platform Settings
Fast Read Clock Frequency KBL-Y 48MHz
Values: 17MHz, 30MHz, 48MHz - This setting allows the customer to configure the KBL-U 48MHz
flash component clock frequency setting for Fast Read. See Kabylake H / LP SPI KBL-H 48MHz
Programming guide for further details.
KBL-S 48MHz
HEDT 48MHz
Fast Read Supported KBL-Y Yes
Values: Yes/No - This setting allows the customer to enable support for Fast Read KBL-U Yes
capabilities for flash components. See Kabylake H / LP SPI Programming guide for KBL-H Yes
further details.
KBL-S Yes
Note: If fast read supported is set to “No” any changes made to Dual I/O, Quad I/
HEDT Yes
O, Dual Output, or Quad Output will not be affected if set to yes. Fast read supported
should also be set to enable frequencies greater than 20MHz.
Invalid Instruction 0 - This setting allows the customer to configure invalid KBL-Y 0x00000021
instruction to protect against Chip Erase. See Kabylake H / LP SPI Programming KBL-U 0x00000021
guide for further details. Note: This setting should be set to '0' if there are not
KBL-H 0x00000021
Invalid instructions.
KBL-S 0x00000021
HEDT 0x00000021
Invalid Instruction 1 - This setting allows the customer to configure invalid KBL-Y 0x00000042
instruction to protect against Chip Erase. See Kabylake H / LP SPI Programming KBL-U 0x00000042
guide for further details. Note: This setting should be set to '0' if there are not
KBL-H 0x00000042
Invalid instructions.
KBL-S 0x00000042
HEDT 0x00000042
Invalid Instruction 2 - This setting allows the customer to configure invalid KBL-Y 0x00000060
instruction to protect against Chip Erase. See Kabylake H / LP SPI Programming KBL-U 0x00000060
guide for further details. Note: This setting should be set to '0' if there are not
KBL-H 0x00000060
Invalid instructions.
KBL-S 0x00000060
HEDT 0x00000060
Invalid Instruction 3 - This setting allows the customer to configure invalid KBL-Y 0x000000AD
instruction to protect against Chip Erase. See Kabylake H / LP SPI Programming KBL-U 0x000000AD
guide for further details. Note: This setting should be set to '0' if there are not
KBL-H 0x000000AD
Invalid instructions.
KBL-S 0x000000AD
HEDT 0x000000AD
Invalid Instruction 4 - This setting allows the customer to configure invalid KBL-Y 0x000000B7
instruction to protect against Chip Erase. See Kabylake H / LP SPI Programming KBL-U 0x000000B7
guide for further details. Note: This setting should be set to '0' if there are not
KBL-H 0x000000B7
Invalid instructions.
KBL-S 0x000000B7
HEDT 0x000000B7
Invalid Instruction 5 - This setting allows the customer to configure invalid KBL-Y 0x000000B9
instruction to protect against Chip Erase. See Kabylake H / LP SPI Programming KBL-U 0x000000B9
guide for further details. Note: This setting should be set to '0' if there are not
KBL-H 0x000000B9
Invalid instructions.
KBL-S 0x000000B9
HEDT 0x000000B9
Invalid Instruction 6 - This setting allows the customer to configure invalid KBL-Y 0x000000C4
instruction to protect against Chip Erase. See Kabylake H / LP SPI Programming KBL-U 0x000000C4
guide for further details. Note: This setting should be set to '0' if there are not
KBL-H 0x000000C4
Invalid instructions.
KBL-S 0x000000C4
HEDT 0x000000C4
Invalid Instruction 7 - This setting allows the customer to configure invalid KBL-Y 0x000000C7
instruction to protect against Chip Erase. See Kabylake H / LP SPI Programming KBL-U 0x000000C7
guide for further details. Note: This setting should be set to '0' if there are not
KBL-H 0x000000C7
Invalid instructions.
KBL-S 0x000000C7
HEDT 0x000000C7
Quad I/O Read Enabled KBL-Y No
Values: Yes/No - This setting allows the customer to enable support for Quad I/O KBL-U No
Read capabilities for flash components. See Kabylake H / LP SPI Programming guide KBL-H Yes
for further details.
KBL-S Yes
HEDT Yes

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 Image Creation: Intel® Flash Image Tool

Table 2-4. Intel® FIT - Flash Settings (Sheet 7 of 9)

Quad Output Read Enabled KBL-Y Yes
Values: Yes/No - This setting allows the customer to enable support for Quad KBL-U Yes
Output Read capabilities for flash components. See Kabylake H / LP SPI KBL-H Yes
Programming guide for further details.
KBL-S Yes
HEDT Yes
Read ID and Read Status clock frequency KBL-Y 17MHz
Values: 17MHz, 30MHz, 48MHz - This setting allows the customer to configure the KBL-U 17MHz
flash component clock frequency setting for Read ID and Read Status. See Kabylake KBL-H 17MHz
H / LP SPI Programming guide for further details.
KBL-S 17MHz
HEDT 17MHz

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Image Creation: Intel® Flash Image Tool

Table 2-4. Intel® FIT - Flash Settings (Sheet 8 of 9)

# Parameter Platform Settings
Write and Erase clock frequency KBL-Y 48MHz
Values: 17MHz, 30MHz, 48MHz - This setting allows the customer to configure the KBL-U 48MHz
flash component clock frequency setting for Write and Erase. See Kabylake H / LP KBL-H 48MHz
SPI Programming guide for further details.
KBL-S 48MHz
HEDT 48MHz
Click on Flash Settings in the left tabs menu> VSCC Table is expanded by default:

# Parameter Platform Settings

Flash Settings - VSCC Table
VSCC Entries
7
W25Q128BV
VSCC Entry

8
Name - This setting allow the OEM input a name designation for each flash KBL-Y Winbond
component being used. Note: This is a free form entry field it does not affect actual KBL-U Winbond
flash component operation.
KBL-H Winbond
KBL-S Winbond
HEDT Winbond
Vendor ID - This configures the JEDEC vendor specific byte ID of the SPI flash KBL-Y 0xEF
component. See Kabylake H / LP SPI Programming guide for further details. KBL-U 0xEF
KBL-H 0xEF
KBL-S 0xEF
HEDT 0xEF
Device ID 0 - This configures the JEDEC device specific byte ID 0 of the SPI flash KBL-Y 0x40
component. See Kabylake H / LP SPI Programming guide for further details. KBL-U 0x40
KBL-H 0x40
KBL-S 0x40
HEDT 0x40
Device ID 1 - This configures the JEDEC device specific byte ID 1 of the SPI flash KBL-Y 0x18
component. See Kabylake H / LP SPI Programming guide for further details. KBL-U 0x18
KBL-H 0x18
KBL-S 0x18
HEDT 0x18

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 Image Creation: Intel® Flash Image Tool

Table 2-4. Intel® FIT - Flash Settings (Sheet 9 of 9)

+ Add VSCC Entry

9
Click on Flash Settings in the left tabs menu> BIOS Configuration is expanded by default:

# Parameter Platform Settings

BIOS Configuration KBL-Y 64KB
Top Swap Block Size KBL-U 64KB

11 Values: 64KB, 128KB, 256KB, 512KB, 1MB - This configures the Top Swap Block
size for the platform. For further details see Kabylake H / LP Platform Controller Hub
KBL-H
KBL-S
64KB
64KB
EDS.
HEDT 64KB

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Image Creation: Intel® Flash Image Tool

Table 2-5. Intel® FIT - Intel® ME Kernel (Sheet 1 of 6)

Click on Intel® ME Kernel in the left tabs menu> Processor is expanded by default:

# Parameter Platform Settings

Intel® ME Kernel - Processor

1
Processor Emulation KBL-Y No Emulation
Values: No Emulation KBL-U No Emulation
EMULATE Intel® vPro (TM) capable Processor KBL-H EMULATE Intel®
EMULATE Intel® Core (TM) branded Processor vPro (TM) capable
Processor
EMULATE Intel® Celeron (R) branded Processor
EMULATE Intel®
EMULATE Intel® Pentium (R) branded Processor KBL-S
vPro (TM) capable
EMULATE Intel® Xeon (R) branded Processor Processor
EMULATE Intel® Xeon (R) Manageability capable Processor
This setting determines processor type to be emulated on pre-production silicon. HEDT EMULATE Intel®
Set this parameter to the type of processor that the target system will use during Core (TM)
production. This field will emulate that processor class for pre-production silicon. It branded
is necessary to set this to Emulate Intel® vPro™ Processor in order to enable Processor
Intel® AMT.
Missing Processor Detection Alert KBL-Y NA
Values: Yes/No - This setting determines if missing processor detection is KBL-U NA
enabled on Desktop / Workstation platforms. Note: This feature will only work if KBL-H No
the platform has the appropriate glue logic present.
KBL-S No
HEDT No
Click on Intel® ME Kernel in the left tabs menu> Intel® ME Firmware Update is expanded by default:

# Parameter Platform Settings

Intel® ME Kernel - Intel® ME Firmware Update

2
Firmware Update OEM ID - This setting allows configuration of an OEM unique ID KBL-Y 0 string
to ensure that customers can only update their platform with images from the OEM KBL-U 0 string
of the platform.
KBL-H 0 string
KBL-S 0 string
HEDT 0 string

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Table 2-5. Intel® FIT - Intel® ME Kernel (Sheet 2 of 6)

Hide Intel® MEBx Firmware Update Control KBL-Y No
Values: Yes/No - This setting allows the customer to hide the Firmware Update KBL-U No
option in the Intel® MEBx interface. KBL-H No
KBL-S No
HEDT No

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Table 2-5. Intel® FIT - Intel® ME Kernel (Sheet 3 of 6)

# Parameter Platform Settings
Intel® ME Region Flash Protection Override KBL-Y Yes
Values: Yes/No - This setting enables descriptor unlock of the Intel® ME Region KBL-U Yes
when the HMRFPO message is sent to firmware prior to BIOS End of POST. KBL-H Yes
KBL-S Yes
HEDT Yes
Click on Intel® ME Kernel in the left tabs menu> Intel® ME Services Configuration is expanded by default:

# Parameter Platform Settings

Intel® ME Kernel - Intel® Services Configuration

3
ODM ID used by Intel® Services - This setting is for entering the ODM ID for KBL-Y 0x00000000
Intel® Services to identify the ODM Board builder. Note: This ID is either KBL-U 0x00000000
generated by or registered with Intel® Services Web servers.
KBL-H 0x00000000
KBL-S 0x00000000
HEDT 0x00000000
System Integrator ID used by Intel® Services - This setting is for entering the KBL-Y 0x00000000
System Integrator ID for Intel® Services to identify the System Integrator. Note: KBL-U 0x00000000
This ID is either generated by or registered with Intel® Services Web servers.
KBL-H 0x00000000
KBL-S 0x00000000
HEDT 0x00000000
Reserved ID used by Intel® Services - This setting is for entering the Reserved KBL-Y 0x00000000
ID for Intel® Services currently not used. KBL-U 0x00000000
KBL-H 0x00000000
KBL-S 0x00000000
HEDT 0x00000000
Click on Intel® ME Kernel in the left tabs menu> Image Identification is expanded by default:

# Parameter Platform Settings

Intel® ME Kernel - Image Identification

4
OEM Tag - This is a free form 32bit field that allows the OEM to configure their own KBL-Y 0x00000000
unique identifier in the firmware image. KBL-U 0x00000000
KBL-H 0x00000000
KBL-S 0x00000000
HEDT 0x00000000

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 Image Creation: Intel® Flash Image Tool

Table 2-5. Intel® FIT - Intel® ME Kernel (Sheet 4 of 6)

Click on Intel® ME Kernel in the left tabs menu> MCTP Configuration is expanded by default:

# Parameter Platform Settings

Intel® ME Kernel - MCTP Configuration

5
MCTP Stack Configuration KBL-Y 0x920030
Defines the Intel® ME’s 8-bits MCTP Endpoint ID’s for each SMBus physical KBL-U 0x920030
interface (SMBus, SMLink0, and SMLink1). These values are needed for FW to KBL-H 0x920030
communicate with MCTP end points. For each of these 3 bytes, a value of 0x00
KBL-S 0x920030
means not used, and values 0xFF or 0x01 - 0x07 or 0x20 - 0x2F are not allowed.
HEDT 0x920030
MctpEspiEnabled KBL-Y No
Value: Yes/No KBL-U No
KBL-H No
KBL-S No
HEDT No
MctpDevicePortEc KBL-Y 0x0
KBL-U 0x0
KBL-H 0x0
KBL-S 0x0
HEDT 0x0
MctpDevicePortSio KBL-Y 0x00
KBL-U 0x00
KBL-H 0x00
KBL-S 0x00
HEDT 0x00
MctpDevicePortIsh KBL-Y 0x00
KBL-U 0x00
KBL-H 0x00
KBL-S 0x00
HEDT 0x00
MctpDevicePortBmc KBL-Y 0x00
KBL-U 0x00
KBL-H 0x00
KBL-S 0x00
HEDT 0x00

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Image Creation: Intel® Flash Image Tool

Table 2-5. Intel® FIT - Intel® ME Kernel (Sheet 5 of 6)

Click on Intel® ME Kernel in the left tabs menu> Firmware Diagnostics is expanded by default:

# Parameter Platform Settings

Intel® ME Kernel - Firmware Diagnostics

6
Automatic Built in Self Test KBL-Y Disabled
Values: Enabled/Disabled KBL-U Disabled
This setting enables the firmware Automatic Built in Self Test which is executed KBL-H Disabled
during first platform boot after initial image flashing. KBL-S Disabled
HEDT Disabled
Click on Intel® ME Kernel in the left tabs menu> Post Manufacturing Lock is expanded by default:

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 Image Creation: Intel® Flash Image Tool

Table 2-5. Intel® FIT - Intel® ME Kernel (Sheet 6 of 6)

# Parameter Platform Settings
Intel® Post Manufacturing Lock

7
Post Manufacturing NVAR Configuration Enabled KBL-Y Yes
Values: Yes/No KBL-U Yes
This setting determines if modifications to Customer configurable NVARs is to be KBL-H Yes
allowed after close of manufacturing. KBL-S Yes
HEDT Yes
Click on Intel® ME Kernel in the left tabs menu> Reserved is expanded by default:

# Parameter Platform Settings

Intel® ME Kernel - Reserved

8
Reserved KBL-Y No
Values: Yes/No KBL-U No
KBL-H No
KBL-S No
HEDT No

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Table 2-6. Intel® FIT - Intel® AMT (Sheet 1 of 7)

Click on Intel® AMT in the left tabs menu> Intel® AMT is expanded by default:

# Parameter Platform Settings

Intel® AMT - Intel® AMT Configuration

1
Intel® AMT Supported KBL-Y No
Values: Yes/No - This setting allows customers to disable Intel® AMT on the KBL-U No
platform and force the platform into Standard Manageability mode. Note: If this KBL-H No
setting has been set to disabled Intel® AMT cannot be re-enabled once the
KBL-S No
descriptor has been locked. This setting applies to Desktop and Workstation only.
HEDT No
Intel® ME Network Services Supported KBL-Y Yes
Values: Yes/No - This setting allows customers to enable / disable Intel® ME KBL-U Yes
Network Services on the platform. Note: This setting and TLS needs to be KBL-H Yes
enabled for proper operation of Intel® Authenticate (Corporate Only). In addition
KBL-S Yes
if this setting is disabled Intel® AMT will also be disabled.
HEDT No
Intel® Manageability Application Supported KBL-Y No
Values: Yes/No - This setting allows customers to force Intel® AMT enabled KBL-U No
platforms to operate in Standard Manageability mode. Note: This setting only KBL-H No
applies to Desktop and Workstation platforms.
KBL-S No
HEDT No
Manageability Application initial power-up state KBL-Y Disabled
Values: Enabled/Disabled KBL-U Disabled
This setting allows customers to determine the power up state for Intel® AMT or KBL-H Disabled
Standard Manageability. Note: If this setting is disabled Intel® AMT or Standard KBL-S Disabled
Manageability can still be re-enabled through the Intel® MEBx interface.
HEDT Disabled
Intel® AMT Idle Timeout KBL-Y 0xFFFF
Values: 0xFFFF - This setting configures the idle timeout value before Intel® KBL-U 0xFFFF
AMT enters into an off state. KBL-H 0xFFFF
KBL-S 0xFFFF
HEDT NA
Intel® AMT Watchdog Automatic Reset Enabled KBL-Y No
Values: Yes/No - This setting allows customers to enable the Intel® ME KBL-U No
firmware to trigger an automatic platform reset if either the MEI or Agent KBL-H No
Presence are in a hung state. Note: This feature only allows one reset at a time
KBL-S No
when the watchdog expires. After this feature has triggered a reset, it must be
re-armed for reuse via management console. HEDT No

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 Image Creation: Intel® Flash Image Tool

Table 2-6. Intel® FIT - Intel® AMT (Sheet 2 of 7)

Click on Intel® AMT in the left tabs menu> KVM Configuration is expanded by default:

# Parameter Platform Settings

Intel® AMT - KVM Configuration

2
Firmware KVM Screen Blanking KBL-Y No
Values: Yes/No - This setting enables KVM Screen blanking capabilities in the KBL-U No
firmware image. Note: This feature is dependent on processor level support. KBL-H No
KBL-S No
HEDT No
KVM Redirection Supported KBL-Y Yes
Values: Yes/No - This setting allows OEMs to enable / disable the KVM KBL-U Yes
Redirection capabilities of the firmware. Note: If this setting has been set to KBL-H Yes
disabled it cannot be re-enabled once the descriptor has been locked.
KBL-S Yes
HEDT No
Click on Intel® AMT in the left tabs menu> Provisioning Configuration is expanded by default:

# Parameter Platform Settings

Intel® AMT - Provisioning Configuration

3
Embedded Host Based Configuration KBL-Y No
Values: Yes/No - This setting allows customers to enable / disable Embedded KBL-U No
Host Based Configuration. Important - EHBC is primarily intended for use in KBL-H No
embedded systems as it offers less user privacy/security protection than may be
KBL-S No
appropriate for business client systems.
HEDT NA
Note: The Intel® FIT tool will not adjust the Redirection Privacy/Security value
based on selection here. Please set security level as needed.
PKI Domain Name Suffix - This setting allow OEMs to pre-configure the
Domain Name Suffix used for PKI provisioning in their firmware image. Note:
For normal out-of-box provisioning functionality this setting should be left empty.

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Image Creation: Intel® Flash Image Tool

Table 2-6. Intel® FIT - Intel® AMT (Sheet 3 of 7)

Click on Intel® AMT in the left tabs menu> OEM Customizable Certificate 1 is expanded by default:

# Parameter Platform Settings

Intel® AMT - OEM Customizable Certificate 1

4
Certificate Enabled KBL-Y No
Values: Yes/No - This setting allows customers to enable PKI provisioning KBL-U No
Custom Certificate 1. KBL-H No
KBL-S No
HEDT NA
Certificate Friendly Name - This setting allows customers to assign a user
friendly name for PKI provisioning Custom Certificate 1. Maximum of 32
characters.
Certificate Stream - This setting allows customers to input hash stream for PKI
provisioning Custom Certificate 1. If enabled the certificate will be used in
addition to those already pre-loaded in base firmware during provisioning. Note:
If the platform is un-configured the Custom Certificate Hash will be deleted.
Click on Intel® AMT in the left tabs menu> OEM Customizable Certificate 2 is expanded by default:

# Parameter Platform Settings

Intel® AMT - OEM Customizable Certificate 2

5
Certificate Enabled KBL-Y No
Values: Yes/No - This setting allows customers to enable PKI provisioning KBL-U No
Custom Certificate 2. KBL-H No
KBL-S No
HEDT NA
Certificate Friendly Name - This setting allows customers to assign a user
friendly name for PKI provisioning Custom Certificate 2. Maximum of 32
characters.
Certificate Stream - This setting allows customers to input hash stream for PKI
provisioning Custom Certificate 2. If enabled the certificate will be used in
addition to those already pre-loaded in base firmware during provisioning. Note:
If the platform is un-configured the Custom Certificate Hash will be deleted.

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 Image Creation: Intel® Flash Image Tool

Table 2-6. Intel® FIT - Intel® AMT (Sheet 4 of 7)

Click on Intel® AMT in the left tabs menu> OEM Customizable Certificate 3 is expanded by default:

# Parameter Platform Settings

Intel® AMT - OEM Customizable Certificate 3

6
Certificate Enabled KBL-Y No
Values: Yes/No - This setting allows customers to enable PKI provisioning KBL-U No
Custom Certificate 3. KBL-H No
KBL-S No
HEDT NA
Certificate Friendly Name - This setting allows customers to assign a user
friendly name for PKI provisioning Custom Certificate 3. Maximum 32 characters.
Certificate Stream - This setting allows customers to input hash stream for PKI
provisioning Custom Certificate 3. If enabled the certificate will be used in
addition to those already pre-loaded in base firmware during provisioning. Note:
If the platform is un-configured the Custom Certificate Hash will be deleted.
Click on Intel® AMT in the left tabs menu> OEM Default Certificate 1 is expanded by default:

# Parameter Platform Settings

Intel® AMT - OEM Default Certificate 1

7
Certificate Enabled KBL-Y No
Values: Yes/No - This setting allows customers to enable PKI provisioning KBL-U No
Default certificate 1. KBL-H No
KBL-S No
HEDT NA
Certificate Friendly Name - This setting allows customers to assign a user
friendly name for PKI provisioning Default Certificate 1. Maximum 32 characters.
Certificate Stream - This setting allows customers to input hash stream for PKI
provisioning custom certificate 1. Note: Default Certificates if enabled will be
used in addition to those already pre-loaded in firmware during provisioning.
Unlike Customizable Certificates the Default Certificates are not deleted when
the platform is un-provisioned.

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Table 2-6. Intel® FIT - Intel® AMT (Sheet 5 of 7)

Click on Intel® AMT in the left tabs menu> OEM Default Certificate 2 is expanded by default:

# Parameter Platform Settings

Intel® AMT - OEM Default Certificate 2

8
Certificate Enabled KBL-Y No
Values: Yes/No - This setting allows customers to enable PKI provisioning KBL-U No
Default certificate 2. KBL-H No
KBL-S No
HEDT NA
Certificate Friendly Name - This setting allows customers to assign a user
friendly name for PKI provisioning Default Certificate 2. Maximum 32 characters.
Certificate Stream - This setting allows customers to input hash stream for PKI
provisioning custom certificate 2. Note: Default Certificates if enabled will be
used in addition to those already pre-loaded in firmware during provisioning.
Unlike Customizable Certificates the Default Certificates are not deleted when
the platform is un-provisioned.
Click on Intel® AMT in the left tabs menu> OEM Default Certificate 3 is expanded by default:

# Parameter Platform Settings

Intel® AMT - OEM Default Certificate 3

9
Certificate Enabled KBL-Y No
Values: Yes/No - This setting allows customers to enable PKI provisioning KBL-U No
Default certificate 3. KBL-H No
KBL-S No
HEDT NA
Certificate Friendly Name - This setting allows customers to assign a user
friendly name for PKI provisioning Default Certificate 3. Maximum 32 characters.
Certificate Stream - This setting allows customers to input hash stream for PKI
provisioning custom certificate 3. Note: Default Certificates if enabled will be
used in addition to those already pre-loaded in firmware during provisioning.
Unlike Customizable Certificates the Default Certificates are not deleted when
the platform is un-provisioned.

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 Image Creation: Intel® Flash Image Tool

Table 2-6. Intel® FIT - Intel® AMT (Sheet 6 of 7)

Click on Intel® AMT in the left tabs menu> OEM Default Certificate 4 is expanded by default:

# Parameter Platform Settings

Intel® AMT - OEM Default Certificate 4

10
Certificate Enabled KBL-Y No
Values: Yes/No - This setting allows customers to enable PKI provisioning KBL-U No
Default certificate 4. KBL-H No
KBL-S No
HEDT NA
Certificate Friendly Name - This setting allows customers to assign a user
friendly name for PKI provisioning Default Certificate 4.
Certificate Stream - This setting allows customers to input hash stream for PKI
provisioning custom certificate 4. Note: Default Certificates if enabled will be
used in addition to those already pre-loaded in firmware during provisioning.
Unlike Customizable Certificates the Default Certificates are not deleted when
the platform is un-provisioned.
Click on Intel® AMT in the left tabs menu> OEM Default Certificate 5 is expanded by default:

# Parameter Platform Settings

Intel® AMT - OEM Default Certificate 5

11
Certificate Enabled KBL-Y No
Values: Yes/No - This setting allows customers to enable PKI provisioning KBL-U No
Default certificate 5. KBL-H No
KBL-S No
HEDT NA
Certificate Friendly Name - This setting allows customers to assign a user
friendly name for PKI provisioning Default Certificate 5.
Certificate Stream - This setting allows customers to input hash stream for PKI
provisioning custom certificate 5. Note: Default Certificates if enabled will be
used in addition to those already pre-loaded in firmware during provisioning.
Unlike Customizable Certificates the Default Certificates are not deleted when
the platform is un-provisioned.

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Image Creation: Intel® Flash Image Tool

Table 2-6. Intel® FIT - Intel® AMT (Sheet 7 of 7)

Click on Intel® AMT in the left tabs menu> Redirection Configuration is expanded by default:

# Parameter Platform Settings

Intel® AMT - Redirection Configuration

12
Redirection Localized Language - This setting allows customers to configure KBL-Y English
which localized language will be used initially by firmware for user consent KBL-U English
output information (Examples: May be displayed before SOL / KVM session
KBL-H English
starts).
KBL-S English
HEDT NA
Redirection Privacy / Security Level - This setting allows customers to KBL-Y Default
configure the Privacy and Security level for redirection operations. KBL-U Default
Default enables all redirection ports (User consent is configurable). KBL-H Default
Enhanced - Enables all redirection ports. (User consent is required and cannot KBL-S Default
be disabled).
HEDT NA
Extreme - Disables Redirection and Remote Configuration / Client Control Mode.
Note: The Intel® FIT tool will not adjust the Embedded Host Based
Configuration value based on selection here. Please set EHBC to yes or no as
needed.
Click on Intel® AMT in the left tabs menu> TLS Configuration is expanded by default:

Intel® AMT - TLS Configuration

13
# Parameter Platform Settings
Transport Layer Security Supported KBL-Y Yes
Values: Yes/No - This setting allows customers to enable / disable firmware KBL-U Yes
Transport Layer Security support. Note: If this is disabled TLS will be KBL-H Yes
permanently disabled in the firmware image. This setting needs to be enabled
KBL-S Yes
along with along with the Intel® ME Network Services Supported for proper
operation of the Intel® Authenticate (Corporate Only) feature. HEDT NA

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 Image Creation: Intel® Flash Image Tool

Table 2-7. Intel® FIT - Intel® Platform Protection (Sheet 1 of 5)

Click on Platform Protection in the left tabs menu> Content Protection is expanded by default:

# Parameter Platform Settings

Platform Protection - Content Protection

1
PAVP Supported KBL-Y Yes
Values: Yes/No KBL-U Yes
This setting determines if the Protected Audio Video Path (PAVP) feature will be KBL-H Yes
permanently disabled in the FW image. KBL-S Yes
HEDT NA
LSPCON Internal Display Port 1 - LSPCON / 4K KBL-Y None
Values: None, Port B, Port C, Port D KBL-U None
This setting determines which port for LSPCON will be connected to the HDCP 2.2 KBL-H None
bridge adapter Display 1. KBL-S None
HEDT NA
HDCP Internal Display Port 1 - 5K KBL-Y None
Values: None, Port A, Port B, Port C, Port D KBL-U None
This setting determines which port is connected for 5K output on the Internal KBL-H None
Display 1. KBL-S None
Note: HEDT NA
Both Display Port 1 & 2 need to be configured for proper operation.

HDCP Internal Display Port 2 - 5K KBL-Y None

Values: None, Port A, Port B, Port C, Port D KBL-U None
This setting determines which port is connected for 5K output on the Internal KBL-H None
Display 2. KBL-S None
Note: HEDT NA
Both Display Port 1 & 2 need to be configured for proper operation.

Click on Platform Protection in the left tabs menu> Graphics uController is expanded by default:

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Table 2-7. Intel® FIT - Intel® Platform Protection (Sheet 2 of 5)

# Parameter Platform Settings
Platform Protection - Graphics UController

2
GuC Encryption Key KBL-Y 0x00000000
Values: This option is for entering the raw hash 256 bit string or certificate file for KBL-U 0x00000000
the Graphics uController. KBL-H 0x00000000
KBL-S 0x00000000
HEDT NA
Click on Platform Protection in the left tabs menu> Hash Key Configuration for Bootguard / ISH is expanded by default:

# Parameter Platform Settings

Platform Protection - Hash Key Configuration for Bootguard / ISH

3
OEM Public Key Hash KBL-Y 0x00000000
Values: This option is for entering the raw hash string or certificate file for Boot KBL-U 0x00000000
Guard and ISH. This 256-bit field represents the SHA-256 hash of the OEM public KBL-H 0x00000000
key corresponding to the private key used to sign the BIOS-SM or ISH image.
KBL-S 0x00000000
Please see Appendix F for further details.
HEDT 0x00000000
Click on Platform Protection in the left tabs menu> Boot Guard Configuration is expanded by default:

# Parameter Platform Settings

Platform Protection - Boot Guard Configuration

4
Key Manifest ID KBL-Y 0x0
Values: This option is for entering the hash of another public key, used by the KBL-U 0x0
ACM to verify the Boot Policy Manifest. KBL-H 0x0
KBL-S 0x0
HEDT 0x0

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 Image Creation: Intel® Flash Image Tool

Table 2-7. Intel® FIT - Intel® Platform Protection (Sheet 3 of 5)

# Parameter Platform Settings
Boot Guard Profile Configuration KBL-Y Boot Guard
Values: Boot Guard Profile 0 - No_FVME Profile 0 -
No_FVME
Boot Guard Profile 1 - VE
Boot Guard
Boot Guard Profile 2 - VME KBL-U
Profile 0 -
Boot Guard Profile 3 - VM No_FVME
Boot Guard Profile 4 - FVE Boot Guard
Boot Guard Profile 5 - FVME KBL-H Profile 0 -
This option configures which Boot Guard Policy Profile will be used. No_FVME
KBL-S Boot Guard
Profile 0 -
No_FVME
HEDT
Boot Guard
Profile 0 -
No_FVME
CPU Debugging KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This setting determines if CPU debug modes will be displayed. When set to KBL-H Enabled
'Enabled' CPU debugging is enabled. KBL-S Enabled
HEDT Enabled
BSP Initialization KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This setting determines BSP behavior when it receives an INIT signal. When set to KBL-H Enabled
'Enabled' BSP will behave normally if it receives an INIT (Disabled BSP Initialization KBL-S Enabled
(DBI) bit=0). When set to ‘Disabled’ BSP will shutdown if it receives an INIT (“DBI”
HEDT Enabled
bit=1).
Click on Platform Protection in the left tabs menu> Intel® PTT Configuration is expanded by default:

# Parameter Platform Settings

Platform Protection - Intel® PTT Configuration

5
Intel® PTT initial power-up state KBL-Y Enabled
Values: Enabled/Disabled - This setting determines if Intel® PTT is enabled on KBL-U Enabled
platform power-up. KBL-H Enabled
KBL-S Disabled
HEDT Disabled
Intel® PTT Supported KBL-Y Yes
Values: Yes/No - This setting permanently disables Intel® PTT in the firmware KBL-U Yes
image. KBL-H Yes
KBL-S Yes
HEDT Yes

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Table 2-7. Intel® FIT - Intel® Platform Protection (Sheet 4 of 5)

Intel® PTT Supported [FPF] KBL-Y Yes
Values: Yes/No - This setting will permanently disable Intel® PTT through KBL-U Yes
platform FPFs. Caution: Using this option will permanently disable Intel® PTT on KBL-H Yes
the platform hardware.
KBL-S Yes
HEDT Yes
Intel® PTT RTC Clear Detection KBL-Y Enabled
This setting determines how the Intel(R) PTT will behave when RTC (CMOS) clear is KBL-U Enabled
triggered on the platform. When Disabled Intel(R) PTT will bypass normal RTC KBL-H Enabled
clear behavior. Note: For designs where there is no Physical Coin Cell Battery, for
KBL-S Enabled
backing up data stored in the RTC well, this setting should be set to 'Disabled'.
HEDT Enabled

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 Image Creation: Intel® Flash Image Tool

Table 2-7. Intel® FIT - Intel® Platform Protection (Sheet 5 of 5)

Click on Platform Protection in the left tabs menu> TPM Over SPI Bus Configuration is expanded by default:

# Parameter Platform Settings

Platform Protection - TPM Over SPI Bus Configuration

6
TPM Clock Frequency KBL-Y 17MHz
Values: 17MHz, 30MHz, 48MHz - This setting determines the clock frequency KBL-U 17MHz
setting to be used for the TPM over SPI bus. KBL-H 17MHz
KBL-S 17MHz
HEDT 17MHz
TPM Over SPI Bus Enabled KBL-Y No
Values: Yes/No - This setting determines if TPM over SPI bus is enabled on the KBL-U No
platform. KBL-H No
KBL-S No
HEDT No

# Parameter Platform Settings

BIOS Guard Protection Override Enabled KBL-Y No
This setting allows BIOS Guard to bypass SPI flash controller protections (i.e. KBL-U No
7 Protected Range Registers and Top Swap). KBL-H
KBL-S
No
No
HEDT No

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Image Creation: Intel® Flash Image Tool

Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 1 of 20)

Click on Integrated Clock Controller in the left tabs menu> Integrated Clock Controller Policies are expanded by
default:

# Parameter Platform Settings

Integrated Clock Controller - Integrated Clock Controller Policies

1
Register Lock Policy KBL-Y 0: Default
Values: 0:Default, 1:All Locked, 2: All Unlocked KBL-U 0: Default
This parameter controls Register lock policy. It defines the integrated clock KBL-H 0: Default
registers left accessible to host after EOP. KBL-S 0: Default
0:Default - Locks all but the registers associated to adjust BCLK nominal HEDT 0: Default
clock frequency and spread settings.
1:All Locked - Locks all integrated clock registers and disables all writes
to these registers via Intel® ME Firmware.
2:All Unlocked - Leaves pre-EOP integrated clock registers unlocked.This
option is mainly used for debug purpose.

Double click on value column of this parameter to choose from available

options.
Boot Profile KBL-Y Profile 0
KBL-U Profile 0
This parameter allows user to select default profile to be used by the final KBL-H Profile 0
generated SPI Flash binary image for the target platform at boot time. KBL-S Profile 0
HEDT Profile 0
Selection is limited to the profiles defined under “Integrated Clock
Controller | Profiles “up to maximum 16 profiles. Profiles can be added by
clicking on “Add profile” button under “Integrated Clock Controller |
Profiles”.

The ‘Record #’ refers to profile created under the “Integrated Clock

Controller | Profiles”.
Default boot profile for system is Profile 0.

Double click on value column of this parameter to choose from available

options.

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 2 of 20)

# Parameter Platform Settings
Failsafe Profile KBL-Y Profile 0
KBL-U Profile 0
This parameter specifies the profile index of the fail-safe profile. On boot KBL-H Profile 0
failure detection or CMOS clear the Intel® ME Firmware will revert to this KBL-S Profile 0
profile if “Integrated Clock Controller |Integrated Clock Controller
HEDT Profile 0
Policies - Profile Changeable “ is set to True. If profile Changeable
parameter is set to False, User can not select Failsafe Boot Profile and
profile 0 will be selected as a fail safe boot profile by default.

The ‘Record #’ refers to profile created under the “Integrated Clock

Controller | Profiles”.
Default Failsafe boot profile for system is Profile 0.

Double click on value column of this parameter to choose from available

options.
Profile Changeable KBL-Y true
KBL-U true
Possible configuration: True/False. KBL-H true
KBL-S true
This parameter controls if BIOS or 3rd party application can select boot HEDT true
profile or not. When set to true, it allows user to change boot profile via
BIOS or 3rd party application. When set to false, Runtime change to boot
profile is not allowed and boot profile selected by “Integrated Clock
Controller |Integrated Clock Controller Policies - Boot Profile “
parameter will be used to boot platform.

Double click on value column of this parameter to choose from available

options.
Click on Integrated Clock Controller in the left tabs menu> Profiles are expanded by default:

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 3 of 20)

# Parameter Platform Settings
Integrated Clock Controller - Profiles - Profile 0 KBL-Y Standard
KBL-U Standard
2 Note: Intel® ME image has to be loaded to enable other ICC profile KBL-H Standard
settings. KBL-S Standard
HEDT Standard
For KBL-Y/U, Intel® FIT provides 2 pre- defined ICC profiles to choose
from.
•Standard: This profile provides default settings for standard
configuration, no adaptive clocking is allowed. Platform clocks output
internal and external are driven from USB3PCIE clock. Default clock
frequency is 100 MHz with 0.47%DownSpread. BCLK clock source should
be turned off in this case to save power.
•Adaptive: This profile provides Wimax/3G friendly configuration. This
profile will configure the platform based on the Adaptive profile allowing
adaptive clocking adjustment for BCLK clock source to reduce EMI
interference. It supports default clock frequency of 98.875 MHz with 0.48%
Downspread.

For KBL-H/S/HEDT, Intel® FIT provides 5 pre-defined ICC profiles to

choose from.

•Standard: Same as KBL-Y/U

•Adaptive: Same as KBL-Y/U
•Overclocking: This profile provides overclocking friendly configuration.
Both Clock sources BCLK and USB3PCIE are turned on in this case. clock
frequency for BCLK and USB3PCIE clock is 100 MHz with
0.5%DownSpread. BCLK overclocking can be supported using BCLK clock
source.
•Overclocking Plus: This profile provides overclocking > 100MHZ and
<166 MHZ for BCLK overclocking.

•Overclocking Ext: This profile provides overclocking > 100MHZ and

supports all OC frequency ranges or BCLK overclocking.

Recommendation on choosing Overclocking profile from available

pre-define profiles

• Overclocking Ext profile supports single 100-340 MHZ BCLK

frequency range. customers are recommended to use this profile for
BCLK Overclocking.
• Overclocking and Overclocking Plus profiles still exists but are not
expected to be used as OC >166 Mhz is not possible using these
profiles.
• Incase customers want to use Overclocking and overclocking plus
profiles, it supports BCLK frequency only upto 166 MHz; customers
are recommended to set BCLK PLL Clock Source Max. frequency to
166 MHz for these profiles.

Note: User can select pre-defined profiles via “Integrated Clock

Controller | Profiles - Profile Type “ parameter

User can add up to maximum 16 profiles.To add new profile, please use
“Integrated Clock Controller | Profiles - + Add Profile Button”
Profile Name KBL-Y Profile 0
KBL-U Profile 0
This parameter allows user to customize profile name for easy KBL-H Profile 0
identification. By default it uses pre-defined profile name like Profile 0. KBL-S Profile 0
HEDT Profile 0

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 4 of 20)

Profile Type KBL-Y Standard
KBL-U Standard
Available ICC profiles for KBL-Y/U are Standard and Adaptive. KBL-H Standard
KBL-S Standard
Available ICC profiles for KBL-H/S/HEDT are Standard, Adaptive, HEDT Standard
OverClocking, OverClockingPlus and OverClocking Ext.

This parameter indicates which pre- defined profile selected for each
profile#.

Double click on value column of this parameter to choose from available

options.
+ Add Profile Button KBL-Y
KBL-U
3 This button is used to add new ICC profile. User can add up to maximum
16 profiles. New profile will be added under “Integrated Clock
KBL-H
KBL-S
Controller | Profiles” tab.
HEDT

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 5 of 20)

Click on Integrated Clock Controller in the left tabs menu> Profiles >Profile> Bclk Clock Configuration is
expanded by default:

# Parameter Platform Settings

Integrated Clock Controller - Profiles - Profile
BclkClockConfiguration

4
BCLK Clock Frequency - This parameter allows user to select the nominal KBL-Y
frequency for the selected clock. Range is limited based on the Clock Range KBL-U
Definition record and HW SKU.
KBL-H
Standard Setting Profile Type - Option is grayed out.
KBL-S
Adaptive Setting Profile Type - Option is able to be edited.
HEDT
Overclocking Setting Profile Type - Option is able to be edited.
Overclocking Plus Setting Profile Type - Option is able to be edited.
Overclocking Ext. Setting Profile Type - Option is able to be edited.

BCLK Spread Setting - This parameter allows user to select the KBL-Y
percentage of Spread setting for the selected clock. Range is limited based KBL-U
on the Clock Range Definition record and HW SKU.
KBL-H
BCLK Clock Frequency
KBL-S
Standard Setting Profile Type - Option is grayed out.
HEDT
Adaptive Setting Profile Type - Option is able to be edited.
Overclocking Setting Profile Type - Option is able to be edited.
Overclocking Plus Setting Profile Type - Option is able to be edited.
Overclocking Ext. Setting Profile Type - Option is able to be edited.

Click on Integrated Clock Controller in the left tabs menu> Profiles >Profile> Clock Range Definition Record is
expanded by default:

# Parameter Platform Settings

Integrated Clock Controller - Profiles - Profile
ClockRangeDefinitionRecord

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 6 of 20)

BCLK PLL Clock Source Maximum Frequency - This parameter allows KBL-Y
user to specify the maximum frequency that can be applied to BCLK clock KBL-U
source when overclocking the platform. Value is limited by divider/
KBL-H
frequency limits determined by HW SKU, and cannot be less than 100 MHz.
KBL-S
Standard Setting Profile Type - Option is grayed out.
HEDT
Adaptive Setting Profile Type - Option is able to be edited.
Overclocking Setting Profile Type - Option is able to be edited.
Overclocking Plus Setting Profile Type - Option is able to be edited.
Overclocking Ext. Setting Profile Type - Option is able to be edited.

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 7 of 20)

# Parameter Platform Settings
BCLK PLL Clock Source Minimum Frequency - This parameter allows KBL-Y
user to specify the minimum frequency that can be applied to BCLK clock KBL-U
source when underclocking the platform. Value is limited by divider/
KBL-H
frequency limits determined by HW SKU, and cannot be greater than 100
MHz. KBL-S
Standard Setting Profile Type - Option is grayed out. HEDT
Adaptive Setting Profile Type - Option is able to be edited.
Overclocking Setting Profile Type - Option is able to be edited.
Overclocking Plus Setting Profile Type - Option is able to be edited.
Overclocking Ext. Setting Profile Type - Option is able to be edited.

BCLK SSC Changes Allowed - This parameter allows user to specify if the KBL-Y
spread mode and percentage is allowed to be modified at runtime or not. if KBL-U
set to “True’: Runtime modification is allowed.
KBL-H
Standard Setting Profile Type - Option is grayed out.
KBL-S
Adaptive Setting Profile Type - Option is able to be edited.
HEDT
Overclocking Setting Profile Type - Option is able to be edited.
Overclocking Plus Setting Profile Type - Option is able to be edited.
Overclocking Ext. Setting Profile Type - Option is able to be edited.
BCLK SSC Halt Allowed - This parameter allows user to select if the KBL-Y
spread generator can be disabled at runtime or not.if set to “True”, the KBL-U
spread generator can be enabled and disabled at runtime.
KBL-H
Standard Setting Profile Type - Option is grayed out.
KBL-S
Adaptive Setting Profile Type - Option is able to be edited.
HEDT
Overclocking Setting Profile Type - Option is able to be edited.
Overclocking Plus Setting Profile Type - Option is able to be edited.
Overclocking Ext. Setting Profile Type - Option is able to be edited.
BCLK SSC Percentage - This parameter Specifies the maximum KBL-Y
percentage of spread adjustment that can be applied to the clock. Value is KBL-U
specified in 1/100th of percent(50=0.5%)
KBL-H
Standard Setting Profile Type - Option is grayed out.
KBL-S
Adaptive Setting Profile Type - Option is able to be edited.
HEDT
Overclocking Setting Profile Type - Option is able to be edited.
Overclocking Plus Setting Profile Type - Option is able to be edited.
Overclocking Ext. Setting Profile Type - Option is able to be edited.
Click on Integrated Clock Controller in the left tabs menu> Profiles >Profile> Clock Output Configuration is
expanded by default:

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 8 of 20)

# Parameter Platform Settings

Integrated Clock Controller - Profiles - Profile Clock Output
Configuration

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 9 of 20)

# Parameter Platform Settings
ITPXDP,SRC[0:5] KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
These parameters come under the Power Management section and they KBL-H Enabled
control Enabling /Disabling of specific Output Clocks at boot time. KBL-S Enabled
HEDT Enabled
These settings should match with platform
hardware design.

For CRB, recommend keeping defaults for

bring up with Intel® ME FW.

These parameters are specifically used to Enable/Disable the respective

CLKOUT_XXX differential output buffers

SRC0[6:15] KBL-Y Disabled

Values: Enabled/Disabled KBL-U Disabled
These parameters come under the Power Management section and they KBL-H Enabled
control Enabling /Disabling of specific Output Clocks at boot time. KBL-S Enabled
These settings should match with platform HEDT Enabled
hardware design.

For CRB, recommend keeping defaults for

bring up with Intel® ME FW.

These parameters are specifically used to Enable/Disable the respective

CLKOUT_XXX differential output buffers
SRC1 KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
Enables or Disables the CLKOUT_SRC1 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
SRC2 KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
Enables or Disables the CLKOUT_SRC2 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
SRC3 KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
Enables or Disables the CLKOUT_SRC3 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
SRC4 KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
Enables or Disables the CLKOUT_SRC4 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
SRC5 KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
Enables or Disables the CLKOUT_SRC5 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
SRC6 KBL-Y NA
Values: Enabled/Disabled KBL-U NA
Enables or Disables the CLKOUT_SRC6 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 10 of 20)

SRC7 KBL-Y NA
Values: Enabled/Disabled KBL-U NA
Enables or Disables the CLKOUT_SRC7 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 11 of 20)

# Parameter Platform Settings
SRC8 KBL-Y NA
Values: Enabled/Disabled KBL-U NA
Enables or Disables the CLKOUT_SRC8 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
SRC9 KBL-Y NA
Values: Enabled/Disabled KBL-U NA
Enables or Disables the CLKOUT_SRC9 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
SRC10 KBL-Y NA
Values: Enabled/Disabled KBL-U NA
Enables or Disables the CLKOUT_SRC10 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
SRC11 KBL-Y NA
Values: Enabled/Disabled KBL-U NA
Enables or Disables the CLKOUT_SRC11 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
SRC12 KBL-Y NA
Values: Enabled/Disabled KBL-U NA
Enables or Disables the CLKOUT_SRC12 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
SRC13 KBL-Y NA
Values: Enabled/Disabled KBL-U NA
Enables or Disables the CLKOUT_SRC13 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
SRC14 KBL-Y NA
Values: Enabled/Disabled KBL-U NA
Enables or Disables the CLKOUT_SRC14 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
SRC15 KBL-Y NA
Values: Enabled/Disabled KBL-U NA
Enables or Disables the CLKOUT_SRC15 differential output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
LPC0[1:0] KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
These parameters are used to control Enabling/Disabling of CLKRUN KBL-H Enabled
support for CLKOUT_LPC clocks. KBL-S Enabled
HEDT Enabled
For CRB, recommend keeping defaults for
bring up with Intel® ME FW

LPC1 KBL-Y Enabled

Values: Enabled/Disabled KBL-U Enabled
Enables or Disables the CLKOUT_LPC1 single ended output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 12 of 20)

CPUPCIBCLK KBL-Y NA
Values: Enabled/Disabled KBL-U NA
Enables or Disables the CPUPCIBCLK output buffer. KBL-H Enabled
KBL-S Enabled
HEDT Enabled

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 13 of 20)

Click on Integrated Clock Controller in the left tabs menu> Profiles >Profile> Power Management Configuration is
expanded by default:

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 14 of 20)

# Parameter Platform Settings
Integrated Clock Controller - Profiles - Profile
PwrManagementConfiguration

7
Configuring CLKREQ# and assigning GPIO depends on how CLKOUT_SRCx
configuration via FIT is done (Enabled or Disabled) and if CLKREQ is
required or not.

Please refer to Appendix B.3 (How to configure CLKREQ#

parameters) for the detail of CLKREQ configuration for SRC Output
clocks. Please configure CLKREQ parameters accordingly.

SRC0[5:0] CLKREQ# Mapping KBL-Y GPP_B5

Possible configuration: Select one of the GPIOs from the list to map it as a KBL-U GPP_B5
CLKREQ# for specific SRC# Output clock. KBL-H GPP_B5
This parameter controls association of dynamic CLKREQ control with SRC KBL-S GPP_B5
(PCIe) clocks.
HEDT GPP_B5

SRC[15:6] CLKREQ# Mapping - KBL-H/S/HEDT Only

Possible configuration: Select one of the GPIOs from the list to map it as a
CLKREQ# for specific SRC# Output put clock.
This parameter controls association of dynamic CLKREQ control with SRC
(PCIe) clocks.

SRC1 CLKREQ# Mapping KBL-Y GPP_B6

Assign the CLKREQ# signal associated with CLKOUT_SRC1. KBL-U GPP_B6
KBL-H GPP_B6
KBL-S GPP_B6
HEDT GPP_B6
SRC2 CLKREQ# Mapping KBL-Y GPP_B7
Assign the CLKREQ# signal associated with CLKOUT_SRC2. KBL-U GPP_B7
KBL-H GPP_B7
KBL-S GPP_B7
HEDT GPP_B7
SRC3 CLKREQ# Mapping KBL-Y GPP_B8
Assign the CLKREQ# signal associated with CLKOUT_SRC3. KBL-U GPP_B8
KBL-H GPP_B8
KBL-S GPP_B8
HEDT GPP_B8
SRC4 CLKREQ# Mapping KBL-Y GPP_B9
Assign the CLKREQ# signal associated with CLKOUT_SRC4. KBL-U GPP_B9
KBL-H GPP_B9
KBL-S GPP_B9
HEDT GPP_B9
SRC5 CLKREQ# Mapping KBL-Y GPP_B10
Assign the CLKREQ# signal associated with CLKOUT_SRC5. KBL-U GPP_B10
KBL-H GPP_B10
KBL-S GPP_B10
HEDT GPP_B10

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 15 of 20)

SRC6 CLKREQ# Mapping KBL-Y NA
Assign the CLKREQ# signal associated with CLKOUT_SRC6. KBL-U NA
KBL-H GPP_H0
KBL-S GPP_H0
HEDT GPP_H0
SRC7 CLKREQ# Mapping KBL-Y NA
Assign the CLKREQ# signal associated with CLKOUT_SRC7. KBL-U NA
KBL-H GPP_H1
KBL-S GPP_H1
HEDT GPP_H1
SRC8 CLKREQ# Mapping KBL-Y NA
Assign the CLKREQ# signal associated with CLKOUT_SRC8. KBL-U NA
KBL-H GPP_H2
KBL-S GPP_H2
HEDT GPP_H2
SRC9 CLKREQ# Mapping KBL-Y NA
Assign the CLKREQ# signal associated with CLKOUT_SRC9. KBL-U NA
KBL-H GPP_H3
KBL-S GPP_H3
HEDT GPP_H3
SRC10 CLKREQ# Mapping KBL-Y NA
Assign the CLKREQ# signal associated with CLKOUT_SRC10. KBL-U NA
KBL-H GPP_H4
KBL-S GPP_H4
HEDT GPP_H4

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 16 of 20)

# Parameter Platform Settings
SRC11 CLKREQ# Mapping KBL-Y NA
Assign the CLKREQ# signal associated with CLKOUT_SRC11. KBL-U NA
KBL-H GPP_H5
KBL-S GPP_H5
HEDT GPP_H5
SRC12 CLKREQ# Mapping KBL-Y NA
Assign the CLKREQ# signal associated with CLKOUT_SRC1. KBL-U NA
KBL-H GPP_H6
KBL-S GPP_H6
HEDT GPP_H6
SRC13 CLKREQ# Mapping KBL-Y NA
Assign the CLKREQ# signal associated with CLKOUT_SRC13. KBL-U NA
KBL-H GPP_H7
KBL-S GPP_H7
HEDT GPP_H7
SRC14 CLKREQ# Mapping KBL-Y NA
Assign the CLKREQ# signal associated with CLKOUT_SRC14. KBL-U NA
KBL-H GPP_H8
KBL-S GPP_H8
HEDT GPP_H8
SRC15 CLKREQ# Mapping KBL-Y NA
Assign the CLKREQ# signal associated with CLKOUT_SRC15. KBL-U NA
KBL-H GPP_H9
KBL-S GPP_H9
HEDT GPP_H9
CLKREQ SRC0 [5:0] Enable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC[5:0] KBL-S Enabled
HEDT Enabled
CLKREQ SRC [15:6] enable - KBL-H Only
This parameter allows user to Enable/Disable the dynamic clock request
control by the assigned CLKREQ# for CLKOUT_SRC[15:6]
CLKREQ SRC1 Enable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC1. KBL-S Enabled
HEDT Enabled
CLKREQ SRC2 Enable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC2. KBL-S Enabled
HEDT Enabled
CLKREQ SRC3 Enable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC3. KBL-S Enabled
HEDT Enabled
CLKREQ SRC4 Enable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC4. KBL-S Enabled
HEDT Enabled

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 17 of 20)

CLKREQ SRC5 Enable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC5. KBL-S Enabled
HEDT Enabled
CLKREQ SRC6 Enable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC6. KBL-S Enabled
HEDT Enabled
CLKREQ SRC7 Enable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC7. KBL-S Enabled
HEDT Enabled
# Parameter Platform Settings
CLKREQ SRC8 Enable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC8. KBL-S Enabled
HEDT Enabled
CLKREQ SRC9 Enable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC9. KBL-S Enabled
HEDT Enabled
CLKREQ SRC10 Enable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC10. KBL-S Enabled
HEDT Enabled
CLKREQ SRC11 Enable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC11. KBL-S Enabled
HEDT Enabled
CLKREQ SRC12 Enable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC12. KBL-S Enabled
HEDT Enabled
CLKREQ SRC13 Enable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC13. KBL-S Enabled
HEDT Enabled
CLKREQ SRC14 Enable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC14. KBL-S Enabled
HEDT Enabled
CLKREQ SRC15 Enable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
This parameter allows user to Enable/Disable the dynamic clock request KBL-H Enabled
control by the assigned CLKREQ# for CLKOUT_SRC15. KBL-S Enabled
HEDT Enabled

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 18 of 20)

CLKRUN LPC0 Enable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable CLKRUN protocol on LPC1 KBL-H Enabled
output clock. KBL-S Enabled
HEDT Enabled
CLKRUN LPC1 Enable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable CLKRUN protocol on LPC1 KBL-H Enabled
output clock. KBL-S Enabled
HEDT Enabled
Clock Gating of Core 24MHz Crystal Disable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter decides if Crystal is forced to be on or is subjected to KBL-H Enabled
dynamic shutdown. Crystal Oscillator can dynamically shut down upon KBL-S Enabled
iSCLK detecting idle condition on all clock consumers of crystal clock.
HEDT Enabled
Note: Recommendation is to leave setting at default value.
Clock Gating of CLKOUT_ITPxDP Disable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable dynamic control of KBL-H Enabled
CLKOUT_ITPxDP.When enabled, CLKOUT_ITPxDP is subject to gating/ KBL-S Enabled
ungating control by CPUBCLKREQ
HEDT Enabled
Note: Recommendation is to leave setting at default value.

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 19 of 20)

# Parameter Platform Settings
Clock Gating of CLKOUT_CPUBCLK Disable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable dynamic control of KBL-H Enabled
CLKOUT_CPUBCLK.When enabled, CLKOUT_CPUBCLK is subject to gating/ KBL-S Enabled
ungating control by CPUBCLKREQ
HEDT Enabled
These settings should match with platform
hardware design.
Note: Recommendation is to leave setting at default value.
Clock Gating of CLKOUT_CPUPCIBCLK Disable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
This parameter allows user to Enable/Disable dynamic control of KBL-H Enabled
CLKOUT_CPUPCIBCLK.When enabled,CLKOUT_CPUPCIBCLK is subject to KBL-S Enabled
gating/ungating control by CPUPCIBCLKREQ
HEDT Enabled
Note: Recommendation is to leave setting at default value.
Clock Gating of CLKOUT_CPUNSSC Disable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable dynamic control of KBL-H Enabled
CLKOUT_CPUNSSC.When enabled,CLKOUT_CPUNSSC is subject to gating/ KBL-S Enabled
ungating control by CPUNSSCCLKREQ
HEDT Enabled
Note: Recommendation is to leave setting at default value.
Clock Gating of CLKOUT_CPUNSSC[P/N] Disable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable dynamic control of KBL-H Enabled
CLKOUT_CPUNSSC[P/N] .Controls the parked state of True (P) and KBL-S Enabled
Complementary (N) copies of the differential pair when
HEDT Enabled
CLKOUT_CPUNSSC[P/N] is dynamically gated under S0 idle state.
Note: Recommendation is to leave setting at default value.
Clock Gating of icc_rosc_fast_clk Disable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable dynamic clock gate on KBL-H Enabled
icc_rosc_fast_clk KBL-S Enabled
Note: Recommendation is to leave setting at default value. HEDT Enabled
Clock Gating of icc_rosc_side_clk Disable KBL-Y Enabled
Values: Enabled/Disabled KBL-U Enabled
This parameter allows user to Enable/Disable dynamic clock gate on KBL-H Enabled
icc_rosc_side_clk KBL-S Enabled
Note: Recommendation is to leave setting at default value. HEDT Enabled
USB3Gen2PCIe PLL OFF Wait KBL-Y 8us
This parameter allows user to set G2PLLOFFWAIT timer value. Once timer KBL-U 8us
expires and there are no wake events, the USB3Gen2PCIe PLL can be KBL-H 8us
shutdown
KBL-S 8us
Note: Recommendation is to leave setting at default value.
HEDT 8us
USB3Gen2PCIe PLL PG Wait KBL-Y 8us
This parameter allows user to set G2PLLPGWAIT timer value. Once timer KBL-U 8us
expires and there are no wake events, the USB3Gen2PCIe PLL can be KBL-H 8us
shutdown
KBL-S 8us
Note: Recommendation is to leave setting at default value.
HEDT 8us
Run-time S0 SUS PG Wait KBL-Y 8us
This parameter allows user to set SUSPGWAIT timer value. Once timer KBL-U 8us
expires and there are no wake events, the USB3Gen2PCIe PLL can be KBL-H 8us
shutdown
KBL-S 8us
Note: Recommendation is to leave setting at default value.
HEDT 8us

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Table 2-8. Intel® FIT - Integrated Clock Controller (Sheet 20 of 20)

# Parameter Platform Settings
Crystal Oscillator Fast Restart Mode KBL-Y 01b
This parameter allows user to configure Crystal Oscillator Fast Restart KBL-U 01b
Mode. In all below listed fast start modes, iSCLK kickstarts crystal XIN/ KBL-H 01b
XOUT by injecting a 24Mhz kickstart reference clock onto these pins.
KBL-S 01b
HEDT 01b
Note: Configuration of this parameter co-relates to configuration of Clock
Gating of Core 24MHz Crystal Disable parameter.

If Clock Gating of Core 24MHz Crystal Disable is set to ‘Disable’, Crystal

Oscillator Fast Restart Mode parameter has no impact.

If Clock Gating of Core 24MHz Crystal Disable is set to ‘Enabled’, Crystal

Oscillator Fast Restart Mode parameter must be set to ‘01b’. Other value
like ‘00b’ can cause wake latency conflict which can cause platform
functional issue.
BCLK PLL Shutdown Wait Interval KBL-Y 8us
This parameter allows user to enable Dynamic power management of BCLK KBL-U 8us
PLL. Upon the event that all conditions (other than this wait timer itself) KBL-H 8us
are satisfied for iSCLK dynamic PLL shutdown, a timer is started.Once it
KBL-S 8us
expires and there are no wake events, this PLL will shutdown.
HEDT 8us
Note: Recommendation is to leave setting at default value.
24MHz Crystal Shutdown Wait Interval KBL-Y 8us
This parameter allows user to Enable Dynamic power management of KBL-U 8us
Crystal. Upon the event that all conditions (other than this wait timer itself) KBL-H 8us
are satisfied for iSCLK crystal shutdown, a timer is started. Once it expires
KBL-S 8us
and there are no wake events, iSCLK will shutdown crystal.
HEDT 8us
Note: Recommendation is to leave setting at default value.

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Table 2-9. Intel® FIT - Intel® Networking & Connectivity (Sheet 1 of 5)

Click on Networking & Connectivity in the left tabs menu> Wired LAN Configuration is expanded by default:

# Parameter Platform Settings

Networking & Connectivity - Wired LAN Configuration

1
GbE MAC SMBus Address KBL-Y 0x70
KBL-U 0x70
KBL-H 0x70
KBL-S 0x70
HEDT 0x70
GbE SMBus Address Enabled KBL-Y Yes
Values: Yes/No - This enables the Intel® Integrated Wired LAN MAC KBL-U Yes
SMBus address. Note: This setting must be enabled if using Intel® KBL-H Yes
Integrated LAN.
KBL-S Yes
HEDT Yes
Intel® PHY over PCIe Enabled KBL-Y Yes
Values: Yes/No - This setting allows customers to enable / disable Intel® KBL-U Yes
Integrated LAN operation over the PCIe Port selected by the GbE PCIe Port KBL-H Yes
Select option.
KBL-S Yes
HEDT Yes
GbE PCIe Port Select KBL-Y PORT5
Values: PORT3, PORT4, PORT5, PORT9, PORT10 - This setting allows KBL-U PORT4
customers to configure the PCIe Port that will Intel® Integrated LAN will KBL-H PORT4
operate on.
KBL-S PORT4
HEDT PORT4
GbE PHY SMBus Address KBL-Y 0x64
This setting configures Intel® Integrated Wired LAN SMBus address to KBL-U 0x64
accept SMBus cycles from the MAC. Note: Recommended setting is 64h. KBL-H 0x64
KBL-S 0x64
HEDT 0x64

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Table 2-9. Intel® FIT - Intel® Networking & Connectivity (Sheet 2 of 5)

LAN Power Well KBL-Y SLP_LAN#
Values: Core Well, Sus Well, ME Well, SLP_LAN - This setting allows KBL-U SLP_LAN#
customers to configure the power well that will be used by Intel® KBL-H SLP_LAN#
Integrated LAN.
KBL-S SLP_LAN#
Note: Recommended setting is SLP_LAN#.
HEDT SLP_LAN#

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Table 2-9. Intel® FIT - Intel® Networking & Connectivity (Sheet 3 of 5)

# Parameter Platform Settings
LAN PHY Power Control GPD11 Signal Configuration KBL-Y LANPHYPC
Values: GPD11, LANPHYPC - This setting allows the customer to assign KBL-U LANPHYPC
the LAN PHY Power Control signal to GbE or as GDP11. Note: If using KBL-H LANPHYPC
Intel® Integrated LAN this setting should be set to "Enable as LANPHYPC".
KBL-S LANPHYPC
HEDT LANPHYPC
LAN PHY Power Up Time KBL-Y 100ms
Values: 50ms, 100ms KBL-U 100ms
KBL-H 100ms
KBL-S 100ms
HEDT 100ms
Intel® Integrated Wired LAN Enable KBL-Y Enabled
Values: Enabled/Disabled - This setting enables or disables the Intel® KBL-U Enabled
Integrated LAN. KBL-H Enabled
KBL-S Enabled
HEDT Enabled
PHY Connection KBL-Y PHY on SMLink0
Values: No PHY connected, PHY on SMLink0 KBL-U PHY on SMLink0
KBL-H PHY on SMLink0
KBL-S PHY on SMLink0
HEDT PHY on SMLink0
Click on Networking & Connectivity in the left tabs menu> Wireless LAN Configuration is expanded by default:

# Parameter Platform Settings

Networking & Connectivity - Wireless LAN Configuration

2
CLINK Enabled KBL-Y
Values: Yes/No - This setting allows customers to enable / disable the KBL-U
Wireless LAN CLINK signal through Intel® ME firmware. Note: For using KBL-H
Intel® vPro™ Wireless solutions this should be set to "Yes".
KBL-S
HEDT No
MLK_RSTB Buffer Driven Mode KBL-Y NA
Values: Open-drained/Driven - This soft strap determines the control KBL-U NA
mode for the output buffer MLK_RST # signal. KBL-H Driven
KBL-S Driven
HEDT NA

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Table 2-9. Intel® FIT - Intel® Networking & Connectivity (Sheet 4 of 5)

WLAN Microcode - This setting allow OEMs to configure which Intel® KBL-Y 0x24FD
Wireless LAN card microcode to load into the firmware image. KBL-U 0x24FD
KBL-H 0x24FD
KBL-S 0x24FD
HEDT NA

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Table 2-9. Intel® FIT - Intel® Networking & Connectivity (Sheet 5 of 5)

# Parameter Platform Settings
WLAN Power Well KBL-Y SLP_WLAN#
Values: Disabled, Sus Well, ME Well, SLP_M#||SPDA, SLP_WLAN# KBL-U SLP_WLAN#
- This setting allows OEMs to configure the power well that will be used by KBL-H SLP_WLAN#
Intel® Wireless LAN.
KBL-S SLP_WLAN#
WLAN Sleep via SLP_WLAN# (default)
HEDT Disabled
Note: Recommended setting is SLP_WLAN#.
SLP_WLAN# / GPD9 Signal Configuration KBL-Y SLP_WLAN#
Values: SLP_WLAN#, GPD9 - This setting allows the customer to assign KBL-U SLP_WLAN#
the WLAN Power Control signal to WLAN or as GDP9. Note: If using KBL-H SLP_WLAN#
Intel® Wireless LAN this setting should be set to "Enable as SLP_WLAN#".
KBL-S SLP_WLAN#
HEDT LANPHYPC
Click on Networking & Connectivity in the left tabs menu> Intel® NFC Configuration is expanded by default:

# Parameter Platform Settings

3 Networking & Connectivity Intel® NFC Configuration

Enable Near Field Communication KBL-Y Yes

Values: Yes/No - This setting allows OEMs to enable / disable Near Field KBL-U Yes
Communication support in the Intel® ME firmware. KBL-H No
Note: If NFC device is not in the system configuration, leave this setting KBL-S No
set to No, as it can cause BIST testing to fail.
HEDT NA
NFC SMBus Address KBL-Y 0x29-NXP
Values: 0x28-NXP, 0x29-NXP, 0x2A-NXP, 0x2B-NXP - This setting KBL-U 0x29-NXP
allows OEMs to configure the SMBus address for the NFC adapter being KBL-H 0x28-NXP
used.
KBL-S 0x29-NXP
HEDT NA

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Table 2-10. Intel® FIT - Flex I/O (Sheet 1 of 13)

Click on Flex I/O in the left tabs menu> Intel® RST for PCIe Configuration is expanded by default:

# Parameter Platform Settings

Flex I/O - Intel® RST for PCIe Configuration

1
Intel® RST for PCIe-C1 Select x2 or x4 KBL-Y NA
Values: x2, x4 - This is used to configure NAND Cycle routers for the KBL-U NA
Intel® RST for PCIe interface as either x2 or x4 lane operation on PCIe KBL-H x2
Controller 1.
KBL-S x2
HEDT x4
Intel® RST for PCIe-C2 Select x2 or x4 KBL-Y x2
Values: x2, x4 - This is used to configure NAND Cycle routers for the KBL-U x2
Intel® RST for PCIe interface as either x2 or x4 lane operation on PCIe KBL-H x2
Controller 2.
KBL-S x2
HEDT x2

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Table 2-10. Intel® FIT - Flex I/O (Sheet 2 of 13)

Intel® RST for PCIe-C3 Select x2 or x4 KBL-Y x2
Values: x2, x4 - This is used to configure NAND Cycle routers for the KBL-U x4
Intel® RST for PCIe interface as either x2 or x4 lane operation on PCIe KBL-H x4
Controller 3.
KBL-S x4
HEDT x2

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Table 2-10. Intel® FIT - Flex I/O (Sheet 3 of 13)

# Parameter Platform Settings
Intel® RST for PCIe Controller 1 KBL-Y NA
Values: 1x4, 2x2 - This is used to configure PCIe Controller 1 for KBL-U NA
Intel® RST for PCIe interface as either x2 or x4 lane operation on PCIe KBL-H x2
Controller 1.
KBL-S x2
HEDT x4
Intel® RST for PCIe Controller 2 KBL-Y x2
Values: 1x4, 2x2 - This is used to configure PCIe Controller 2 for KBL-U x2
Intel® RST for PCIe interface as either x2 or x4 lane operation on PCIe KBL-H x2
Controller 2.
KBL-S x2
HEDT x2
Intel® RST for PCIe Controller 3 KBL-Y x2
Values: 1x4, 2x2 - This is used to configure PCIe Controller 3 for KBL-U x4
Intel® RST for PCIe interface as either x2 or x4 lane operation on PCIe KBL-H x4
Controller 3.
KBL-S x4
HEDT x2
PCIe Controller 2 Port 1 SRIS Enabled KBL-Y No
Values: Yes/ No - This is used to configure SRIS Port 1 for Intel® RST KBL-U No
for PCIe on PCIe Controller 2. Note: Configuration of this setting is only KBL-H NA
required if the NVM device will be connected external SATA Express
KBL-S NA
cable.
HEDT NA
PCIe Controller 2 Port 2 SRIS Enabled KBL-Y No
Values: Yes/ No - This is used to configure SRIS Port 2 for Intel® RST KBL-U No
for PCIe on PCIe Controller 2.Note: Configuration of this setting is only KBL-H NA
required if the NVM device will be connected external SATA Express
KBL-S NA
cable.
HEDT NA
PCIe Controller 2 Port 3 SRIS Enabled KBL-Y No
Values: Yes/ No - This is used to configure SRIS Port 3 for Intel® RST KBL-U No
for PCIe on PCIe Controller 2. Note: Configuration of this setting is only KBL-H NA
required if the NVM device will be connected external SATA Express
KBL-S NA
cable.
HEDT NA
PCIe Controller 2 Port 4 SRIS Enabled KBL-Y No
Values: Yes/ No - This is used to configure SRIS Port 4 for Intel® RST KBL-U No
for PCIe on PCIe Controller 2. Note: Configuration of this setting is only KBL-H NA
required if the NVM device will be connected external SATA Express
KBL-S NA
cable.
HEDT NA
PCIe Controller 3 Port 1 SRIS Enabled KBL-Y No
Values: Yes/ No - This is used to configure SRIS Port 1 for Intel® RST KBL-U No
for PCIe on PCIe Controller 3. Note: Configuration of this setting is only KBL-H No
required if the NVM device will be connected external SATA Express
KBL-S No
cable.
HEDT No
PCIe Controller 3 Port 2 SRIS Enabled KBL-Y No
Values: Yes/ No - This is used to configure SRIS Port 2 for Intel® RST KBL-U No
for PCIe on PCIe Controller 3. Note: Configuration of this setting is only KBL-H No
required if the NVM device will be connected external SATA Express
KBL-S No
cable.
HEDT No
PCIe Controller 3 Port 3 SRIS Enabled KBL-Y No
Values: Yes/ No - This is used to configure SRIS Port 3 for Intel® RST KBL-U No
for PCIe on PCIe Controller 3. Note: Configuration of this setting is only KBL-H No
required if the NVM device will be connected external SATA Express
KBL-S No
cable.
HEDT No
PCIe Controller 3 Port 4 SRIS Enabled KBL-Y No
Values: Yes/ No - This is used to configure SRIS Port 4 for Intel® RST KBL-U No
for PCIe on PCIe Controller 3. Note: Configuration of this setting is only KBL-H No
required if the NVM device will be connected external SATA Express
KBL-S No
cable.
HEDT No

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Table 2-10. Intel® FIT - Flex I/O (Sheet 4 of 13)

# Parameter Platform Settings
PCIe Controller 5 Port 1 SRIS Enabled KBL-Y NA
Values: Yes/ No - This is used to configure SRIS Port 1 for Intel® RST KBL-U NA
for PCIe on PCIe Controller 5. Note: Configuration of this setting is only KBL-H No
required if the NVM device will be connected external SATA Express
KBL-S No
cable.
HEDT
PCIe Controller 5 Port 2 SRIS Enabled KBL-Y NA
Values: Yes/ No - This is used to configure SRIS Port 2 for Intel® RST KBL-U NA
for PCIe on PCIe Controller 5. Note: Configuration of this setting is only KBL-H No
required if the NVM device will be connected external SATA Express
KBL-S No
cable.
HEDT
PCIe Controller 5 Port 3 SRIS Enabled KBL-Y NA
Values: Yes/ No - This is used to configure SRIS Port 3 for Intel® RST KBL-U NA
for PCIe on PCIe Controller 5. Note: Configuration of this setting is only KBL-H No
required if the NVM device will be connected external SATA Express
KBL-S No
cable.
HEDT
PCIe Controller 5 Port 4 SRIS Enabled KBL-Y NA
Values: Yes/ No - This is used to configure SRIS Port 4 for Intel® RST KBL-U NA
for PCIe on PCIe Controller 5. Note: Configuration of this setting is only KBL-H No
required if the NVM device will be connected external SATA Express
KBL-S No
cable.
HEDT
PCIe Controller 6 Port 1 SRIS Enabled KBL-Y NA
Values: Yes/ No - This is used to configure SRIS Port 1 for Intel® RST KBL-U NA
for PCIe on PCIe Controller 5. Note: Configuration of this setting is only KBL-H No
required if the NVM device will be connected external SATA Express
KBL-S No
cable.
HEDT
PCIe Controller 6 Port 2 SRIS Enabled KBL-Y NA
Values: Yes/ No - This is used to configure SRIS Port 2 for Intel® RST KBL-U NA
for PCIe on PCIe Controller 5. Note: Configuration of this setting is only KBL-H No
required if the NVM device will be connected external SATA Express
KBL-S No
cable.
HEDT
PCIe Controller 6 Port 3 SRIS Enabled KBL-Y NA
Values: Yes/ No - This is used to configure SRIS Port 3 for Intel® RST KBL-U NA
for PCIe on PCIe Controller 5. Note: Configuration of this setting is only KBL-H No
required if the NVM device will be connected external SATA Express
KBL-S No
cable.
HEDT
PCIe Controller 6 Port 4 SRIS Enabled KBL-Y NA
Values: Yes/ No - This is used to configure SRIS Port 4 for Intel® RST KBL-U NA
for PCIe on PCIe Controller 5. Note: Configuration of this setting is only KBL-H No
required if the NVM device will be connected external SATA Express
KBL-S No
cable.
HEDT
Click on Flex I/O in the left tabs menu> PCIe Lane Reversal Configuration is expanded by default:

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Table 2-10. Intel® FIT - Flex I/O (Sheet 5 of 13)

# Parameter Platform Settings
Flex I/O - PCIe Lane Reversal Configuration

2
PCIe Controller 1 Lane Reversal Enabled KBL-Y No
Values: Yes/ No - This setting allows the PCIe lanes on Controller 1 to KBL-U No
be reversed. Note: Refer to EDS for PCIe supported port KBL-H No
configurations. KBL-S No
HEDT No
PCIe Controller 2 Lane Reversal Enabled KBL-Y No
Values: Yes/ No - This setting allows the PCIe lanes on Controller 2 to KBL-U No
be reversed. Note: Refer to EDS for PCIe supported port KBL-H No
configurations. KBL-S No
HEDT No
PCIe Controller 3 Lane Reversal Enabled KBL-Y No
Values: Yes/ No - This setting allows the PCIe lanes on Controller 3 to KBL-U Yes
be reversed. Note: Refer to EDS for PCIe supported port KBL-H No
configurations. KBL-S No
HEDT No
PCIe Controller 4 Lane Reversal Enabled KBL-Y NA
Values: Yes/ No - This setting allows the PCIe lanes on Controller 4 to KBL-U NA
be reversed. Note: Refer to EDS for PCIe supported port KBL-H No
configurations. KBL-S No
HEDT No
PCIe Controller 5 Lane Reversal Enabled KBL-Y NA
Values: Yes/ No - This setting allows the PCIe lanes on Controller 5 to KBL-U NA
be reversed. Note: Refer to EDS for PCIe supported port KBL-H No
configurations. KBL-S No
HEDT No
PCIe Controller 6 Lane Reversal Enabled KBL-Y NA
Values: Yes/ No - This setting allows the PCIe lanes on Controller 6 to KBL-U NA
be reversed. Note: Refer to EDS for PCIe supported port KBL-H No
configurations. KBL-S No
HEDT Yes
Click on Flex I/O in the left tabs menu> PCIe Port Configuration is expanded by default:

# Parameter Platform Settings

Flex I/O - PCIe Port Configuration

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Table 2-10. Intel® FIT - Flex I/O (Sheet 6 of 13)

PCIe Controller 1 (Port 1-4) KBL-Y 1x4
Values: 4x1, (1x2, 2x1), 2x2, 1x4 - This setting controls PCIe Port KBL-U 4x1
configurations for PCIe Controller 1. For further details see Kabylake H / KBL-H 1x4
LP Platform Controller Hub EDS.
KBL-S 4x1
HEDT 4x1
PCIe Controller 2 (Port 5-8) KBL-Y 4x1
Values: 4x1, (1x2, 2x1), 2x2, 1x4 - This setting controls PCIe Port KBL-U 4x1
configurations for PCIe Controller 2. For further details see Kabylake H / KBL-H 4x1
LP Platform Controller Hub EDS.
KBL-S 4x1
HEDT 1x4
PCIe Controller 3 (Port 9-12) KBL-Y 4x1
Values: 4x1, (1x2, 2x1), 2x2, 1x4 - This setting controls PCIe Port KBL-U 1x4
configurations for PCIe Controller 3. For further details see Kabylake H / KBL-H 4x1
LP Platform Controller Hub EDS.
KBL-S 1x4
HEDT 1x4
PCIe Controller 4 (Port 13-16) KBL-Y NA
Values: 4x1, (1x2, 2x1), 2x2, 1x4 - This setting controls PCIe Port KBL-U NA
configurations for PCIe Controller 4. For further details see Kabylake H / KBL-H 1x2, 2x1
LP Platform Controller Hub EDS.
KBL-S 1x2, 2x1
HEDT 4x1
PCIe Controller 5 (Port 17-20) KBL-Y NA
Values: 4x1, (1x2, 2x1), 2x2, 1x4 - This setting controls PCIe Port KBL-U NA
configurations for PCIe Controller 5. For further details see Kabylake H / KBL-H 4x1
LP Platform Controller Hub EDS.
KBL-S 1x4
HEDT 4x1
PCIe Controller 6 (Port 21-24) KBL-Y NA
Values: 4x1, (1x2, 2x1), 2x2, 1x4 - This setting controls PCIe Port KBL-U NA
configurations for PCIe Controller 6. For further details see Kabylake H / KBL-H 4x1
LP Platform Controller Hub EDS.
KBL-S 1x4
HEDT 1x4
Click on Flex I/O in the left tabs menu> PCIe Gen3 PLL Clock Control is expanded by default:

# Parameter Platform Settings

Flex I/O - PCIe Gen3 PLL Clock Control

Secondary Gen3 PLL Enabled KBL-Y NA

Values: Yes, No - This setting determines which Gen3 PLL source clock KBL-U NA
PCIe Controller 6 (Port 21-24) will use. Note: When the Secondary Gen3 KBL-H No
PLL option is disabled PCIe Controller 6 (Port 21-24) will use Primary
KBL-S No
Gen3 PLL as the source clock.
HEDT No

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Table 2-10. Intel® FIT - Flex I/O (Sheet 7 of 13)

Click on Flex I/O in the left tabs menu> SATA / PCIe Combo Port Configuration is expanded by default:

# Parameter Platform Settings

Flex I/O - SATA / PCIe Combo Port Configuration

SATA / PCIe Combo Port 0 KBL-Y SATA

Values: SATA, PCIe (or GbE), GPIO - This setting configures the PCIe KBL-U SATA
port to operate as either: KBL-H GPIO
PCIe Port 7 or SATA Port 0 (LP) KBL-S GPIO
PCIe Port 9 or SATA Port 0 (H) HEDT PCIe (or GbE)
For further details on Flex I/O see Kabylake H / LP Platform Controller
Hub EDS.
SATA / PCIe Combo Port 1 KBL-Y GPIO
Values: SATA, PCIe (or GbE), GPIO - This setting configures the PCIe KBL-U SATA
port to operate as either: KBL-H GPIO
PCIe Port 8 or SATA Port 1 (LP) KBL-S GPIO
PCIe Port 10 or SATA Port 1 (H) HEDT PCIe (or GbE)
For further details on Flex I/O see Kabylake H / LP Platform Controller
Hub EDS.
SATA / PCIe Combo Port 2 KBL-Y PCIe (or GbE)
Values: SATA, PCIe (or GbE), GPIO - This setting configures the PCIe KBL-U PCIe (or GbE)
port to operate as either: KBL-H PCIe (or GbE)
PCIe Port 11 or SATA Port 1 (LP) KBL-S SATA
PCIe Port 13 or SATA Port 0 (H) HEDT SATA
For further details on Flex I/O see Kabylake H / LP Platform Controller
Hub EDS.
SATA / PCIe Combo Port 3 KBL-Y PCIe (or GbE)
Values: SATA, PCIe (or GbE), GPIO - This setting configures the PCIe KBL-U PCIe (or GbE)
port to operate as either: KBL-H PCIe (or GbE)
PCIe Port 12 or SATA Port 2 (LP) KBL-S SATA
PCIe Port 14 or SATA Port 1 (H) HEDT SATA
For further details on Flex I/O see Kabylake H / LP Platform Controller
Hub EDS.

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Table 2-10. Intel® FIT - Flex I/O (Sheet 8 of 13)

# Parameter Platform Settings
SATA / PCIe Combo Port 4 KBL-Y NA
Values: SATA, PCIe (or GbE), GPIO - This setting configures the PCIe KBL-U NA
port to operate as either: KBL-H GPIO
PCIe Port 15 or SATA Port 2 (H) KBL-S GPIO
For further details on Flex I/O see Kabylake H / LP Platform Controller HEDT SATA
Hub EDS.
SATA / PCIe Combo Port 5 KBL-Y NA
Values: SATA, PCIe (or GbE), GPIO - This setting configures the PCIe KBL-U NA
port to operate as either: KBL-H PCIe (or GbE)
PCIe Port 16 or SATA Port 3 (H) KBL-S PCIe (or GbE)
For further details on Flex I/O see Kabylake H / LP Platform Controller HEDT SATA
Hub EDS.
SATA / PCIe Combo Port 6 KBL-Y NA
Values: SATA, PCIe (or GbE), GPIO - This setting configures the PCIe KBL-U NA
port to operate as either: KBL-H PCIe (or GbE)
PCIe Port 17 or SATA Port 4 (H) KBL-S PCIe (or GbE)
For further details on Flex I/O see Kabylake H / LP Platform Controller HEDT SATA
Hub EDS.
SATA / PCIe Combo Port 7 KBL-Y NA
Values: SATA, PCIe (or GbE), GPIO - This setting configures the PCIe KBL-U NA
port to operate as either: KBL-H PCIe (or GbE)
PCIe Port 18 or SATA Port 5 (H) KBL-S PCIe (or GbE)
For further details on Flex I/O see Kabylake H / LP Platform Controller HEDT SATA
Hub EDS.
SATA / PCIe Combo Port 8 KBL-Y NA
Values: SATA, PCIe (or GbE), GPIO - This setting configures the PCIe KBL-U NA
port to operate as either: KBL-H PCIe (or GbE)
PCIe Port 19 or SATA Port 6 (H) KBL-S PCIe (or GbE)
For further details on Flex I/O see Kabylake H / LP Platform Controller HEDT SATA
Hub EDS.
SATA / PCIe Combo Port 9 KBL-Y NA
Values: SATA, PCIe (or GbE), GPIO - This setting configures the PCIe KBL-U NA
port to operate as either: KBL-H PCIe (or GbE)
PCIe Port 20 or SATA Port 7 (H) KBL-S PCIe (or GbE)
For further details on Flex I/O see Kabylake H / LP Platform Controller HEDT SATA
Hub EDS.
Click on Flex I/O in the left tabs menu> SATA / PCIe Combo Port Select Polarity is expanded by default:

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Table 2-10. Intel® FIT - Flex I/O (Sheet 9 of 13)

# Parameter Platform Settings
Flex I/O - SATA / PCIe Combo Port Select Polarity

Polarity Select SATA / PCIe Combo Port 0 KBL-Y SATA

Values: 0 = SATA/0 = PCIe - This setting is used to determine the KBL-U SATA
native mode configuration for SATA / PCIe Combo Port 0. KBL-H SATA
For further details on Flex I/O see Kabylake H / LP Platform Controller KBL-S SATA
Hub EDS.
HEDT PCIe
Polarity Select SATA / PCIe Combo Port 1 KBL-Y PCIe
Values: 0 = SATA/0 = PCIe - This setting is used to determine the KBL-U PCIe
native mode configuration for SATA / PCIe Combo Port 1. KBL-H SATA
For further details on Flex I/O see Kabylake H / LP Platform Controller KBL-S SATA
Hub EDS.
HEDT PCIe
Polarity Select SATA / PCIe Combo Port 2 KBL-Y PCIe
Values: 0 = SATA/0 = PCIe - This setting is used to determine the KBL-U PCIe
native mode configuration for SATA / PCIe Combo Port 2. KBL-H PCIe
For further details on Flex I/O see Kabylake H / LP Platform Controller KBL-S PCIe
Hub EDS.
HEDT SATA
Polarity Select SATA / PCIe Combo Port 3 KBL-Y PCIe
Values: 0 = SATA/0 = PCIe - This setting is used to determine the KBL-U PCIe
native mode configuration for SATA / PCIe Combo Port 3. KBL-H PCIe
For further details on Flex I/O see Kabylake H / LP Platform Controller KBL-S PCIe
Hub EDS.
HEDT SATA
Polarity Select SATA / PCIe Combo Port 4 KBL-Y NA
Values: 0 = SATA/0 = PCIe - This setting is used to determine the KBL-U NA
native mode configuration for SATA / PCIe Combo Port 4. KBL-H SATA
For further details on Flex I/O see Kabylake H / LP Platform Controller KBL-S SATA
Hub EDS.
HEDT PCIe
Polarity Select SATA / PCIe Combo Port 5 KBL-Y NA
Values: 0 = SATA/0 = PCIe - This setting is used to determine the KBL-U NA
native mode configuration for SATA / PCIe Combo Port 5. KBL-H SATA
For further details on Flex I/O see Kabylake H / LP Platform Controller KBL-S PCIe
Hub EDS.
HEDT PCIe
Polarity Select SATA / PCIe Combo Port 6 KBL-Y NA
Values: 0 = SATA/0 = PCIe - This setting is used to determine the KBL-U NA
native mode configuration for SATA / PCIe Combo Port 6. KBL-H SATA
For further details on Flex I/O see Kabylake H / LP Platform Controller KBL-S PCIe
Hub EDS.
HEDT SATA
Polarity Select SATA / PCIe Combo Port 7 KBL-Y NA
Values: 0 = SATA/0 = PCIe - This setting is used to determine the KBL-U NA
native mode configuration for SATA / PCIe Combo Port 7. KBL-H PCIe
For further details on Flex I/O see Kabylake H / LP Platform Controller KBL-S PCIe
Hub EDS.
HEDT PCIe
Polarity Select SATA / PCIe Combo Port 8 KBL-Y NA
Values: 0 = SATA/0 = PCIe - This setting is used to determine the KBL-U NA
native mode configuration for SATA / PCIe Combo Port 8. KBL-H PCIe
For further details on Flex I/O see Kabylake H / LP Platform Controller KBL-S PCIe
Hub EDS.
HEDT PCIe
Polarity Select SATA / PCIe Combo Port 9 KBL-Y NA
Values: 0 = SATA/0 = PCIe - This setting is used to determine the KBL-U NA
native mode configuration for SATA / PCIe Combo Port 9. KBL-H PCIe
For further details on Flex I/O see Kabylake H / LP Platform Controller KBL-S PCIe
Hub EDS.
HEDT PCIe

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Table 2-10. Intel® FIT - Flex I/O (Sheet 10 of 13)

Click on Flex I/O in the left tabs menu> USB3 Port Configuration is expanded by default:

# Parameter Platform Settings

Flex I/O - USB3 Port Configuration

USB3 / PCIe Combo Port 0 KBL-Y PCIe (or GbE)

Values: PCIe (or GbE), USB3 - This setting configures the PCIe port KBL-U USB3
to operate as either: KBL-H USB3
PCIe Port 1 or USB3 Port 5 (LP) KBL-S USB3
USB3 Port 7 or PCIe Port 1 (H) HEDT USB3
For further details on Flex I/O see Kabylake H / LP Platform Controller
Hub EDS.
USB3 / PCIe Combo Port 1 KBL-Y PCIe (or GbE)
Values: PCIe (or GbE), USB3 - This setting configures the PCIe port KBL-U USB3
to operate as either: KBL-H USB3
PCIe Port 6 or USB3 Port 2 (LP) KBL-S USB3
USB3 Port 8 or PCIe Port 2 (H) HEDT USB3
For further details on Flex I/O see Kabylake H / LP Platform Controller
Hub EDS.
USB3 / PCIe Combo Port 2 KBL-Y NA
Values: PCIe (or GbE), USB3 - This setting configures the PCIe port to KBL-U NA
operate as either USB3 Port 9 or PCIe Port 3. For further details on Flex KBL-H USB3
I/O see Kabylake H / LP Platform Controller Hub EDS. KBL-S PCIe (or GbE)
HEDT PCIe (or GbE)
USB3 / PCIe Combo Port 3 KBL-Y NA
Values: PCIe (or GbE), USB3 - This setting configures the PCIe port to KBL-U NA
operate as either USB3 Port 10 or PCIe Port 4. For further details on Flex KBL-H USB3
I/O see Kabylake H / LP Platform Controller Hub EDS.
KBL-S USB3
HEDT USB3

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Table 2-10. Intel® FIT - Flex I/O (Sheet 11 of 13)

Click on Flex I/O in the left tabs menu> XHCI Port Configuration is expanded by default:

# Parameter Platform Settings

Flex I/O - XHCI Port Configuration

8
XHCI Port 1 Ownership KBL-Y XHCI
Values: XHCI, Non-XHCI - This setting configures USB3 Port 1 to KBL-U XHCI
operate as either XHCI or Non-XHCI. For further details on Flex I/O see KBL-H XHCI
Kabylake H / LP Platform Controller Hub EDS.
KBL-S XHCI
HEDT XHCI
XHCI Port 2 Ownership KBL-Y XHCI
Values: XHCI, Non-XHCI - This setting configures USB3 Port 2 to KBL-U XHCI
operate as either XHCI or Non-XHCI. For further details on Flex I/O see KBL-H XHCI
Kabylake H / LP Platform Controller Hub EDS.
KBL-S XHCI
HEDT Non-XHCI
XHCI Port 3 Ownership KBL-Y XHCI
Values: XHCI, Non-XHCI - This setting configures USB3 Port 3 to KBL-U XHCI
operate as either XHCI or Non-XHCI. For further details on Flex I/O see KBL-H XHCI
Kabylake H / LP Platform Controller Hub EDS.
KBL-S XHCI
HEDT
XHCI Port 4 Ownership KBL-Y XHCI
Values: XHCI, Non-XHCI - - This setting configures USB3 Port 4 to KBL-U XHCI
operate as either XHCI or Non-XHCI. For further details on Flex I/O see KBL-H XHCI
Kabylake H / LP Platform Controller Hub EDS.
KBL-S XHCI
HEDT
XHCI Port 5 Ownership KBL-Y Non-XHCI
Values: XHCI, Non-XHCI - This setting configures USB3 Port 5 to KBL-U XHCI
operate as either XHCI or Non-XHCI. For further details on Flex I/O see KBL-H Non-XHCI
Kabylake H / LP Platform Controller Hub EDS.
KBL-S XHCI
HEDT

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Table 2-10. Intel® FIT - Flex I/O (Sheet 12 of 13)

XHCI Port 6 Ownership KBL-Y Non-XHCI
Values: XHCI, Non-XHCI - This setting configures USB3 Port 6 to KBL-U XHCI
operate as either XHCI or Non-XHCI. For further details on Flex I/O see KBL-H Non-XHCI
Kabylake H / LP Platform Controller Hub EDS.
KBL-S Non-XHCI
HEDT

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Table 2-10. Intel® FIT - Flex I/O (Sheet 13 of 13)

# Parameter Platform Settings
XHCI Port 7 Ownership KBL-Y NA
Values: XHCI, Non-XHCI - This setting configures USB3 Port 7 to KBL-U NA
operate as either XHCI or Non-XHCI. For further details on Flex I/O see KBL-H XHCI
Kabylake H / LP Platform Controller Hub EDS.
KBL-S XHCI
HEDT
XHCI Port 8 Ownership KBL-Y NA
Values: XHCI, Non-XHCI - This setting configures USB3 Port 8 to KBL-U NA
operate as either XHCI or Non-XHCI. For further details on Flex I/O see KBL-H XHCI
Kabylake H / LP Platform Controller Hub EDS.
KBL-S XHCI
HEDT
XHCI Port 9 Ownership KBL-Y NA
Values: XHCI, Non-XHCI - This setting configures USB3 Port 9 to KBL-U NA
operate as either XHCI or Non-XHCI. For further details on Flex I/O see KBL-H XHCI
Kabylake H / LP Platform Controller Hub EDS.
KBL-S XHCI
HEDT
XHCI Port 10 Ownership KBL-Y NA
Values: XHCI, Non-XHCI - This setting configures USB3 Port 10 to KBL-U NA
operate as either XHCI or Non-XHCI. For further details on Flex I/O see KBL-H Non-XHCI
Kabylake H / LP Platform Controller Hub EDS.
KBL-S Non-XHCI
HEDT

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Table 2-11. Intel® FIT - Internal PCH Buses (Sheet 1 of 11)

Click on Internal PCH Buses in the left tabs menu> OPI Configuration is expanded by default:

# Parameter Platform Settings

Internal PCH Buses - OPI Configuration KBL-Y
KBL-U
1 KBL-H
KBL-S
HEDT
OPI Link Speed KBL-Y
Values: GT2/GT4 - This setting configures the OPI / DMI Link Speed. KBL-U
For further details see Kabylake PCH EDS. KBL-H
KBL-S
HEDT
OPI Link Width KBL-Y
Values: 1 Lanes, 2 Lanes, 4 Lanes, 8 Lanes - This setting configures KBL-U
the OPI /DMI Link Width. For further details see Kabylake PCH EDS. KBL-H
KBL-S
HEDT
OPI Link Voltage KBL-Y
Values: 0.85 Volts, 0.95 Volts - This setting configures the OPI / DMI KBL-U
Link Voltage. For further details see Kabylake PCH EDS. KBL-H
KBL-S
HEDT
Click on Internal PCH Buses in the left tabs menu> DMI Configuration is expanded by default:

# Parameter Platform Settings

Internal PCH Buses - DMI Configuration

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Table 2-11. Intel® FIT - Internal PCH Buses (Sheet 2 of 11)

DMI Lane Reversal KBL-Y No
Values: Yes/No - This setting allows the DMI Lane signals to be KBL-U No
reversed. For further details see Kabylake H / LP Platform Controller Hub KBL-H No
EDS.
KBL-S No
HEDT No
DMI RequesterID Enabled KBL-Y NA
Values: Yes/No - This setting is applicable for platforms that contain KBL-U NA
multiple processor sockets. If multiple processors need to access Serial KBL-H No
Flash then this needs to be set to ‘Yes’. If platform has only one
KBL-S No
processor socket set this to ‘No’.
HEDT No

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Table 2-11. Intel® FIT - Internal PCH Buses (Sheet 3 of 11)

# Parameter Platform Settings
DMI Port Staggering KBL-Y Yes
Values: Yes/No - This setting configures DMI for Port Staggering. For KBL-U Yes
further details see Kabylake H / LP Platform Controller Hub EDS. KBL-H Yes
KBL-S Yes
HEDT Yes
Click on Internal PCH Buses in the left tabs menu> eSPI Configuration is expanded by default:

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Table 2-11. Intel® FIT - Internal PCH Buses (Sheet 4 of 11)

# Parameter Platform Settings
Internal PCH Buses - eSPI Configuration

3
eSPI / EC Boot Enabled KBL-Y Yes
Values: Yes/No KBL-U Yes
KBL-H Yes
KBL-S Yes
HEDT N/A
eSPI / EC Bus Frequency KBL-Y 60MHz
20MHz, 24MHz, 30MHz, 40MHz, 60MHz KBL-U 60MHz
KBL-H 60MHz
KBL-S 60MHz
HEDT N/A
eSPI / EC CRC Check Enabled KBL-Y No
Values: Yes/No KBL-U No
KBL-H No
KBL-S No
HEDT N/A
eSPI / EC Max Outstanding Requests for Master Attached Flash KBL-Y 2
Channel KBL-U 2
Values: 1, 2 KBL-H 2
KBL-S 2
HEDT N/A
eSPI / EC Max Read Request Payload size for Master Attached KBL-Y 64 bytes
Flash Channel KBL-U 64 bytes
Values: 64 bytes, 128 bytes, 256 bytes, 512 bytes, 1024 bytes, KBL-H 64 bytes
2048 bytes, 4096 bytes
KBL-S 64 bytes
HEDT N/A
eSPI / EC Max Read Request Payload size for OOB Channel KBL-Y 64 bytes
Values: 64 bytes, 128 bytes, 256 bytes, 512 bytes, 1024 bytes, KBL-U 64 bytes
2048 bytes, 4096 bytes KBL-H 64 bytes
KBL-S 64 bytes
HEDT N/A
eSPI / EC Max Read Request Payload size for Peripheral Channel KBL-Y 64 bytes
Values: 64 bytes, 128 bytes, 256 bytes, 512 bytes, 1024 bytes, KBL-U 64 bytes
2048 bytes, 4096 bytes KBL-H 64 bytes
KBL-S 64 bytes
HEDT N/A
eSPI / EC Max Virtual Wire Channels KBL-Y 8
Values: 8, 4, 2, 1 KBL-U 8
KBL-H 8
KBL-S 8
HEDT N/A
eSPI / EC Maximum I/O Mode KBL-Y Single, Dual and Quad
Values: Single, Single and Dual, Single and Quad, Single Dual and KBL-U Single, Dual and Quad
Quad KBL-H Single, Dual and Quad
KBL-S Single, Dual and Quad
HEDT N/A
eSPI / EC OOB Channel Enabled KBL-Y Yes
Values: Yes/No KBL-U Yes
KBL-H Yes
KBL-S Yes
HEDT N/A

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Table 2-11. Intel® FIT - Internal PCH Buses (Sheet 5 of 11)

eSPI / EC Peripheral Channel Enabled KBL-Y Yes
Values: Yes/No KBL-U Yes
KBL-H Yes
KBL-S Yes
HEDT N/A
eSPI / EC Slave Device Max Read Request OOB Channel Enable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
KBL-H Disabled
KBL-S Disabled
HEDT N/A
eSPI / EC Slave Device Max Outstanding Requests KBL-Y NA
KBL-U NA
KBL-H 2
KBL-S 2
HEDT N/A

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Table 2-11. Intel® FIT - Internal PCH Buses (Sheet 6 of 11)

# Parameter Platform Settings
eSPI / EC Slave Device Max Read Request Payload size for OOB KBL-Y 64 bytes
Channel KBL-U 64 bytes
KBL-H 64 bytes
KBL-S 64 bytes
HEDT N/A
eSPI / EC Slave Device Max Read Request Payload size for KBL-Y 64 bytes
Peripheral Channel KBL-U 64 bytes
KBL-H 64 bytes
KBL-S 64 bytes
HEDT N/A
eSPI / EC Slave Device OOB Channel Enable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
KBL-H Enabled
KBL-S Enabled
HEDT N/A
eSPI / EC Slave Device Peripheral Channel Enable KBL-Y NA
Values: Enabled/Disabled KBL-U NA
KBL-H Enabled
KBL-S Enabled
HEDT N/A
eSPI / EC Slave Device Virtual Wire Channel Enabled KBL-Y NA
Values: Enabled/Disabled KBL-U NA
KBL-H Enabled
KBL-S Enabled
HEDT N/A
eSPI / EC Slave Device CRC Check Enabled KBL-Y NA
Values: Yes/No KBL-U NA
KBL-H Yes
KBL-S Yes
HEDT N/A
eSPI / EC Slave Device Maximum I/O Mode KBL-Y NA
KBL-U NA
KBL-H Single
KBL-S Single
HEDT N/A
eSPI / EC Slave Device Bus Frequency KBL-Y NA
KBL-U NA
KBL-H 20MHz
KBL-S 20MHz
HEDT N/A
eSPI / EC Slave Device Max Virtual Wire Channels KBL-Y NA
KBL-U NA
KBL-H 8
KBL-S 8
HEDT N/A
eSPI Low Frequency Debug Override KBL-Y No
When enabled this setting will divide eSPI clock frequency by 8. KBL-U No
Note: This setting should only be used for debugging purposes. Leaving KBL-H No
this setting enable will impact eSPI performance. KBL-S No
HEDT No

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Table 2-11. Intel® FIT - Internal PCH Buses (Sheet 7 of 11)

Click on Internal PCH Buses in the left tabs menu> PCH Timer Configuration is expanded by default:

# Parameter Platform Settings

Internal PCH Buses - PCH Timer Configuration

4
APWROK Timing KBL-Y 2 ms
Values: 2ms, 4ms, 8ms, 16ms - This soft strap determines the time KBL-U 2 ms
between the SLP_A# pin de-asserting and the APWROK timer expiration. KBL-H 2 ms
For further details see Kabylake H / LP Platform Controller Hub EDS.
KBL-S 2 ms
HEDT 2 ms
PCH clock output stable to PROCPWRGD high (tPCH45) KBL-Y 100 ms
Values: 100ms, 50ms, 5ms, 1ms - This setting configures the KBL-U 100 ms
minimum timing from XCK_PLL locked to CPUPWRGD high. For further KBL-H 100 ms
details see Kabylake H / LP Platform Controller Hub EDS.
KBL-S 100 ms
HEDT 100 ms
PCIe Power Stable Timer (tPCH33) KBL-Y Disabled
Values: Enabled/Disabled - This setting configures the enables / KBL-U Disabled
disables the t36 timer. When enabled PCH will count 99ms from PWROK KBL-H Disabled
assertion before PLTRST# is de-asserted. Note: The recommended
KBL-S Disabled
setting is "Disabled".
HEDT Disabled
PROCPWRGD and SYS_PWROK high to SUS_STAT# de-assertion KBL-Y 1 ms
(tPCH46) KBL-U 1 ms
Values: 1ms, 2ms, 5ms - This setting configures the minimum timing KBL-H 1 ms
from CPUPWRGD assertion to SUS_STAT#. For further details see
KBL-S 1 ms
Kabylake H / LP Platform Controller Hub EDS.
HEDT 1 ms
Time Stamp Counter Clear on Warm Reset KBL-Y NA
Values: Yes/No - When set to ‘Yes’ causes PCH to clear the Time Stamp KBL-U NA
Counter when a Warm Reset is performed. KBL-H No
KBL-S No
HEDT No

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Table 2-11. Intel® FIT - Internal PCH Buses (Sheet 8 of 11)

Click on Internal PCH Buses in the left tabs menu> SMBus / SMLink Configuration is expanded by default:

# Parameter Platform Settings

Internal PCH Buses - SMBus / SMLink Configuration

5
Intel® SMBus ASD Address Enable KBL-Y No
Values: Yes/No - This setting enables / disables the Intel® SMBus Alert KBL-U No
Sending Device. For details see Kabylake H / LP SPI Programming guide KBL-H No
for further details.
KBL-S No
HEDT No
Intel® SMBus ASD Address - This setting configures the Intel® SMBus KBL-Y 0x00000000
Alert Sending Device Address. For details see Kabylake H / LP SPI KBL-U 0x00000000
Programming guide for further details.
KBL-H 0x00000000
KBL-S 0x00000000
HEDT 0x00000000

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Table 2-11. Intel® FIT - Internal PCH Buses (Sheet 9 of 11)

# Parameter Platform Settings
Intel® SMBus I2C Address Enabled KBL-Y No
Values: Yes/No - This setting enables / disables the Intel® SMBus I2C KBL-U No
Address. Note: This setting is only used for testing purposes. The KBL-H No
recommended setting is "No".
KBL-S No
HEDT No
Intel® SMBus I2C Address - This setting configures the Intel® SMBus KBL-Y 0x00000000
I2C Address. Note: This setting is only used for testing purposes. The KBL-U 0x00000000
recommended setting is "0000000".
KBL-H 0x00000000
KBL-S 0x00000000
HEDT 0x00000000
Intel® SMBus MCTP Address Enabled KBL-Y No
Values: Yes/No - This setting enables / disables the Intel® SMBus KBL-U No
MCTP Address. Note: This setting is only used for testing purposes. The KBL-H No
recommended setting is "No".
KBL-S No
HEDT No
Intel® SMBus MTCP Address - This setting configures the Intel® KBL-Y 0x00000000
SMBus MCTP Address. Note: This setting is only used for testing KBL-U 0x00000000
purposes. The default setting is "0000000".
KBL-H 0x00000000
KBL-S 0x00000000
HEDT 0x00000000
Intel® SMBus Subsystem Vendor & Device ID for ASF - This setting KBL-Y 0x00000000
configures the Intel® SMBus Subsystem Vendor & Device ID for ASF. For KBL-U 0x00000000
details see Kabylake H / LP SPI Programming guide further details.
KBL-H 0x00000000
KBL-S 0x00000000
HEDT 0x00000000
SMBus / SMLink TCO Slave Connection KBL-Y Intel® SMBus
Values: Intel® SMBus, SMLink0 - This setting configures the TCO KBL-U Intel® SMBus
Slave connection to ether the Intel® SMBus or SMLink0. For further KBL-H Intel® SMBus
details see Kabylake H / LP Platform Controller Hub EDS.
KBL-S Intel® SMBus
HEDT Intel® SMBus
SMLink0 Enabled KBL-Y Yes
Values: Yes/No - This setting enables / disables SMLink0 interface. For KBL-U Yes
further details see Kabylake H / LP Platform Controller Hub EDS. Note: If KBL-H Yes
using Intel® NFC this setting must be set to "Yes".
KBL-S Yes
HEDT Yes
SMLink0 Frequency KBL-Y 1 MHz
Values: 100KHz, 400KHz, 1 MHz - This setting determines the KBL-U 1 MHz
frequency at which the SMLink0 will operate. Note: The recommended KBL-H 1 MHz
setting is "1MHz".
KBL-S 1 MHz
HEDT 1Mhz
SMLink1 Enabled KBL-Y Yes
Values: Yes/No - This setting enables / disables SMLink1 interface. For KBL-U Yes
further details see Kabylake H / LP Platform Controller Hub EDS. Note: KBL-H Yes
This setting must be set to "Yes" if using PCH / MCP Thermal reporting.
KBL-S Yes
HEDT Yes
SMLink1 Frequency KBL-Y 100 KHz
Values: 100KHz, 400KHz, 1 MHz - This setting determines the KBL-U 100 KHz
frequency at which the SMLink1 will operate. Note: The recommended KBL-H 100 KHz
setting is "100KHz".
KBL-S 100 KHz
HEDT 100 KHz
SMLink1 GP Target Address - This setting configures SMLink1 GP KBL-Y 0x00000000
Target Address. For further details see Kabylake H / LP Platform KBL-U 0x00000000
Controller Hub EDS.
KBL-H 0x00000000
KBL-S 0x00000000
HEDT 0x00000000

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Table 2-11. Intel® FIT - Internal PCH Buses (Sheet 10 of 11)

SMLink1 GP Target Address Enabled KBL-Y No
Values: Yes/No - This setting enables / disables SMLink1 GP Target KBL-U No
Address interface. For further details see Kabylake H / LP Platform KBL-H No
Controller Hub EDS. Note: This setting must be set to "Yes" if using PCH
KBL-S No
/ MCP Thermal reporting.
HEDT No
SMLink1 I2C Target Address - This setting configures SMLink1 I2C KBL-Y 0x00000000
Target Address. For further details see Kabylake H / LP Platform KBL-U 0x00000000
Controller Hub EDS.
KBL-H 0x00000000
KBL-S 0x00000000
HEDT 0x00000000

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Table 2-11. Intel® FIT - Internal PCH Buses (Sheet 11 of 11)

# Parameter Platform Settings
SMLink1 I2C Target Address Enabled KBL-Y No
Values: Yes/No - This setting configures SMLink1 I2C Target Address. KBL-U No
For further details see Kabylake H / LP Platform Controller Hub EDS. KBL-H No
KBL-S No
HEDT No

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Table 2-12. Intel® FIT - GPIO (Sheet 1 of 3)

Click on GPIO in the left tabs menu> LAN / GPIO Select is expanded by default:

# Parameter Platform Settings

GPIO - LAN / GPIO Select

1
LAN PHY Power Control GPD11 Signal Configuration KBL-Y LANPHYPC
KBL-U LANPHYPC
KBL-H LANPHYPC
KBL-S LANPHYPC
HEDT LANPHYPC
Click on GPIO in the left tabs menu> WLAN / GPIO Select is expanded by default:

# Parameter Platform Settings

GPIO - WLAN / GPIO Select

2
SLP_WLAN# / GPD9 Signal Configuration KBL-Y SLP_WLAN#
KBL-U SLP_WLAN#
KBL-H SLP_WLAN#
KBL-S SLP_WLAN#
HEDT GDP9
Click on GPIO in the left tabs menu> Platform Power / GPIO is expanded by default:

# Parameter Platform Settings

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Table 2-12. Intel® FIT - GPIO (Sheet 2 of 3)

GPIO - Platform Power / GPIO

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Table 2-12. Intel® FIT - GPIO (Sheet 3 of 3)

# Parameter Platform Settings
SLP_A# / GPD6 Signal Configuration KBL-Y SLP_A#
KBL-U SLP_A#
KBL-H SLP_A#
KBL-S SLP_A#
HEDT SLP_A#
SLP_S3# / GPD4 Signal Configuration KBL-Y SLP_S3#
KBL-U SLP_S3#
KBL-H SLP_S3#
KBL-S SLP_S3#
HEDT SLP_S3#
SLP_S4# / GPD5 Signal Configuration KBL-Y SLP_S4#
KBL-U SLP_S4#
KBL-H SLP_S4#
KBL-S SLP_S4#
HEDT SLP_S4#
SLP_S5# / GPD10 Signal Configuration KBL-Y SLP_S5#
KBL-U SLP_S5#
KBL-H SLP_S5#
KBL-S SLP_S5#
HEDT SLP_S5#
Click on GPIO in the left tabs menu> ME Feature Pins is expanded by default:

# Parameter Platform Settings

GPIO - ME Feature Pins

4
NFC Reset GPIO Select
NFC must be enabled in the Networking and Connectivity section to
configure this setting.
NFC IRQ GPIO Select
NFC must be enabled in the Networking and Connectivity section to
configure this setting.
NFC DFU GPIO Select
NFC must be enabled in the Networking and Connectivity section to
configure this setting.

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Table 2-13. Intel® FIT - Power (Sheet 1 of 2)

Click on Power in the left tabs menu> Platform Power is expanded by default:

# Parameter Platform Settings

1 Power - Platform Power

SLP_A# / GPD6 Signal Configuration KBL-Y SLP_A#

Values: SLP_A#, GPD6 - This setting allows the customer to assign the KBL-U SLP_A#
SLP_A# Power Control signal as SLP_A# or as GDP6. For further details see KBL-H SLP_A#
Kabylake H / LP Platform Controller Hub EDS.
KBL-S SLP_A#
HEDT SLP_A#
SLP_S3# / GPD4 Signal Configuration KBL-Y SLP_S3#
Values: SLP_S3#, GPD4 - This setting allows the customer to assign the KBL-U SLP_S3#
SLP_S3# Power Control signal as SLP_S3# or as GDP4. For further details see KBL-H SLP_S3#
Kabylake H / LP Platform Controller Hub EDS.
KBL-S SLP_S3#
HEDT SLP_S3#
SLP_S4# / GPD5 Signal Configuration KBL-Y SLP_S4#
Values: SLP_S4#, GPD5 - This setting allows the customer to assign the KBL-U SLP_S4#
SLP_S4# Power Control signal as SLP_S4# or as GDP5. For further details see KBL-H SLP_S4#
Kabylake H / LP Platform Controller Hub EDS.
KBL-S SLP_S4#
HEDT SLP_S4#
SLP_S5# / GPD10 Signal Configuration KBL-Y SLP_S5#
Values: SLP_S5#, GPD10 - This setting allows the customer to assign the KBL-U SLP_S5#
SLP_S5# Power Control signal as SLP_S5# or as GDP10. For further details see KBL-H SLP_S5#
Kabylake H / LP Platform Controller Hub EDS.
KBL-S SLP_S5#
HEDT SLP_S5#
SLP_S0# Tunnel KBL-Y Enabled
This setting Enables / Disables the tunneling of the SLP_S0# pin over ESPI to KBL-U Enabled
the EC when in ESPI mode. KBL-H Enabled
KBL-S Enabled
HEDT Enabled

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Table 2-13. Intel® FIT - Power (Sheet 2 of 2)

Click on Power in the left tabs menu> Deep Sx is expanded by default:

# Parameter Platform Settings

Power - Deep Sx

2
Deep Sx Enabled KBL-Y Yes
Values: Yes/ No - This setting enables / disables support for Deep Sx KBL-U Yes
operation. For further details see Kabylake H / LP Platform Controller Hub EDS. KBL-H Yes
Note: Support for Deep Sx is board design dependent.
KBL-S Yes
HEDT Yes

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Table 2-14. Intel® FIT - Integrated Sensor Hub (Sheet 1 of 3)

Click on Integrated Sensor Hub in the left tabs menu> Integrated Sensor Hub is expanded by default:

# Parameter Platform Settings

Integrated Sensor Hub

1
Integrated Sensor Hub Supported KBL-Y
Values: Yes/No KBL-U
This setting allows customers to disable ISH on the platform. KBL-H
KBL-S
HEDT
Integrated Sensor Hub Power Up State KBL-Y
Values: Enabled/Disabled KBL-U
Field is enabled for editing if “Integrated Sensor Hub Supported” field KBL-H
above is set to “Yes”. This setting allows customers to determine the KBL-S
power up state for ISH.
HEDT
Integrated Sensor Hub Signing Policy KBL-Y
Values: OEM/Intel, OEM KBL-U
This setting determines ISH signing will be checked against the Intel KBL-H
provisioned hash included in the base image or OEM public key hash KBL-S
provisioned on the platform.
HEDT
Click on Integrated Sensor Hub in the left tabs menu> ISH Image is expanded by default:

# Parameter Platform Settings

Integrated Sensor Hub - ISH Image

2
Length - Total size (in bytes) of the ISH code partition including
reserved space. It is recommended to be at least 256kb.

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Table 2-14. Intel® FIT - Integrated Sensor Hub (Sheet 2 of 3)

Input File KBL-Y Path to your ISH firmware
binary file
KBL-U Path to your ISH firmware
binary file
Path to your ISH firmware
KBL-H
binary file
Path to your ISH firmware
KBL-S binary file

HEDT

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Table 2-14. Intel® FIT - Integrated Sensor Hub (Sheet 3 of 3)

Click on Integrated Sensor Hub in the left tabs menu> ISH Data is expanded by default:

# Parameter Platform Settings

Integrated Sensor Hub - ISH Data

3
PDT Binary File KBL-Y Path for PDT Binary file
KBL-U Path for PDT Binary file
KBL-H Path for PDT Binary file
KBL-S Path for PDT Binary file
HEDT

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Table 2-15. Intel® FIT - Debug (Sheet 1 of 4)

Click on Debug in the left tabs menu> Intel® ME Firmware Debugging Overrides is expanded by default:

# Parameter Platform Settings

1 Debug - Intel® ME Firmware Debugging Overrides

Debug Override Pre-Production Silicon - Allows the OEM to control FW KBL-Y 0x00000000
features to assist with pre-production platform debugging. This control has no KBL-U 0x00000000
effect if used on production silicon.
KBL-H 0x00000000
Bit 0: Disable DRAM_INIT_DONE (default timeout 60 seconds)
KBL-S 0x00000000
Bit 1: Disable Host Reset Timer
HEDT 0x00000000
Bit 2: Disable CPU_RESET_DONE timeout
Bit 3: Reserved
Bit 4: Disable Intel® ME Power Gating
Bit 5: Reserved
Bit 6: Secure Boot debug hook. Used to shorten wait time before ENF shutdown.
Bit 7: Force real FPFs on preproduction (default is to use flash)
Bit 8: Secure Boot debug hook. Used to reduce S3 or FFS optimization tries.
Bit 9: Reserved
Bit 10: Override power package to always enter M3.
Note: Certain options do not work when the descriptor is locked.
Debug Override Production Silicon - Allows the OEM to control FW features to KBL-Y 0x00000000
assist with production platform debugging. KBL-U 0x00000000
Bit 0: Extend DRAM_INIT_DONE timeout to 30 minutes (default timeout 15 KBL-H 0x00000000
seconds)
KBL-S 0x00000000
Bit 1: Disable Host Reset Timer
HEDT 0x00000000
Bit 2: Disable CPU_RESET_DONE timeout
Note: Certain options do not work when the descriptor is locked.
Enable Intel® ME Reset Capture on CLR_RST# KBL-Y No
Values: Yes/No - This setting configures Intel® ME behavior when it resets KBL-U No
during CL_RST#1. Note: The recommended default for this setting is "No". KBL-H No
KBL-S No
HEDT No
Firmware ROM Bypass KBL-Y No
Values: Yes/No - This setting enables / disables firmware ROM bypass. Note: KBL-U No
This setting only has affect when the firmware being used has ROM Bypass code KBL-H No
present.
KBL-S No
HEDT No
Click on Debug in the left tabs menu> Direct Connection Interface Configuration is expanded by default:

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Table 2-15. Intel® FIT - Debug (Sheet 2 of 4)

# Parameter Platform Settings

Debug - Direct Connection Interface Configuration

2
Direct Connect Interface (DCI) Enabled KBL-Y No
Values: Yes/No - This setting enables / disables the DCI interface used for KBL-U No
Intel® Trace Hub debugging. KBL-H No
KBL-S No
HEDT No
Click on Debug in the left tabs menu> Intel® Trace Hub Technology is expanded by default:

# Parameter Platform Settings

Debug - Intel® Trace Hub Technology

3
Intel® Trace Hub Emergency Mode Enabled KBL-Y No
Values: Yes/No - This setting enable / disables Intel® Trace Hub in the firmware KBL-U No
base image. KBL-H No
KBL-S No
HEDT No
Intel® Trace Hub Soft Enabled KBL-Y No
Values: Yes/No - This setting configures the Intel® Trace Hub soft enable. KBL-U No
Note: When enabling this setting you also need to enable Intel® Trace Hub Debug KBL-H No
Messages setting for proper operation.
KBL-S No
HEDT No
Intel® Trace Hub Debug Message Enabled KBL-Y No
Values: Yes/No - This setting enables/disables the Intel® Trace Hub debug KBL-U No
messages. Note: When enabling this setting you also need to enable Intel® Trace KBL-H No
Hub Soft Enable setting for proper operation.
KBL-S No
HEDT No
Unlock Token
This allows the OEM to input an Unlock Token binary file for closed chassis debug.
Click on Debug in the left tabs menu> Intel® IDLM is expanded by default:

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Table 2-15. Intel® FIT - Debug (Sheet 3 of 4)

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Table 2-15. Intel® FIT - Debug (Sheet 4 of 4)

# Parameter Platform Settings
Debug - Intel® IDLM

4
Intel® IDLM
This allows an IDLM binary to be merged into output image built by Intel® FIT.

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Table 2-16. Intel® FIT - CPU Straps (Sheet 1 of 4)

Click on CPU Straps in the left tabs menu> CPU Straps are expanded by default:

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Table 2-16. Intel® FIT - CPU Straps (Sheet 2 of 4)

# Parameter Platform Settings
CPU Straps - CPU Straps

1
Disable Hyperthreading KBL-Y No
Values: Yes/No KBL-U No
This setting controls enabling or disabling of Hyper threading. Note: This strap is KBL-H No
intended for debugging purposes only. See BIOS Spec for more details on KBL-S No
enabling / disabling Hyperthreading.
HEDT No
Number of Active Cores KBL-Y All
Values: All, 1, 2, 3, 4 KBL-U All
This setting controls the number of active processor cores. Note: This strap is KBL-H All
intended for debugging purposes only. See BIOS Spec for more details on KBL-S All
enabling or disabling processor cores.
HEDT All
BIST Initialization KBL-Y No
Values: Yes/No KBL-U No
This setting determines if BIST will be run at platform reset after BIOS requested KBL-H No
actions. KBL-S No
Note: This strap is intended for debugging purposes only. HEDT No
Flex Ratio KBL-Y 0x0
This setting controls the maximum processor non-turbo ratio. Note: This strap is KBL-U 0x0
intended for debugging purposes only. See BIOS Spec for more details on KBL-H 0x0
maximum processor non-turbo ratio configuration.
KBL-S 0x0
HEDT 0x0
Processor Boot Max Frequency KBL-Y Yes
Values: Yes/No KBL-U Yes
This setting determines if the processor will operate at maximum frequency at KBL-H Yes
power-on and boot. Note: This strap is intended for debugging purposes only. KBL-S Yes
HEDT Yes
JTAG Power Disable KBL-Y No
Values: Yes - JTAG Power on C10 and Lower/No - No Power on C10 and KBL-U No
Lower KBL-H No
This setting determines if JTAG power will be maintained on C10 or lower power KBL-S No
states. Note: This strap is intended for debugging purposes only.
HEDT No
SA Power Plane Topology KBL-Y 0x2
This setting determines the SA power plane topology. See Processor EDS for KBL-U 0x2
details. Note: This strap should be left at the recommended default setting. KBL-H 0x2
KBL-S 0x2
HEDT 0x2
SA VR Type KBL-Y SVID
Value: SVID/Fixed VR KBL-U SVID
This setting determines the SA core domain VR type. See Processor EDS for KBL-H SVID
details. KBL-S Fixed VR
HEDT Fixed VR
IA Power Plane Topology KBL-Y 0x0
This setting determines the IA power plane topology. See Processor EDS for KBL-U 0x0
details. Note: This strap should be left at the recommended default setting. KBL-H 0x0
KBL-S 0x0
HEDT 0x0
IA Power Plane VR KBL-Y SVID
Value: SVID/Fixed VR KBL-U SVID
This setting determines the IA core domain VR type. See Processor EDS for KBL-H SVID
details. KBL-S SVID
HEDT SVID

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Table 2-16. Intel® FIT - CPU Straps (Sheet 3 of 4)

Ring Power Plane Topology KBL-Y 0x0
This setting determines the Ring power plane topology. See Processor EDS for KBL-U 0x0
details. Note: This strap should be left at the recommended default setting. KBL-H 0x0
KBL-S 0x0
HEDT 0x0
Ring VR Type KBL-Y SVID
Value: SVID/Fixed VR KBL-U SVID
This setting determines the Ring domain VR type. See Processor EDS for details. KBL-H SVID
KBL-S SVID
HEDT SVID

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Table 2-16. Intel® FIT - CPU Straps (Sheet 4 of 4)

# Parameter Platform Settings
GT_US Power Plane Topology KBL-Y 0x1
This setting determines the GT Unslice power plane topology. See Processor EDS KBL-U 0x3
for details. Note: This strap should be left at the recommended default setting. KBL-H 0x3
FOR KBL-U 23e GT3 Only - if using GT merged power plane the value should be KBL-S 0x3
0x1.
HEDT NA
GT_US VR Type KBL-Y SVID
Value: SVID/Fixed VR KBL-U SVID
This setting determines the GT Unslice domain VR type. See Processor EDS for KBL-H SVID
details. KBL-S SVID
HEDT NA
GT_S Power Plane Topology KBL-Y 0x1
This setting determines the GT slice power plane topology. See Processor EDS for KBL-U 0x1
details. Note: This strap should be left at the recommended default setting. KBL-H 0x1
KBL-S 0x1
HEDT NA
GT_SVR Type KBL-Y SVID
Value: SVID/Fixed VR KBL-U SVID
This setting determines the GT slice domain VR type. See Processor EDS for KBL-H SVID
details. KBL-S SVID
HEDT NA
SVID Presence KBL-Y SVID Present
Value: SVID Present/SVID Not Present KBL-U SVID Present
This setting determines if SVID rails are present on the platform. See Processor KBL-H SVID Present
EDS for details. KBL-S SVID Present
HEDT
Platform IMON Disable KBL-Y 0x0
This strap should be left at the recommended default setting. KBL-U 0x0
KBL-H 0x1
KBL-S 0x1
HEDT NA
eOPIO Power Plane Topology KBL-Y 0x00000000
This setting determines the eOPIO power plane topology. See Processor EDS for KBL-U 0x00000000
details. Note: This strap should be left at the recommended default setting. KBL-H 0x00000005
KBL-S 0x00000005
HEDT NA
eOPIO VR Type KBL-Y Fixed VR
Value: SVID/Fixed VR KBL-U Fixed VR
This setting determines the eOPIO domain VR type. See Processor EDS for details. KBL-H Fixed VR
KBL-S Fixed VR
HEDT NA
EDRAM Power Plane Topology KBL-Y 0x00000000
This setting determines the EDRAM power plane topology. See Processor EDS for KBL-U 0x00000000
details. Note: This strap should be left at the recommended default setting. KBL-H 0x00000004
KBL-S 0x00000004
HEDT NA
EDRAM VR Type KBL-Y Fixed VR
Value: SVID/Fixed VR KBL-U Fixed VR
This setting determines the EDRAM domain VR type. See Processor EDS for KBL-H Fixed VR
details. KBL-S Fixed VR
HEDT NA
SE Key Mode KBL-Y 0
Note: This strap should be left at the recommended default setting. KBL-U 0
KBL-H 0
KBL-S 0
HEDT NA

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Table 2-17. Intel® FIT - Build Image

# Parameter CRB Values

Green Build button Can also select CTRL+B, or Build> Build Image from the menu bar
along the top of the screen

1
Console shows status of
build and path where saved
2

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Programming SPI Flash Devices and Checking Firmware Status

3 Programming SPI Flash Devices

and Checking Firmware Status

Now that the Flash image file has been created, it can be programmed into the SPI
Flash device(s) of the target machine. For platforms that don’t boot, a Flash Chip
Programmer will be required. For platforms that can boot to DOS or Windows*, the
Intel® FPT can be used.

3.1 Flash Burner/Programmer

The specific use of a Flash burner/programmer is beyond the scope of this document.
Here are some general steps that may be followed:
1. Navigate to your Output Directory (as specified in Table 2-2) where your
generated SPI Flash image(s) are saved. It is assumed that this image file is named
outimage.bin.

If two total SPI Flash devices were specified during the build process, then
additional image files will be saved, one for each SPI Flash device. These files are
assumed to be named outimage(1).bin and outimage(2).bin.
2. Utilize a Flash burner/programmer to program the image(s). For multiple SPI Flash
devices, the images are numbered sequentially to correspond to the first and
second SPI Flash device accordingly.

3.1.1 In-Circuit SPI Flash Programming for CRB

Mobile CRBs have the SPI Flash devices soldered down. As a result, to program the SPI
Flash for mobile CRBs, follow these steps:
1. Leave CRB powered on.
2. Connect Flash Programmer (such as DediProg SF600) header to connector J3F3
which is labelled “SPI TPM”. Make sure to line up pin 1 on the header.
3. Program the first image [outimage(1).bin] to the CRB.
4. In Dediprog software, select application memory chip 2 button and load second
image if created.
5. Program the second image [outimage(2).bin] to the CRB if created.
6. Once programming is complete, disconnect the Flash Programmer header. Power
off and unplug CRB. Remove cell coin battery, wait approximately 10 seconds.
Replace cell coin battery, plug CRB back in and power on.

3.2 Flash Programming Tool (Intel® FPT)

Intel® FPT can be used to substitute for a Flash burner/programmer, provided the
system is capable of booting to a DOS or Windows* OS.

Note: Intel® FPT will automatically disable the Intel® ME or EFI prior to flashing the
image to the platform.

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Intel® FPT DOS Version

The DOS versions supported by Intel® FPT are: DOS, Free DOS, and DRMK DOS. Use
the following steps to program the SPI Flash devices,
1. Copy all the files in the “(root)\Tools\System Tools\Flash Programming Tool\DOS”
directory to the root directory of a bootable USB key.
2. Navigate to your Output Directory (as specified in Table 2-2) where your
generated SPI Flash image(s) are saved. It is assumed that this image file is named
outimage.bin. Copy this image file to the root directory of the USB key.
3. Boot the target system to DOS and change to the root directory of the bootable
USB key. At the DOS prompt type:

fpt.exe -i

The system should respond with the number of SPI Flash devices available. For
example:

--- Flash Devices Found ---

W25Q64BV ID:0xEF4017 Size: 8192KB (65536Kb)
W25Q64BV ID:0xEF4017 Size: 8192KB (65536Kb)

Note: If the SPI Flash device does not currently contain a descriptor it may
report only a single device.
4. Program the SPI Flash image to the Flash device(s) by issuing the following
command at the prompt:

fpt.exe -f outimage.bin

If the programming was successful, then the following message will be shown.

FPT Operation Passed

If the programming was NOT successful, then repeat this step to try again. If
programming problems persist, then check the SPI Flash devices and platform
hardware.
5. Execute a platform global reset using Intel® FPT -greset. Next go to Section 3.3 to
check the Intel® ME Firmware status.

3.2.1 Intel® FPT Windows* Version

The Windows* OS versions supported by Intel® FPT are: Windows* PE 64, Windows*
7, Windows* 8/8.1. There are two versions of Intel® FPT for Windows*: a 32-bit
version and a 64-bit version. Most Windows* OS, Windows* 7 (32-bit or 64-bit),
Windows* 8/8.1 (32-bit or 64-bit) can use Windows* version of Intel® FPT. However,
Windows* OS which do not support 32 bit compatible mode (Win PE 64-bit) must use
Intel® FPT Windows* 64-bit version due to compatibility issues.

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Use the following steps to program the SPI Flash devices,

1. Navigate to your Output Directory (as specified in Table 2-2) where your
generated SPI Flash image(s) are saved. It is assumed that this image file is named
outimage.bin. Copy this image file to Intel® FPT directory located at “(root)
\Tools\System Tools\Flash Programming Tool\Windows”.
2. Boot the target system to Windows* and open a Command Prompt window. In this
window, change to the Intel® FPT directory and at the prompt type:

fptw.exe -i

The system should respond with the number of SPI Flash devices available. For
example:

--- Flash Devices Found ---

W25Q64BV ID:0xEF4017 Size: 8192KB (65536Kb)
W25Q64BV ID:0xEF4017 Size: 8192KB (65536Kb)

Note: If the SPI Flash device does not currently contain a descriptor it may
report only a single device.
3. Program the SPI Flash image to the Flash device(s) by issuing the following
command at the prompt:

fptw.exe -f outimage.bin

If the programming was successful, then the following message will be shown.

FPT Operation Passed

If the programming was NOT successful, then repeat this step to try again. If
programming problems persist, then check the SPI Flash devices and platform
hardware.
4. Use fptw.exe -greset to perform a G3 power cycle. Next go to Section 3.3 to check
the Intel® ME Firmware status.

3.3 Checking Intel® ME Firmware Status

Use the following steps to check the platform health and Intel® ME FW status,
1. Copy the file MEInfo.exe in the “(root)\Tools\System Tools\MEInfo\DOS” directory
to the root directory of a bootable USB key.
2. Boot the target system and use F2 or Del to enter the BIOS setup menu. Load
default values for BIOS (on Intel® CRBs press F3 to load default values). Save and
reboot (on Intel® CRBs press F4 and select Yes).
3. Boot the target system to DOS and change to the root directory of the bootable
USB key. At the DOS prompt type:

MEInfo.exe -fwsts

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The system should respond with a message similar to below.

Intel® MEInfo Version: 11.7.0.xxxx

Copyright(C) 2005 - 2014, Intel Corporation. All rights reserved.

FW Status Register1: 0x1E000255

FW Status Register2: 0x60002306
FW Status Register3: 0x00000300
FW Status Register4: 0x00004001
FW Status Register5: 0x00000101
FW Status Register6: 0x03C00FC9

Current State: Normal

ManufacturingMode: Enabled
FlashPartition: Valid
OperationalState: M0 with UMA
InitComplete: Complete
BUPLoadState: Success
ErrorCode: No Error
ModeOfOperation: Normal
Phase: HOSTCOMM Module
ICC: Valid OEM data, ICC programmed
SPI Flash Log: Not Present
ME File System Corrupted: No
FPF and ME Config Status: Not committed

As in the above example if there are NO errors shown, then

• your platform’s health is good
• Intel® ME FW has successfully initialized
• Intel® ME FW is operating normally

Note: This section is only intended to show how to use the MEInfo.exe tool for checking
firmware status. For full usage and capabilities of the MEInfo.exe tool, please see the
System Tools User Guide.

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3.4 Common Bring Up Issues and Troubleshooting

Table
Table 3-1. Common Bring Up Issues and Troubleshooting Table

Problem / Issue Solution / Workaround

System does not boot to By default, the system will boot to EFI Shell. To boot to DOS,
DOS 1. Enter BIOS menu, then go to the ‘Boot’ screen
2. Change ‘Boot Option #1’ to be your USB key (ensure USB key is
formatted to be DOS bootable)
3. Press ‘F4’ to save settings and reboot
Hear 3 beeps when Possible device is disconnected or device not found, check
platform powers on • platform power and MCP fan power connectors
• DIMM memory modules (if applicable for memory down modules
• USB devices (keyboard, mouse, USB key) may be plugged into
inactive USB port
• missing/incorrect jumpers
• missing or poorly socketed MCP
No display on monitor Ensure Corporate FW SKU supports integrated graphics. Try external
graphics card.
USB device not detected USB device may be plugged into inactive USB port
or does not work
System does not boot Incorrect Flash image – possible reasons:
(Post Code 00) • wrong FW selected during Flash image build process
• wrong Flash size selected
Re-build image with correct settings and re-flash using Flash burner.

§§

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Appendix — Flash Configurations

A Appendix — Flash
Configurations

This chapter covers only the basic information needed for clock control parameter
programming. For a more detailed treatment of Mainstream - Mobile Family clocks, see
Intel®Kabylake PCH-H / LP Clocks and Intel® Management Engine — Platform
Compliancy Guide for ME Hardware.

Figure A-1. Configuration “A” — Desktop/Server/Workstation or Mobile

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 Appendix — Flash Configurations

Figure A-2. Configuration “B” — Mobile Only

Figure A-3. Configuration “C” — Desktop/Server/Workstation Only

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Appendix — Flash Configurations

Figure A-4. Configuration “D” — Mobile Only

§§

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Appendix — Intel® ICCS SKU Support Matrix

B Appendix — Intel® ICCS SKU

Support Matrix

The following table describes ICC features supported for specific PCH SKU, clock range
(maximum and minimum), spread mode supported by Kabylake-H/LP SKUs.

Note: Please refer to Kabylake-H/LP Platform Controller Hub (PCH) External Design
Specification (EDS) for details about Kabylake-H/LP Chipset Clock architecture

In below tables,

Min = Clock Div Max (minimum allowed frequency)

Max = Clock Div Min (maximum allowed frequency)

B.1 Intel® ICCS SKU Matrix - KBP-LP

Note: ICC SKU is divided into 2 categories: Basic and Enhanced. Mark "x" indicates
category supported by PCH SKU.

Table B-1. Intel® ICCS SKU Matrix - KBP-LP

PCH SKU Basic Enhanced

Premium Y x

Premium U x

Base U x

Features Standard Clock Configuration Standard Clock Configuration

Supported Adaptive Clock Configuration

Pre-Defined Standard Standard

ICC profile Adaptive
supported

Clock Range
[Min-Max]=100 MHz. BCLK [Min-Max] = 98 - 100 MHz.
Supported

SSC
Down SSC: 0 - 0.5% Down SSC: 0 - 0.5%
Supported

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 Appendix — Intel® ICCS SKU Support Matrix

B.2 Intel® ICCS SKU Matrix - KBP-H

Note: ICC SKU is divided into 3 categories: Basic, Enhanced and Extreme. Mark "x"
indicates category supported by PCH SKU.

Table B-2. Intel® ICCS SKU Matrix - KBP-H

PCH SKU Basic Enhanced Extreme

Q270 X

Q250 X

B250 X

H270 X

Z270 X

X290 X

Standard clock configuration Standard clock configuration Standard clock configuration

adaptive clock configuration adaptive clock configuration
Features
Supported BCLK Overclocking clock
configuration

Standard Standard Standard

Pre-defined Adaptive Adaptive
ICC Profile OverClocking
supported Overclocking Plus
Overclocking Ext.

Clock Range [Min-Max] = 100 MHz BCLK [Min-Max] = 98 - 100 MHz Overclocking Range support:
Supported
BCLK Over clocking [Min-Max] =
99.5 -170 MHz *

BCLK Over clocking Plus [Min-Max]

= 99.5 -341 MHz*

BCLK Overclocking Ext.[Min-Max]

= 98.0 - 341 MHz*

SSC Down SSC: 0 - 0.5% Down SSC : 0 - 0.5% BCLK Over clocking Down SSC :
Supported 0 - 0.5%

BCLK Over clocking Plus Down SSC

: 0 - 0.2%

BCLK Over clocking Ext. Down SSC

: 0 - 0.2%

*BCLK Overclocking ranges mentioned here are ranges supported by The Intel® ME
FW, please make sure to choose range based on platform/HW configuration.

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Appendix — Intel® ICCS SKU Support Matrix

B.3 How to configure CLKREQ# parameters

Below table provides guideline on how to configure CLKREQ# parameters for
SRC[0:15] output clocks depending on dynamic control of the clock via CLKREQ is
required or not.

Configuring CLKREQ# and assigning GPIO depends on how CLKOUT_SRCx

configuration via FIT is done (Enabled or Disabled) and if CLKREQ is required or not.

Note: In below table, Mask Control CLKREQ cannot be configured via FIT Tool. It’s configured
to default once by FW during cold boot and bios can set/clear bits anytime.

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Appendix — Intel® ICCS SKU Support Matrix

Please refer to below table and set FIT parameters accordingly.

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Appendix — Intel® ICCS SKU Support Matrix

Table B-3. How to configure CLKREQ# parameters via FIT Tool

FIT->ICC->Profile Dynamic Control Recommendation Recommendation Mask Overall
of SRCx clock via for How to for How to Control Recommendation
ClockOut Config. ->SRCx CLKREQ configure configure CLKREQ
Parameter required?
FIT->ICC- FIT->ICC-
configured to enabled or >Profile >Profile
disabled?
PowerMgmt PowerMgmt
Config. ->SRCx Config. ->
CLKREQ# CLKREQ SRCx
Mapping Enable

Enabled Yes Configure platform Enabled Leave at If user wants

mapped/routed Default - platform ‘s SRC
GPIO using this 0b clock/s to be
above mentioned dynamically
FIT parameter. managed;
associated CLKREQ
configuration is
required.

Thus either the

default mapped
GPIO/CLKREQ
should be used or a
different user
defined GPIO/clkreq
cab be used and
must be mapped
accordingly.

Note: Make sure the

mapped GPIO/
CLKREQ is
configured in native
CLKREQ mode and
is routed on the
platform.

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Appendix — Intel® ICCS SKU Support Matrix

Table B-3. How to configure CLKREQ# parameters via FIT Tool

FIT->ICC->Profile Dynamic Control Recommendation Recommendation Mask Overall
of SRCx clock via for How to for How to Control Recommendation
ClockOut Config. ->SRCx CLKREQ configure configure CLKREQ
Parameter required?
FIT->ICC- FIT->ICC-
configured to enabled or >Profile >Profile
disabled?
PowerMgmt PowerMgmt
Config. ->SRCx Config. ->
CLKREQ# CLKREQ SRCx
Mapping Enable

Enabled No Keep Default Disabled N/A if user do not want

platform’s SRC
clock/s to be
Recomm
dynamically
endation
managed; no need
is to
to configure
leave at
CLKREQ#
default
associated for the
value,
specific SRC clock.

The default mapped

GPIO/CLKREQ
should remain as
HW default GPIO
mode.

Note that CLKREQ is

not needed but SRC
clock itself is still
needed . In this
case, the GPIO
should remain as
GPIO mode but
there is no
requirement that
SRC clock buffer
itself to be disabled.

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Appendix — Intel® ICCS SKU Support Matrix

Table B-3. How to configure CLKREQ# parameters via FIT Tool

FIT->ICC->Profile Dynamic Control Recommendation Recommendation Mask Overall
of SRCx clock via for How to for How to Control Recommendation
ClockOut Config. ->SRCx CLKREQ configure configure CLKREQ
Parameter required?
FIT->ICC- FIT->ICC-
configured to enabled or >Profile >Profile
disabled?
PowerMgmt PowerMgmt
Config. ->SRCx Config. ->
CLKREQ# CLKREQ SRCx
Mapping Enable

Disabled N/A Keep Default Keep it enabled Set to If SRCx output clock
1b. is disabled, please
keep FIT->ICC-
Since SRCx clock is
>Power
unused/disabled.
Management
Config. -> CLKREQ
SRCx Enable =
Enabled

However no need to
configure an
associated GPIO
mapping.

The default mapped

GPIO should not be
changed. The pin
need not to be
routed on the
platform from the
view of ARC clock
control. It could be
routed for GPIO
associated
functionality.

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Appendix — Boot Guard Configuration

C Appendix — Boot Guard

Configuration

C.1 Boot Guard Profiles

The following table describes the profiles available for Boot Guard Configuration.

Table C-1. Profile Description

Index Profile Name F V M ENF PBE Description

Boot Guard Profile - 0 0 0 00 0 This configuration will invoke Boot Guard during boot with
No_FVME neither Verification nor Measurement. For platforms with all
0
the required Boot Guard components but do not wish to enable
Boot Guard boot block verification protection.

Boot Guard VE 0 1 0 01 1 When Verification is desired but if verification fails the platform
1 will continue to boot with the unverified IBB for a short period,
to allow remediation.

2 Boot Guard VME 0 1 1 01 1 When Verification and Measured are desired and the asset
protection is provided by both TPM protection and a timed
remediation period.

3 Boot Guard VM 0 1 1 00 1 When Verification and Measured are desired and the asset
protection is provided by TPM protection.

4 Boot Guard FVE 1 1 0 11 1 Strict Verification enforcement.

5 Boot Guard FVME 1 1 1 11 1 Strict Verification and Measured enforcement. Prevents

unverified IBB from running.

C.2 Enforcement Policies

Table C-2. Enforcement Policy Description

Error Enforcement
Enforcement Mode Name Description
Policy (ENF)

Infinite time before shutdown – don’t shutdown the

0 Unrestricted Mode platform, let everything run normally.

30 minutes before shutdown – enough time to

1 Remediation Mode remediate the system, e.g. update BIOS or other data
on flash via host tools.

2 Reserved
3 Restricted Mode 0 minutes before shutdown – instant shutdown policy.

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 Appendix — Boot Guard Configuration

C.3 OEM Profile Parameters

Table C-3. Profile Parameters Description

Parameter Description Settings

Force Boot Guard ACM Enabled Force Boot Guard Boot determines if the false - Allow the CPU to jump to the
(F) platform starts the Force Boot Guard Boot legacy reset vector if the Boot Guard
timer. If it successfully starts it indicates Module cannot be successfully loaded.
success. When the Force Boot Guard timer (default)
stops, it starts the Protect Bios Environment
timer, if indicated by the boot policy
true - Force the Boot Guard ACM to
restrictions. Anchor ACM then jumps to the
execute.
Initial Boot Block(IBB) with the Force Boot
Guard Boot time stopped and the Protect BIOS
enable timer running.

Verified Boot Enabled (V) Boot Guard cryptographically verifies the false - Platform does not perform
platform Initial Boot Block (IBB) using the verified boot (default)
boot policy key. On successful verification,
Boot Guard executes Initial Boot Block (IBB)
true - Platform performs verified boot
using the boot policy key. If the verification
fails, Anchor signals or enters Remediation.

Measured Boot Enabled (M) Boot Guard measures the Initial Boot Block false - Platform does not perform
(IBB) into the TPM. Boot Guard perform no measured boot (default)
verification that the IBB is correct or from the
platform manufacturer. The Slylake
true - Platform performs measured
implementation of Boot Guard will support
boot
measurements into TPM or Intel’s Platform
Trust Technology.

Protect Bios Environment Platform manufacturer may want Initial boot false - Take no actions to control the
Enabled (PBE) block to be protected between verification/ environment during execution of the
measurement and execution from attacks on BIOS components (default)
buses and non-CPU components. Boot Guard
accomplishes this by allowing the initial boot
true - Takes actions to control the
block to be verified and executed in LLC in
environment during the execution of
NEM if PBE is enabled.
the BIOS components.

Error Enforcement Policy (ENF) Boot Guard invokes the Enforcement Policy See Section C-2 for details.
when a fatal error is encountered. The action
taken by ENF is determined by the OEM set
persistent policies. Like,
• Allowing platform to continue to boot
• Immediate Shutdown
• Shutdown with Timeout intervals
When the ENF logic is invoked, PTT or TPM
also disconnects.

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Appendix — Intel® Platform Trust Technology

D Appendix — Intel® Platform

Trust Technology

D.1 Intel® Platform Trust Technology

The following table describes the platform configurations supported by Intel® Platform
Trust Technology.

Note: Intel® Platform Trust Technology does not support the full TPM functionality
requirements and should not be used for Intel® vPro™ based platforms.

Table D-1. Intel® Platform Trust Technology Configuration table

Platform Protection> Intel® PTT Configuration

Platform Protection> Intel® PTT Configuration

Platform Protection> Intel® PTT Configuration

Intel® PTT initial power up state

Intel® PTT Supported [FPF]

Configuration Description
Intel® PTT Supported

Intel® PTT Permanently Disabled No No After the End of Manufacturing command, this setting will
Disabled in HW via FPF permanently set into the FPFs contained in the MCP. If disabled,
the specific MCP can never be enabled for Intel® PTT.

Intel® PTT Permanently Disabled No Yes This setting allows Intel® PTT to be set to disabled without
Disabled in base firmware disabling the MCP FPFs. This is the recommended option to
image permanently disable Intel® PTT on a platform.

Intel® PTT Ship State Disabled Yes Yes Intel® PTT initially shipped in disabled mode, can be enabled by
Disabled in base firmware BIOS command.
image

Intel® PTT Enabled Enabled Yes Yes This is the recommended option to enable Intel® PTT on a
platform.

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 Appendix — Settings for RVP CRBs (B)

E Appendix — Settings for RVP CRBs (B)

The following table describes the configuration settings required for RVP CRBs in the Intel® FIT tool.
Please see SPI Programming Guide for additional details.

Table E-1. Kabylake-LP RVP Board Settings

CRB Intel® FIT

Setting Name Offset Value
Board Visible

RVP7 SATA / PCIe GP Select for Port 0 No 0x168 [1:0] 0x0

SATA / PCIe GP Select for Port 2 No 0x168 [5:4] 0x3

USB3 / PCIe Combo Port 0 Strap No 0x16E [1:0] 0x0

USB3 / PCIe Combo Port 1 Strap No 0x16E [3:2] 0x0

GbE PCIe Port Select Yes 0x17C [5:3] PORT4

SATA / PCIe Combo Port 1 Strap Yes 0x17D [3:2] SATA

SATA / PCIe Combo Port 3 Strap Yes 0x180 [1:0] GPIO

USB3 / PCIe Combo Port 0 Yes 0x182 [1:0] USB3

USB3 / PCIe Combo Port 1 Yes 0x182 [3:2] USB3

SATA / PCIe Select for Port 1 No 0x18C [1:0] 0x0

SATA / PCIe Select for Port 2 No 0x18C [5:4] 0x3

PCIe Controller 1 (Port 1-4) Yes 0x19D [4:3] 4x1

PCIe Controller 3 (Port 9-12) Yes 0x1AD [4:3] 1x4

PCIe Controller 3 Lane Reversal Enabled Yes 0x1AD [2] Yes

XHCI Port 4 Ownership Yes 0x1B8 [4] XHCI

XHCI Port 5 Ownership Yes 0x1B8 [5] XHCI

Note: The Intel® FIT default settings for Kabylake-LP are based on the RVP3 CRB.

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 Appendix — Settings for RVP CRBs (B)

Table E-2. Kabylake-H RVP Board Settings

CRB Intel® FIT

Intel® FIT Setting Name Offset Value
Board Visible

SATA / PCIe GP Select for Port 0 No 0x1AC[1:0] 0x3

SATA / PCIe GP Select for Port 1 No 0x1AC [3:2] 0x3

SATA / PCIe GP Select for Port 2 No 0x1AC [5:4] 0x0

SATA / PCIe GP Select for Port 3 No 0x1AC [7:6] 0x0

SATA / PCIe GP Select for Port 4 No 0x1AD[1:0] 0x3

SATA /PCIe Combo Port 2 Yes 0x1C1 [5:4] GPIO

SATA /PCIe Combo Port 3 Yes 0x1C4 [1:0] GPIO

SATA /PCIe Combo Port 4 Yes 0x1C4 [3:2] SATA

SATA /PCIe Combo Port 5 Yes 0x1C4 [5:4] SATA

SATA /PCIe Combo Port 6 Yes 0x1C4 [7:6] GPIO

Polarity Select SATA / PCIe Combo Port 2 Yes 0x1C8 [2] SATA

Polarity Select SATA / PCIe Combo Port 3 Yes 0x1C8 [3] SATA

RVP8 Polarity Select SATA / PCIe Combo Port 4 Yes 0x1C8 [4] PCIe

Polarity Select SATA / PCIe Combo Port 5 Yes 0x1C8 [5] PCIe

Polarity Select SATA / PCIe Combo Port 6 Yes 0x1C8 [6] SATA

SATA / PCIe Select for Port 0 No 0x1D0 [1:0] 0x3

SATA / PCIe Select for Port 1 No 0x1D0 [3:2] 0x3

SATA / PCIe Select for Port 2 No 0x1D0 [5:4] 0x0

SATA / PCIe Select for Port 3 No 0x1D0 [7:6] 0x0

SATA / PCIe GPIO Polarity Port 0 No 0x1D2 [0] 0x1

SATA / PCIe GPIO Polarity Port 1 No 0x1D2 [1] 0x1

SATA / PCIe GPIO Polarity Port 2 No 0x1D2 [2] 0x0

SATA / PCIe GPIO Polarity Port 3 No 0x1D2 [3] 0x0

SATA / PCIe GPIO Polarity Port 4 No 0x1D2 [4] 0x1

PCIe Controller 4 (Port 13-16) Yes 0x1F9 [4:3] 1x2, 2x1

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 Appendix — Settings for RVP CRBs (B)

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 Appendix — Integrated Sensor Hub (ISH) Public Key Settings

F Appendix — Integrated Sensor Hub

(ISH) Public Key Settings
The following table describes the configuration matrix required for ISH configuration for the Intel® FIT
tool. Please see System Tools User Guide within ME kit, Manufacturing Test with Intel® Management
Engine (Intel® ME) Firmware 11 and Intel® Integrated Sensor Solution on Kabylake Mobile, Kabylake
Desktop, and Greenlow Workstation Platforms (CDI # 554868) for additional details.

CLSMNF = Close Manufacturing switch used with Intel® Flash Programming Tool (FPT)

PV = Production Version

For additional information on FPT see System Tools User Guide included with ME kit under system tools
folder.

Table F-1. ISH Public Key Settings

FPF Automatic FPF MEI command after FPF MEI command before
Firmware MCP
Commit CLSMNF (Yes/No) CLSMNF (Yes/No)

Pre-production Production No No - Not a valid combination No - Not a valid combination

Production (PV not set) Pre-production No Yes No

Production (PV not set) Production No Yes No

Pre-production Pre-production No Yes No

Production (PV not set) Production Yes No No

Note: The Intel® FIT allows integration of binary files within Integrated Sensor Hub section under ISH Image
and ISH Data. The Intel® FIT does not generate or create the required files. The table above lists
configuration combinations that can be used. Please see VIP # 105658 - Intel® Integrated Sensor
Solution 3.0 for KBL Program Alpha Corporate Milestone Release Version 3.0.0.1037 update for firmware
information.

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