Kabylake-LP Client Platform

SPI Programming Guide

November 2017

Revision 1.4

Intel Confidential
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2 Intel Confidential
Contents
1 Introduction ............................................................................................................ 11
1.1 Overview ......................................................................................................... 11
1.2 Terminology ..................................................................................................... 12
1.3 Reference Documents ........................................................................................ 12
2 PCH SPI Flash Architecture...................................................................................... 13
2.1 Descriptor Mode ................................................................................................ 13
2.2 Serial Flash Discoverable Parameter (SFDP) .......................................................... 13
2.3 SPI Fast Read ................................................................................................... 13
2.4 Intel® Trusted Platform Module (Intel® TPM) on SPI Bus ........................................ 13
2.5 Boot Flow for Kabylake PCH-LP Family ................................................................. 13
2.6 Flash Regions ................................................................................................... 14
2.6.1 Flash Region Sizes.................................................................................. 14
2.7 Hardware Sequencing ........................................................................................ 14
3 PCH SPI Flash Compatibility Requirement ............................................................... 15
3.1 Kabylake PCH-LP SPI Flash Requirements ............................................................. 15
3.1.1 General Requirements............................................................................. 15
3.1.2 Bios Requirement ................................................................................... 16
3.1.3 Software / Firmware Requirements ........................................................... 16
3.1.4 JEDEC ID (Opcode 9Fh) .......................................................................... 17
3.1.5 Multiple Page Write Usage Model .............................................................. 17
3.1.6 Hardware Sequencing Requirements ......................................................... 17
3.2 Kabylake PCH-LP SPI AC Electrical Compatibility Guidelines..................................... 18
3.3 SPI Flash DC Electrical Compatibility Guidelines ..................................................... 20
4 Descriptor Overview ................................................................................................ 21
4.1 Flash Descriptor Content .................................................................................... 22
4.1.1 Descriptor Signature and Map .................................................................. 23
4.1.1.1 FLVALSIG - Flash Valid Signature
(Flash Descriptor Records) ......................................................... 23
4.1.1.2 FLMAP0 - Flash Map 0 Register
(Flash Descriptor Records) ......................................................... 23
4.1.1.3 FLMAP1 - Flash Map 1 Register
(Flash Descriptor Records) ......................................................... 24
4.1.1.4 FLMAP2—Flash Map 2 Register
(Flash Descriptor Records) ......................................................... 24
4.1.2 Flash Descriptor Component Section ......................................................... 25
4.1.2.1 FLCOMP—Flash Components Register
(Flash Descriptor Records) ......................................................... 25
4.1.2.2 FLILL—Flash Invalid Instructions Register
(Flash Descriptor Records) ......................................................... 27
4.1.2.3 FLILL1—Flash Invalid Instructions Register
(Flash Descriptor Records) ......................................................... 27
4.1.3 Flash Descriptor Region Section ............................................................... 28
4.1.3.1 FLREG0—Flash Region 0 (Flash Descriptor) Register ..........................
(Flash Descriptor Records) ......................................................... 29
4.1.3.2 FLREG1—Flash Region 1 (BIOS) Register
(Flash Descriptor Records) ......................................................... 29
4.1.3.3 FLREG2—Flash Region 2 (Intel® ME) Register
(Flash Descriptor Records) ......................................................... 29
4.1.3.4 FLREG3—Flash Region 3 (GbE) Register
(Flash Descriptor Records) ......................................................... 30

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 4.1.3.5 FLREG4—Flash Region 4 (Platform Data) Register
(Flash Descriptor Records) ......................................................... 30
4.1.3.6 FLREG8—Flash Region 8(Embeded Controller) Register
(Flash Descriptor Records) ......................................................... 30
4.1.4 Flash Descriptor Master Section................................................................ 31
4.1.4.1 FLMSTR1—Flash Master 1 (Host CPU/ BIOS)................................. 31
4.1.4.2 FLMSTR2—Flash Master 2 (Intel® ME) ......................................... 31
4.1.4.3 FLMSTR3—Flash Master 3 (GbE) ................................................. 31
4.1.4.4 FLMSTR4—Flash Master 4 (Reserved) .......................................... 32
4.1.4.5 FLMSTR5—Flash Master 5 (EC) ................................................... 32
4.1.5 PCH / CPU Softstraps .............................................................................. 32
4.1.6 Descriptor Upper Map Section .................................................................. 32
4.1.6.1 FLUMAP1—Flash Upper Map 1
(Flash Descriptor Records) ......................................................... 32
4.1.7 Intel® ME Vendor Specific Component Capabilities Table ............................. 32
4.1.7.1 JID0—JEDEC-ID 0 Register
(Flash Descriptor Records) ......................................................... 33
4.1.7.2 VSCC0—Vendor Specific Component Capabilities 0
(Flash Descriptor Records) ......................................................... 33
4.1.7.3 JIDn—JEDEC-ID Register n
(Flash Descriptor Records) ......................................................... 34
4.1.7.4 VSCCn—Vendor Specific Component Capabilities n
(Flash Descriptor Records) ......................................................... 34
4.2 OEM Section ..................................................................................................... 34
4.3 Region Access Control........................................................................................ 34
4.3.1 Intel Recommended Permissions for Region Access ..................................... 35
4.3.2 Overriding Region Access ........................................................................ 35
4.4 Intel® ME Vendor-Specific Component Capabilities (Intel® ME VSCC) Table............... 36
4.4.1 How to Set a VSCC Entry in Intel® ME VSCC Table for Kabylake PCH-LP Platforms
36
4.4.2 Intel® ME VSCC Table Settings for Kabylake PCH-LP Family Systems ............ 38
5 Serial Flash Discoverable Parameter (SFDP) Overview ............................................ 39
5.1 Introduction ..................................................................................................... 39
5.2 Discoverable Parameter Opcode and Flash Cycle.................................................... 39
5.3 Parameter Table Supported on PCH ..................................................................... 39
5.4 Detailed JEDEC Specification ............................................................................... 40
6 Configuring BIOS/GbE for SPI Flash Access............................................................. 41
6.1 Unlocking SPI Flash Device Protection for Kabylake PCH-LP Platform ........................ 41
6.2 Locking SPI Flash via Status Register ................................................................... 42
6.3 SPI Protected Range Register Recommendations ................................................... 42
6.4 Recommendations for Flash Configuration Lockdown and Vendor Component Lock Bits42
6.4.1 Flash Configuration Lockdown .................................................................. 42
6.4.2 Vendor Component Lock ......................................................................... 43
6.5 Host Vendor Specific Component Control Registers (VSCC) ..................................... 43
6.6 Host VSCC Register Settings ............................................................................... 47
7 Intel® ME Disable for Debug/Flash Burning Purposes.............................................. 48
7.1 Intel® ME Disable.............................................................................................. 48
7.1.1 Erasing/Programming Intel® ME Region .................................................... 48
8 Recommendations for SPI Flash Programming in Manufacturing Environments ....... 49
9 Flash Descriptor PCH / CPU Configuration Section................................................... 50
9.1 PCH Descriptor Record 0 (Flash Descriptor Records)............................................... 50
9.2 PCH Descriptor Record 1 (Flash Descriptor Records)............................................... 51
9.3 PCH Descriptor Record 2 (Flash Descriptor Records)............................................... 51

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 9.4 PCH Descriptor Record 3 (Flash Descriptor Records)............................................... 51
9.5 PCH Descriptor Record 4 (Flash Descriptor Records)............................................... 51
9.6 PCH Descriptor Record 5 (Flash Descriptor Records)............................................... 52
9.7 PCH Descriptor Record 6 (Flash Descriptor Records)............................................... 52
9.8 PCH Descriptor Record 7 (Flash Descriptor Records)............................................... 52
9.9 PCH Descriptor Record 8 (Flash Descriptor Records)............................................... 53
9.10 PCH Descriptor Record 9 (Flash Descriptor Records)............................................... 53
9.11 PCH Descriptor Record 10 (Flash Descriptor Records) ............................................. 53
9.12 PCH Descriptor Record 11 (Flash Descriptor Records) ............................................. 54
9.13 PCH Descriptor Record 12 (Flash Descriptor Records) ............................................. 54
9.14 PCH Descriptor Record 13 (Flash Descriptor Records) ............................................. 54
9.15 PCH Descriptor Record 14 (Flash Descriptor Records) ............................................. 55
9.16 PCH Descriptor Record 15 (Flash Descriptor Records) ............................................. 55
9.17 PCH Descriptor Record 16 (Flash Descriptor Records) ............................................. 55
9.18 PCH Descriptor Record 17 (Flash Descriptor Records) ............................................. 55
9.19 PCH Descriptor Record 18 (Flash Descriptor Records) ............................................. 56
9.20 PCH Descriptor Record 19 (Flash Descriptor Records) ............................................. 56
9.21 PCH Descriptor Record 20 (Flash Descriptor Records) ............................................. 56
9.22 PCH Descriptor Record 21 (Flash Descriptor Records) ............................................. 56
9.23 PCH Descriptor Record 22 (Flash Descriptor Records) ............................................. 56
9.24 PCH Descriptor Record 23 (Flash Descriptor Records) ............................................. 57
9.25 PCH Descriptor Record 24 (Flash Descriptor Records) ............................................. 57
9.26 PCH Descriptor Record 25 (Flash Descriptor Records) ............................................. 57
9.27 PCH Descriptor Record 26 (Flash Descriptor Records) ............................................. 58
9.28 PCH Descriptor Record 27 (Flash Descriptor Records) ............................................. 58
9.29 PCH Descriptor Record 28 (Flash Descriptor Records) ............................................. 59
9.30 PCH Descriptor Record 29 (Flash Descriptor Records) ............................................. 59
9.31 PCH Descriptor Record 30 (Flash Descriptor Records) ............................................. 59
9.32 PCH Descriptor Record 31 (Flash Descriptor Records) ............................................. 59
9.33 PCH Descriptor Record 32 (Flash Descriptor Records) ............................................. 60
9.34 PCH Descriptor Record 33 (Flash Descriptor Records) ............................................. 60
9.35 PCH Descriptor Record 34 (Flash Descriptor Records) ............................................. 60
9.36 PCH Descriptor Record 35 (Flash Descriptor Records) ............................................. 60
9.37 PCH Descriptor Record 36 (Flash Descriptor Records) ............................................. 60
9.38 PCH Descriptor Record 37 (Flash Descriptor Records) ............................................. 61
9.39 PCH Descriptor Record 38 (Flash Descriptor Records) ............................................. 61
9.40 PCH Descriptor Record 39 (Flash Descriptor Records) ............................................. 61
9.41 PCH Descriptor Record 40 (Flash Descriptor Records) ............................................. 61
9.42 PCH Descriptor Record 41 (Flash Descriptor Records) ............................................. 62
9.43 PCH Descriptor Record 42 (Flash Descriptor Records) ............................................. 62
9.44 PCH Descriptor Record 43 (Flash Descriptor Records) ............................................. 62
9.45 PCH Descriptor Record 44 (Flash Descriptor Records) ............................................. 62
9.46 PCH Descriptor Record 45 (Flash Descriptor Records) ............................................. 63
9.47 PCH Descriptor Record 46 (Flash Descriptor Records) ............................................. 63
9.48 PCH Descriptor Record 47 (Flash Descriptor Records) ............................................. 63
9.49 PCH Descriptor Record 48 (Flash Descriptor Records) ............................................. 63
9.50 PCH Descriptor Record 49 (Flash Descriptor Records) ............................................. 63
9.51 PCH Descriptor Record 50 (Flash Descriptor Records) ............................................. 64
9.52 PCH Descriptor Record 51 (Flash Descriptor Records) ............................................. 64
9.53 PCH Descriptor Record 52 (Flash Descriptor Records) ............................................. 65
9.54 PCH Descriptor Record 53 (Flash Descriptor Records) ............................................. 65
9.55 PCH Descriptor Record 54 (Flash Descriptor Records) ............................................. 66
9.56 PCH Descriptor Record 55 (Flash Descriptor Records) ............................................. 67
9.57 PCH Descriptor Record 56 (Flash Descriptor Records) ............................................. 67
9.58 PCH Descriptor Record 57 (Flash Descriptor Records) ............................................. 68

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 9.59 PCH Descriptor Record 58 (Flash Descriptor Records) ............................................. 69
9.60 PCH Descriptor Record 59 (Flash Descriptor Records) ............................................. 69
9.61 PCH Descriptor Record 60 (Flash Descriptor Records) ............................................. 70
9.62 PCH Descriptor Record 61 (Flash Descriptor Records) ............................................. 70
9.63 PCH Descriptor Record 62 (Flash Descriptor Records) ............................................. 70
9.64 PCH Descriptor Record 63 (Flash Descriptor Records) ............................................. 71
9.65 PCH Descriptor Record 64 (Flash Descriptor Records) ............................................. 71
9.66 PCH Descriptor Record 65 (Flash Descriptor Records) ............................................. 72
9.67 PCH Descriptor Record 66 (Flash Descriptor Records) ............................................. 73
9.68 PCH Descriptor Record 67 (Flash Descriptor Records) ............................................. 73
9.69 PCH Descriptor Record 68 (Flash Descriptor Records) ............................................. 73
9.70 PCH Descriptor Record 69 (Flash Descriptor Records) ............................................. 74
9.71 PCH Descriptor Record 70 (Flash Descriptor Records) ............................................. 74
9.72 PCH Descriptor Record 71 (Flash Descriptor Records) ............................................. 74
9.73 PCH Descriptor Record 72 (Flash Descriptor Records) ............................................. 75
9.74 PCH Descriptor Record 73 (Flash Descriptor Records) ............................................. 76
9.75 PCH Descriptor Record 74 (Flash Descriptor Records) ............................................. 76
9.76 PCH Descriptor Record 75 (Flash Descriptor Records) ............................................. 76
9.77 PCH Descriptor Record 76 (Flash Descriptor Records) ............................................. 76
9.78 PCH Descriptor Record 77 (Flash Descriptor Records) ............................................. 77
9.79 PCH Descriptor Record 78 (Flash Descriptor Records) ............................................. 78
9.80 PCH Descriptor Record 79 (Flash Descriptor Records) ............................................. 78
9.81 PCH Descriptor Record 80 (Flash Descriptor Records) ............................................. 79
9.82 PCH Descriptor Record 81 (Flash Descriptor Records) ............................................. 79
9.83 PCH Descriptor Record 82 (Flash Descriptor Records) ............................................. 79
9.84 PCH Descriptor Record 83 (Flash Descriptor Records) ............................................. 79
9.85 PCH Descriptor Record 84 (Flash Descriptor Records) ............................................. 80
9.86 PCH Descriptor Record 85 (Flash Descriptor Records) ............................................. 80
9.87 PCH Descriptor Record 86 (Flash Descriptor Records) ............................................. 80
9.88 PCH Descriptor Record 87 (Flash Descriptor Records) ............................................. 80
9.89 PCH Descriptor Record 88 (Flash Descriptor Records) ............................................. 81
9.90 PCH Descriptor Record 89 (Flash Descriptor Records) ............................................. 81
9.91 PCH Descriptor Record 90 (Flash Descriptor Records) ............................................. 81
9.92 PCH Descriptor Record 91 (Flash Descriptor Records) ............................................. 82
9.93 PCH Descriptor Record 92 (Flash Descriptor Records) ............................................. 82
9.94 PCH Descriptor Record 93 (Flash Descriptor Records) ............................................. 82
9.95 PCH Descriptor Record 94 (Flash Descriptor Records) ............................................. 82
9.96 PCH Descriptor Record 95 (Flash Descriptor Records) ............................................. 82
9.97 PCH Descriptor Record 96 (Flash Descriptor Records) ............................................. 83
9.98 PCH Descriptor Record 97 (Flash Descriptor Records) ............................................. 83
9.99 PCH Descriptor Record 98 (Flash Descriptor Records) ............................................. 83
9.100 PCH Descriptor Record 99 (Flash Descriptor Records) ............................................. 84
9.101 PCH Descriptor Record 100 (Flash Descriptor Records) ........................................... 84
9.102 PCH Descriptor Record 101 (Flash Descriptor Records) ........................................... 85
9.103 PCH Descriptor Record 102 (Flash Descriptor Records) ........................................... 85
9.104 PCH Descriptor Record 103 (Flash Descriptor Records) ........................................... 85
9.105 PCH Descriptor Record 104 (Flash Descriptor Records) ........................................... 85
9.106 PCH Descriptor Record 105 (Flash Descriptor Records) ........................................... 85
9.107 PCH Descriptor Record 106 (Flash Descriptor Records) ........................................... 86
9.108 PCH Descriptor Record 107 (Flash Descriptor Records) ........................................... 86
9.109 PCH Descriptor Record 108 (Flash Descriptor Records) ........................................... 87
9.110 PCH Descriptor Record 109 (Flash Descriptor Records) ........................................... 87
9.111 PCH Descriptor Record 110 (Flash Descriptor Records) ........................................... 88
9.112 PCH Descriptor Record 111 (Flash Descriptor Records) ........................................... 88
9.113 PCH Descriptor Record 112 (Flash Descriptor Records) ........................................... 88

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 9.114 PCH Descriptor Record 113 (Flash Descriptor Records) ........................................... 88
9.115 PCH Descriptor Record 114 (Flash Descriptor Records) ........................................... 89
9.116 PCH Descriptor Record 115 (Flash Descriptor Records) ........................................... 90
9.117 PCH Descriptor Record 116 (Flash Descriptor Records) ........................................... 90
9.118 PCH Descriptor Record 117 (Flash Descriptor Records) ........................................... 90
9.119 PCH Descriptor Record 118 (Flash Descriptor Records) ........................................... 91
9.120 PCH Descriptor Record 119 (Flash Descriptor Records) ........................................... 91
9.121 PCH Descriptor Record 120 (Flash Descriptor Records) ........................................... 92
9.122 PCH Descriptor Record 121 (Flash Descriptor Records) ........................................... 92
9.123 PCH Descriptor Record 122 (Flash Descriptor Records) ........................................... 93
9.124 PCH Descriptor Record 123 (Flash Descriptor Records) ........................................... 93
9.125 PCH Descriptor Record 124 (Flash Descriptor Records) ........................................... 93
9.126 PCH Descriptor Record 125 (Flash Descriptor Records) ........................................... 94
9.127 PCH Descriptor Record 126 (Flash Descriptor Records) ........................................... 94
9.128 PCH Descriptor Record 127 (Flash Descriptor Records) ........................................... 94
9.129 PCH Descriptor Record 128 (Flash Descriptor Records) ........................................... 95
9.130 PCH Descriptor Record 129 (Flash Descriptor Records) ........................................... 95
9.131 PCH Descriptor Record 130 (Flash Descriptor Records) ........................................... 95
9.132 PCH Descriptor Record 131 (Flash Descriptor Records) ........................................... 95
9.133 PCH Descriptor Record 132 (Flash Descriptor Records) ........................................... 95
9.134 PCH Descriptor Record 133 (Flash Descriptor Records) ........................................... 96
9.135 PCH Descriptor Record 134 (Flash Descriptor Records) ........................................... 96
9.136 PCH Descriptor Record 135 (Flash Descriptor Records) ........................................... 96
9.137 PCH Descriptor Record 136 (Flash Descriptor Records) ........................................... 96
9.138 PCH Descriptor Record 137 (Flash Descriptor Records) ........................................... 96
9.139 PCH Descriptor Record 138 (Flash Descriptor Records) ........................................... 97
9.140 PCH Descriptor Record 139 (Flash Descriptor Records) ........................................... 97
9.141 PCH Descriptor Record 140 (Flash Descriptor Records) ........................................... 97
9.142 PCH Descriptor Record 141 (Flash Descriptor Records) ........................................... 97
9.143 PCH Descriptor Record 142 (Flash Descriptor Records) ........................................... 97
9.144 PCH Descriptor Record 143 (Flash Descriptor Records) ........................................... 98
9.145 PCH Descriptor Record 144 (Flash Descriptor Records) ........................................... 98
9.146 PCH Descriptor Record 145 (Flash Descriptor Records) ........................................... 98
9.147 PCH Descriptor Record 146 (Flash Descriptor Records) ........................................... 98
9.148 PCH Descriptor Record 147 (Flash Descriptor Records) ........................................... 98
9.149 PCH Descriptor Record 148 (Flash Descriptor Records) ........................................... 99
9.150 PCH Descriptor Record 149 (Flash Descriptor Records) ........................................... 99
9.151 PCH Descriptor Record 150 (Flash Descriptor Records) ........................................... 99
9.152 PCH Descriptor Record 151 (Flash Descriptor Records) ........................................... 99
9.153 PCH Descriptor Record 152 (Flash Descriptor Records) ........................................... 99
9.154 PCH Descriptor Record 153 (Flash Descriptor Records) ......................................... 100
9.155 PCH Descriptor Record 154 (Flash Descriptor Records) ......................................... 100
9.156 PCH Descriptor Record 155 (Flash Descriptor Records) ......................................... 100
9.157 PCH Descriptor Record 156 (Flash Descriptor Records) ......................................... 100
9.158 PCH Descriptor Record 157 (Flash Descriptor Records) ......................................... 101
9.159 PCH Descriptor Record 158 (Flash Descriptor Records) ......................................... 101
9.160 PCH Descriptor Record 159 (Flash Descriptor Records) ......................................... 102
9.161 PCH Descriptor Record 160 (Flash Descriptor Records) ......................................... 102
9.162 PCH Descriptor Record 161 (Flash Descriptor Records) ......................................... 103
9.163 PCH Descriptor Record 162 (Flash Descriptor Records) ......................................... 103
9.164 PCH Descriptor Record 163 (Flash Descriptor Records) ......................................... 103
9.165 PCH Descriptor Record 164 (Flash Descriptor Records) ......................................... 104
9.166 PCH Descriptor Record 165 (Flash Descriptor Records) ......................................... 104
9.167 PCH Descriptor Record 166 (Flash Descriptor Records) ......................................... 104
9.168 PCH Descriptor Record 167 (Flash Descriptor Records) ......................................... 105

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 9.169 PCH Descriptor Record 168 (Flash Descriptor Records) ......................................... 105
9.170 PCH Descriptor Record 169 (Flash Descriptor Records) ......................................... 106
9.171 PCH Descriptor Record 170 (Flash Descriptor Records) ......................................... 107
9.172 PCH Descriptor Record 171 (Flash Descriptor Records) ......................................... 108
9.173 PCH Descriptor Record 172 (Flash Descriptor Records) ......................................... 109
9.174 PCH Descriptor Record 173 (Flash Descriptor Records) ......................................... 109
9.175 PCH Descriptor Record 174 (Flash Descriptor Records) ......................................... 110
9.176 PCH Descriptor Record 175 (Flash Descriptor Records) ......................................... 110
9.177 PCH Descriptor Record 176 (Flash Descriptor Records) ......................................... 111
9.178 PCH Descriptor Record 177 (Flash Descriptor Records) ......................................... 111
9.179 PCH Descriptor Record 178 (Flash Descriptor Records) ......................................... 112
9.180 PCH Descriptor Record 179 (Flash Descriptor Records) ......................................... 112
9.181 Kabylake-R CPU Descriptor Record 0 (Flash Descriptor Records) ............................ 113
9.182 Kabylake-R CPU Descriptor Record 1 (Flash Descriptor Records) ............................ 114
9.183 Kabylake-R CPU Descriptor Record 2 (Flash Descriptor Records) ............................ 116
10 Configuration Dependencies .................................................................................. 118
10.1 Descriptor Configuration Setting Enabling Dependencies ....................................... 118
10.1.1 High Speed IO (HSIO) Port Enabling ....................................................... 118
10.1.1.1 Configuring PCIe on HSIO ........................................................ 121
10.1.1.2 Configure Intel® RST on PCIe ................................................... 122
10.1.2 Intel® Integrated LAN Controller Enabling................................................ 124
10.1.3 Intel® Wireless LAN Controller Enabling................................................... 124
10.1.4 Deep Sx Enabling Dependencies ............................................................. 125
10.1.5 Intel® SMBus Enabling.......................................................................... 125
10.1.6 SMLink0 Enabling Dependencies ............................................................. 126
10.1.7 SMLink1 Enabling Dependencies ............................................................. 126
10.1.8 TPM over SPI Enabling Dependencies ...................................................... 127
10.1.9 mSATA/M.2 / SATA Express Enabling ...................................................... 127
10.1.9.1 SATA0 / PCIe7 mSATA /M.2 / SATA Express Enabling HSIO .......... 127
10.1.9.2 SATA1A / PCIe8 mSATA /M.2 / SATA Express Enabling ................ 128
10.1.9.3 SATA1B / PCIe11 mSATA /M.2 / SATA Express Enabling............... 128
10.1.9.4 SATA2 / PCIe12 mSATA /M.2 / SATA Express Enabling................. 129
A FAQ and Troubleshooting ...................................................................................... 130

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Figures
3-1 SPI Timing .............................................................................................................. 21
3-2 PCH Test Load ......................................................................................................... 22
4-1 Flash Descriptor (Kabylake PCH-LP)............................................................................ 23
5-1 SFDP Read Instruction Sequence................................................................................ 41

Tables
1-1 Terminology ............................................................................................................ 14
1-2 Reference Documents ............................................................................................... 14
3-1 SPI Timings (17 MHz) ............................................................................................... 20
3-2 SPI Timings (30 MHz) ............................................................................................... 20
3-3 SPI Timings (48 MHz) ............................................................................................... 21
4-1 Region Access Control Table Options........................................................................... 36
4-2 Recommended Read/Write Permissions ....................................................................... 37
4-3 Recommended Read/Write Settings for Platforms ......................................................... 37
4-4 Jidn - JEDEC ID Portion of Intel® ME VSCC Table.......................................................... 38
4-5 Vsccn – Vendor-Specific Component Capabilities Portion of the Kabylake PCH-LP Platforms 38
6-1 VSCC0 - Vendor-Specific Component Capabilities Register for SPI Component 0 ............... 45
6-2 VSCC1 - Vendor Specific Component Capabilities Register for SPI Component 1 ............... 47
6-3 Description of How WSR and WEWS is Used................................................................. 48
10-1HSIO Lane Muxing Selection .................................................................................... 121

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Revision History

Document Revision
Description Revision Date
Number Number

1.2 • Initial KBL-R release January 2017

1.3 • Corrected Table 4-3 BIOS Read Permissions February 2017
1.4 • Added note to GBE PCIe* Port Select about HSIO register access November 2017

§§

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Introduction

1 Introduction

1.1 Overview
This manual is intended for OEMs and software vendors to clarify various aspects of
programming the SPI flash on PCH family based platforms. The current scope of this
document is for Intel® microarchitecture code name Kabylake-R-R PCH-LP only.

Chapter 2, “PCH SPI Flash Architecture”

• Overview of SPI flash, Descriptor, Flash Layout, compatible SPI flash.

Chapter 3, “PCH SPI Flash Compatibility Requirement”

• Overview of compatibility requirements for Kabylake-R PCH-LP products.
Chapter 4, “Descriptor Overview”
• Overview of the descriptor and Descriptor record definition

Chapter 5, “Serial Flash Discoverable Parameter (SFDP) Overview”

• Overview of the SFDP definition.

Chapter 6, “Configuring BIOS/GbE for SPI Flash Access”

• Describes how to configure BIOS/GbE for SPI flash access.

Chapter 7, “Intel® ME Disable for Debug/Flash Burning Purposes”

• Methods of disabling Intel Management Engine for debug purposes.

Chapter 8, “Recommendations for SPI Flash Programming in Manufacturing

Environments”
• Recommendations for manufacturing environments.

Chapter 9, “Flash Descriptor PCH / CPU Configuration Section”

• Flash Descriptor PCH / CPU Soft Strap Section.

Chapter 10, “Configuration Dependencies”

• Descriptor configuration dependencies for enabling Kabylake-R Hardware I/O, Bus
and GPIO components.

Appendix A, “FAQ and Troubleshooting”

• Frequently asked questions and Troubleshooting tips.

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Introduction

1.2 Terminology
Table 1-1. Terminology
Term Description

BIOS Basic Input-Output System

CRB Customer Reference Board

Intel® FPT Intel® Flash Programming Tool - programs the SPI flash
®
Intel FIT Intel® Flash Image Tool – creates a flash image from separate binaries

FW Firmware

FWH Firmware Hub – LPC based flash where BIOS may reside

FPF Field Programmable Fuse

GbE Intel Integrated 1000/100/10

HDCP High-bandwidth Digital Content Protection

Intel® AMT Intel® Active Management Technology

Kabylake-R PCH-LP Kabylake-R Platform Integrated I/O

Intel®Management Engine Intel firmware that adds Intel® Active Management Technology, Castle Peak,
Firmware (Intel® ME FW) Sentry Peak, etc.

Intel PCH Intel Platform Controller Hub

Intel PCHn family All PCHn derivatives including PCHn (desktop) and PCHnM (mobile)

LPC Low Pin Count Bus- bus on where legacy devices such a FWH reside

LVSCC Lower Vendor Specific Component Capabilities

PCH Platform Controller Hub

PCH–LP Platform Controller Hub – Low Power

SFDP Serial Flash Discoverable Parameter

SPI Serial Peripheral Interface – refers to serial flash memory in this document

UVSCC Upper Vendor Specific Component Capabilities

VSCC Vendor Specific Component Capabilities

1.3 Reference Documents

Table 1-2. Reference Documents
Document Document # / Location

Kabylake-R PCH-LP External Design Contact your Intel field representative.

Specification (EDS)
Intel Flash Image Tool (FIT) \System Tools\Flash Image Tool of latest Intel® ME kit from VIP.
The Kit MUST match the platform you intend to use the flash tools
for.
Intel Flash Programming Tool (FPT) \System Tools\Flash Programming Tool of latest Intel® ME from
VIP. The Kit MUST match the platform you intend to use the flash
tools for.
FW Bring Up Guide Root directory of latest Intel® Management Engine kit from VIP.
The Kit MUST match the platform you intend to use the flash tools
for.

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Intel Confidential 12
PCH SPI Flash Architecture

2 PCH SPI Flash Architecture

2.1 Descriptor Mode

The Kabylake Platform supports up to two SPI flash devices. The flash connected to
Chip Select 0 must contain a valid Descriptor as defined in Section 4. The contents of
the Descriptor provide platform configuration and enable the PCH to securely manage
storage among multiple users/purposes.

SPI flash must be connected directly to the PCH SPI bus.

Note: Kabylake only supports Descriptor mode.

See SPI Supported Feature Overview of the latest Intel Platform Controller Hub
Family External Design Specification (EDS) for Kabylake PCH-LP Family for more
detailed information.

2.2 Serial Flash Discoverable Parameter (SFDP)

Serial flash with SFDP have their supported capabilities and commands stored inside
the serial flash devices. The controller will discover the attributes needed to operate.

Kabylake PCH-LP requires SPI flash devices support JEDEC standard JESD216 SDFDP
(Serial Flash Discoverable Parameters. Revision A (JESD216A) or later is strongly
recommended but not mandatory. SFDP provides a consistent method of describing the
functional and feature capabilities of SPI devices in a standard set of internal parameter
tables. These parameter tables can be interrogated by PCH to enable adjustment
needed to accommodate divergent feature from multiple vendors.

Please refer to Chapter 5, “Serial Flash Discoverable Parameter (SFDP) Overview” for
more information.

2.3 SPI Fast Read

Note: See SPI for Flash section of the latest Intel Platform Controller Hub Family External
Design Specification (EDS) for Kabylake PCH-LP Family for more detailed
information.50-MHz support requires SPI component that meet 66-MHz timing.

2.4 Intel® Trusted Platform Module (Intel® TPM) on

SPI Bus
Kabylake PCH-LP Family supports Intel TPM on the SPI bus.

See Serial Peripheral Interface (SPI) section of the latest Intel Platform Controller
Hub Family External Design Specification (EDS) for Kabylake PCH-LP Family for more
detailed information.

2.5 Boot Flow for Kabylake PCH-LP Family

See Boot BIOS strap in the Functional Straps of the latest Intel Platform Controller
Hub Family External Design Specification (EDS) for Kabylake PCH-LP Family for more
detailed information.

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PCH SPI Flash Architecture

See Chapter 4, “Descriptor Overview” for more detailed information.

13H287

2.6 Flash Regions

The controller can divide the SPI flash into separate regions below.
Region Content

0 Descriptor

1 BIOS

2 ME – Intel® Management Engine Firmware (Intel® ME FW)

3 GbE – Location for Integrated LAN firmware and MAC address

4 PDR – Platform Data Region (Optional)1

8 Embedded Controller (EC)

Notes:
1. The PDR region is optional and is not applicable for Kabylake PCH-LP or not required for proper platform
operation.

See SPI Flash Regions section of the latest Intel Platform Controller Hub Family
External Design Specification (EDS) for Kabylake PCH-LP Family for more detailed
information.

2.6.1 Flash Region Sizes

SPI flash space requirements differ by platform and configuration. Please refer to
documentation specific to your platform for BIOS and ME Region flash size estimates.

See SPI Flash Regions section of the latest Intel Platform Controller Hub Family
External Design Specification (EDS) for Kabylake PCH-LP Family for more detailed
information.

2.7 Hardware Sequencing

Host/Bios and ME may read/write /erase flash via Hardware Sequencing or Software
Sequencing registers.

Kabylake Hardware sequencing has been enhanced to include all operations the BIOS
needs to perform.

Note: Host / Bios Software Sequencing is not supported in Kabylake.

Hardware sequencing has a predefined list of opcodes, the PCH discovers the 4k and
64k erase opcodes via SFDP.

See Serial Peripheral Interface Memory Mapped Configuration Registers in

Kabylake PCH-LP Family External Design Specification (EDS) for more details.

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PCH SPI Flash Compatibility Requirement

3 PCH SPI Flash Compatibility

Requirement

3.1 Kabylake PCH-LP SPI Flash Requirements

• Kabylake PCH-LP Family allows for up to two SPI flash devices to store BIOS, Intel®
ME FW and integrated LAN information.
— Intel® ME FW is required for Kabylake PCH-LP Family-based platforms
— Each SPI component can support up to 64 MB (128 MB total addressable) using
26-bit addressing
• 3.3V or 1.8V SPI I/O buffer VCC
• SPI Fast Read instruction is supported and frequency of 17 MHz, 30 MHz and 48
MHz
• SPI Dual Output and Dual I/O Fast Read instruction is supported with frequency of
17 MHz, 30 MHz and 48 MHz
• SPI Quad Output and Quad I/O Fast read instruction is supported with frequency of
17 MHz, 30 MHz and 48 MHz

If there are two SPI components, both components have to support fast read in order
to enable Fast Read in PCH.

Enabling Quad mode reads may require special configuration of the flash device during
platform manufacturing, prior to first boot. No special configuration is required for flash
devices that support Quad mode but do not contain a Quad Enable (QE) bit. Flash
devices that contain a QE bit must be configured with QE=1. Several manufacturers
offer SKU’s with QE=1 by default.

3.1.1 General Requirements

• Erase size capability of: 4 KBytes erase must be supported uniformly across the
flash array. If 64k erase is also supported, then it must be supported uniformly
across the flash array.
• Serial flash device must ignore the upper address bits such that an address of
FFFFFFh aliases to the top of the flash memory.
• SPI Compatible Mode 0 support: Clock phase is 0 and data is latched on the rising
edge of the clock.
• If the device receives a command that is not supported or incomplete (less than 8
bits), the device must discard the cycle gracefully without any impact on the flash
content.
• An erase command (page, sector, block, chip, etc.) must set all bits inside the
designated area (page, sector, block, chip, etc.) to 1 (Fh).
• Status Register bit 0 must be set to 1 when a write, erase or write to status register
is in progress and cleared to 0 when a write or erase is NOT in progress.
• Devices requiring the Write Enable command must automatically clear the Write
Enable Latch at the end of Data Program instructions.

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PCH SPI Flash Compatibility Requirement

• The flexibility to perform a write between 1 byte to 64 bytes is required.

• SFDP fields: dword 1, bit 4 “Write Enable Instruction”. Dword 1, bit 3 “Volatile
Status Register”, both bits must be 0.

Intel Management Firmware must meet the SPI flash based BIOS Requirements plus:
• 2.2 Serial Flash Discoverable Parameter (SFDP)
• 3.1.4 JEDEC ID (Opcode 9Fh)
• 3.1.5 Multiple Page Write Usage Model
• 3.1.6 Hardware Sequencing Requirements

Write protection scheme must meet guidelines as defined in SPI Flash Unlocking
Requirements for Intel Management Engine.

SPI Flash Unlocking Requirements for Intel Management Engine

a. Flash devices must be globally unlocked (read, write and erase access on the
ME region) from power on by writing 0 to the Block Protect bits in the flash’s
status register to disable write protection.
b. If the status register must be unprotected, it must use the write enable 06h
instruction.
c. Opcode 01h (write to status register) must then be used to write 0 to the Block
Protect bits in the status register. If the device contains a Quad Enable bit in
the status register, then firmware must perform a read-modify-write to prevent
changing the state of the QE bit when writing to the status register. This must
unlock the entire part. If the SPI flash’s status register has non-volatile bits
that must be written to, bits [5:2] of the flash’s status register must be all 0h
to indicate that the flash is unlocked.

3.1.2 Bios Requirement

BIOS must ensure there is no SPI flash based read/write/erase protection on the GbE
region. GbE firmware and drivers for the integrated LAN need to be able to read, write
and erase the GbE region at all times.

3.1.3 Software / Firmware Requirements

The recommended Intel ME firmware flow for clearing block protect is:
1. Determine the location of the Quad Enable (QE) bit using the SFDP table QER field
(for devices that support SFDP rev A or later) or the VSCC table QER field (for
SDFDP rev -)
2. Read status registers 1 and 2.
3. Modify status to clear Block Protect bits and leave QE bit unchanged.
4. Write the status register using an atomic {write_enable, write_status} sequence
(this happens automatically when hardware sequencing is used.
5. Issue a write_disable instruction using software sequencing.

After global unlock, BIOS has the ability to lock down small sections of the flash as long
as they do not involve the ME or GbE region. See 6.1 Unlocking SPI Flash Device
318H

Protection for Kabylake PCH-LP Platform and 6.2 Locking SPI Flash via Status Register
320H1

for more information about flash based write/erase protection.

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PCH SPI Flash Compatibility Requirement

3.1.4 JEDEC ID (Opcode 9Fh)

Since each serial flash device may have unique capabilities and commands, the JEDEC
ID is the necessary mechanism for identifying the device so the uniqueness of the
device can be comprehended by the controller (master). The JEDEC ID uses the opcode
9Fh and a specified implementation and usage model. This JEDEC Standard
Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV1
and is available on the JEDEC website: www.jedec.org.

3.1.5 Multiple Page Write Usage Model

Intel platforms have firmware usage models require that the serial flash device support
multiple writes to a page (minimum of 512 writes) without requiring a preceding erase
command. BIOS commonly uses capabilities such as counters that are used for error
logging and system boot progress logging. These counters are typically implemented
by using byte-writes to ‘increment’ the bits within a page that have been designated as
the counter. The Intel firmware usage models require the capability for multiple data
updates within any given page. These data updates occur via byte-writes without
executing a preceding erase to the given page. Both the BIOS and Intel Management
Engine firmware multiple page write usage models apply to sequential and non-
sequential data writes.

Flash parts must also support the writing of a single byte 1024 times in a single 256-
byte page without erase. There will be 64 pages where this usage model will occur.
These 64 pages will be every 16 kilobytes.

3.1.6 Hardware Sequencing Requirements

The following table contains a list of commands and the associated opcodes that a SPI-
based serial flash device must support in order to be compatible with hardware
sequencing.
Commands OPCODE Notes

Write to Status 01h Writes a byte to SPI flash’s status register. Enable Write to
Register Status Register command must be run prior to this command

Program Data 02h Single byte or 64 byte write as determined by flash part
capabilities and software

Read Data 03h

Write Disable 04h

Read Status 05h Outputs contents of SPI flash’s status register

Write Enable 06h

Fast Read 0Bh

Enable Write to Status 06h If write-status 01h requires a write-enable, then 06h must
Register enable write-status.

Erase Programmable/ 4 Kbyte erase. Uses the value from SFDP (if available) else
Discoverable value from VSCCn Erase Opcode register value

Chip Erase C7h and/or 60

JEDEC ID 9Fh See Section 3.1.4 for more information

Dual Output Fast Read 3Bh/ Discoverable Discoverable opcodes are obtained from each component’s
SFDP table

Dual I/O Fast Read Discoverable Opcode is optained from each component’s SFDP table

Quad I/O Fast Read Discoverable Opcode is optained from each component’s SFDP table

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PCH SPI Flash Compatibility Requirement

3.2 Kabylake PCH-LP SPI AC Electrical Compatibility

Guidelines
Table 3-1. SPI Timings (17 MHz)
Sym Parameter Min Max Units Notes

t180a Serial Clock Frequency - 20MHz Operation 17.06 18.73 MHz 1

Tco of SPI_MOSI with respect to serial clock falling

t183a -5 13 ns
edge at the host

Setup of SPI_MISO with respect to serial clock falling

t184a 16 - ns
edge at the host

Hold of SPI_MISO with respect to serial clock falling

t185a 0 - ns
edge at the host

Setup of SPI_CS[1:0]# assertion with respect to serial

t186a 30 - ns
clock rising edge at the host

Hold of SPI_CS[1:0]# assertion with respect to serial

t187a 30 - ns
clock rising edge at the host

t188a SPI_CLK High time 26.37 - ns 2

t189a SPI_CLK Low time 26.82 - ns 2

Notes:
1. Typical clock frequency driven by Kabylake PCH-LP Family is 17 MHz.
2. Measurement point for low time and high time is taken at.5(VccME3_3).

Table 3-2. SPI Timings (30 MHz)

Sym Parameter Min Max Units Notes

t180b Serial Clock Frequency - 33 MHz Operation 29.83 32.81 MHz 1

Tco of SPI_MOSI with respect to serial clock falling

t183b -5 5 ns
edge at the host

Setup of SPI_MISO with respect to serial clock falling

t184b 8 - ns
edge at the host

Hold of SPI_MISO with respect to serial clock falling

t185b 0 - ns
edge at the host

Setup of SPI_CS[1:0]# assertion with respect to serial

t186b 30 - ns
clock rising edge at the host

Hold of SPI_CS[1:0]# assertion with respect to serial

t187b 30 - ns
clock rising edge at the host

t188b SPI_CLK High time 14.88 - ns 2

t189b SPI_CLK Low time 15.18 - ns 2

Notes:
1. Typical clock frequency driven by Kabylake PCH-LP Family is 33 MHz.
2. Measurement point for low time and high time is taken at.5(VccME3_3).

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PCH SPI Flash Compatibility Requirement

Table 3-3. SPI Timings (48 MHz)

Sym Parameter Min Max Units Notes

t180c Serial Clock Frequency - 50 MHz Operation 46.99 53.40 MHz 1

Tco of SPI_MOSI with respect to serial clock falling

t183c edge at the host -3 3 ns

Setup of SPI_MISO with respect to serial clock falling

t184c edge at the host 8 - ns

Hold of SPI_MISO with respect to serial clock falling

t185c edge at the host 0 - ns

Setup of SPI_CS[1:0]# assertion with respect to

t186c serial clock rising edge at the host 30 - ns

Hold of SPI_CS[1:0]# assertion with respect to serial

t187c clock rising edge at the host 30 - ns

t188c SPI_CLK High time 7.84 - ns 2, 3

t189c SPI_CLK Low time 11.84 - ns 2, 3

Notes:
1. Typical clock frequency driven by Kabylake PCH-LP Family is 48 MHz.
2. When using 48 MHz mode ensure target flash component can meet t188c and t189c specifications.
Recommended to use SPI flash component rated at 66 MHz or faster.
3. Measurement point for low time and high time is taken at.5(VccME3_3).

Figure 3-1. SPI Timing

t188 t189

SPI_CLK
t183

SPI_MOSI
t184 t185

SPI_MISO

t186 t187

SPI_CS#

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PCH SPI Flash Compatibility Requirement

3.3 SPI Flash DC Electrical Compatibility Guidelines

Parameter Min Max Units Notes

Supply Voltage (Vcc) 3.14 3.7 V

Input High Voltage 0.5*VCC VCC+0.5 V

Input Low Voltage -0.5 0.3*VCC V

Output High Characteristics 0.9*VCC VCC V Ioh = -0.5mA

Output Low Characteristics 0.1*VCC Iol = 1.5mA

Input Leakage Current -10 10 uA

Output Rise Slew Rate (0.2 Vcc - 0.6 Vcc) 1 4 V/ns 1

Output Fall Slew Rate (0.6 Vcc - 0.2 Vcc) 1 4 V/ns 1

Note:
1. Testing condition: 1K pull up to Vcc, 1kohm pull down and 10 pF pull down and 1/2 inch trace. See Figure
3.3 for more detail.

Figure 3-2. PCH Test Load

§§

Intel Confidential 20
 Descriptor Overview

4 Descriptor Overview

The Flash Descriptor is a data structure that is programmed on the SPI flash part on Kabylake PCH-LP based
platforms. The Descriptor data structure describes the layout of the flash as well as defining configuration
parameters for the PCH. The descriptor is on the SPI flash itself and is not in memory mapped space like PCH
programming registers. The maximum size of the Flash Descriptor is 4 KBytes. It requires its own discrete
erase block, so it may need greater than 4 KBytes of flash space depending on the flash architecture that is on
the target system.

The information stored in the Flash Descriptor can only be written during the manufacturing process as its
read/write permissions must be set to Read Only when the computer leaves the manufacturing floor.

The Descriptor has 9 parts:

Figure 4-1. Flash Descriptor (Kabylake PCH-LP)

• The Flash signature at the bottom of the flash (offset 10h) must be 0FF0A55Ah in order to be in Descriptor
mode.

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 Descriptor Overview

• The Descriptor map has pointers to the lower five descriptor sections as well as the size of each.
• The Component section has information about the SPI flash part(s) the system. It includes the number of
components, density of each component, read, write and erase frequencies and invalid instructions.
• The Region section defines the base and the limit of the BIOS, ME, GbE, PDR (Optional), Embedded
Controller (EC)and regions as well as their size.
• The master region contains the hardware security settings for the flash, granting read/write permissions
for each region and identifying each master.
• PCH chipset soft strap sections contain PCH configurable parameters.
• The Reserved region is for future chipset usage.
• The Descriptor Upper Map determines the length and base address of the Intel® ME VSCC Table.
• The Intel® ME VSCC Table holds the JEDEC ID and the ME VSCC information for all the SPI Flash part(s)
supported by the NVM image. BIOS and GbE write and erase capabilities depend on VSCC0 and VSCC1
registers in SPIBAR memory space.
• OEM Section is 256 Byte section reserved at the top of the Flash Descriptor for use by the OEM.

See SPI Supported Feature Overview and Flash Descriptor Records in the Kabylake PCH-LPH Family
External Design Specification (EDS).

4.1 Flash Descriptor Content

The following sections describe the data structure of the Flash Descriptor on the SPI device. These are not
registers or memory space within PCH. FDBAR - is address 0x0 on the SPI flash device on chip select 0.

Recommended flash descriptor map:

Region Name Starting Address

Signature 0x10

Component FCBA 0x30

Regions FRBA 0x40

Masters FMBA 0x80

PCH Straps FPSBA 0x100

CPU Straps FCPUSBA 0x300

Register Init FIBA 0x340

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 Descriptor Overview

4.1.1 Descriptor Signature and Map

4.1.1.1 FLVALSIG - Flash Valid Signature
(Flash Descriptor Records)
Memory Address:FDBAR + 010h Size: 32 bits

Recommended Value:0FF0A55Ah

Bits Description

Flash Valid Signature. This field identifies the Flash Descriptor sector as valid. If the contents at
31:0 this location contain 0FF0A55Ah, then the Flash Descriptor is considered valid and it will operate in
Descriptor Mode (Note: Non-Descriptor mode is not supported for Kabylake).

4.1.1.2 FLMAP0 - Flash Map 0 Register

(Flash Descriptor Records)
Memory Address: FDBAR + 014h Size: 32 bits

Bits Description

31:27 Reserved

26:24 Reserved

Flash Region Base Address (FRBA). This identifies address bits [11:4] for the Region portion of
the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.
23:16

Set this value to 04h. This will define FRBA as 40h.

15:13 Reserved

12 Reserved. Set to ‘0’

11 Reserved. Set to ‘0’

10 Reserved

Number Of Components (NC). This field identifies the total number of Flash Components. Each
supported Flash Component requires a separate chip select.
9:8 00 = 1 Component
01 = 2 Components
All other settings = Reserved

Flash Component Base Address (FCBA). This identifies address bits [11:4] for the Component
portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.
7:0

set this field to 03h. This will define FCBA as 30h

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 Descriptor Overview

4.1.1.3 FLMAP1 - Flash Map 1 Register

(Flash Descriptor Records)
Memory Address: FDBAR + 018h Size: 32 bits

Recommended Value: 41100208h

Bits Description

PCH Strap Length (PSL). Identifies the 1s based number of Dwords of PCH Straps to be read, up
to 255 DWs (1KB) max. A setting of all 0's indicates there are no PCH DW straps.
31:24

This field MUST be set to 42h

Flash PCH Strap Base Address (FPSBA). This identifies address bits [11:4] for the PCH Strap
portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.
23:16

Set this field to 10h. This will define FPSBA to 100h

15:11 Reserved

Number Of Masters (NM). This field identifies the total number of Flash Masters.
10:8
Set this field to 10b

Flash Master Base Address (FMBA). This identifies address bits [11:4] for the Master portion of
the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.
7:0

Set this field to 08h. This will define FMBA as 80h

4.1.1.4 FLMAP2—Flash Map 2 Register

(Flash Descriptor Records)
Memory Address: FDBAR + 01Ch Size: 32 bits

Bits Description

Register Init Length (RIL): Identifies the 1's based number of register initialization entries. If
31:24 this field is set to 0, then there are no Register Init entries to send. Each register init entry is 2DW
in length. Set this field to 0h.
23:16 Reserved. Set this field to 31h.

CPU Strap Length (CPUSL). Identifies the 1's based number of Dwords of Processor Straps to be
15:08 read, up to 255 DWs (1KB) max. A setting of all 0's indicates there are no Processor DW straps.
Set this field to 03h.

Flash CPU Strap Base Address (FCPUSBA). This identifies address bits [11:4] for the Processor
7:0 Strap portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.
Set this field to 30h. This will define FCPUSBA as 300h

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 Descriptor Overview

4.1.2 Flash Descriptor Component Section

4.1.2.1 FLCOMP—Flash Components Register
(Flash Descriptor Records)
The following section of the Flash Descriptor is used to identify the different SPI Flash Components and their
capabilities.

Memory Address: FCBA + 000h Size: 32 bits

Bits Description

31 Reserved

Dual Output Fast Read Support

0 : Dual Output Fast Read is not supported
30 1 : Dual Output Fast Read is supported
Notes:
1. This setting is no longer required and has deprecated in Kabylake.

Read ID and Read Status Clock Frequency.

010 = 48 MHz
100 = 30 MHz
110 = 17 MHz
29:27 All other Settings = Reserved
Notes:
1. If more than one Flash component exists, this field must be set to the lowest common
frequency of the different Flash components.
2. If setting to 48 MHz, ensure flash meets timing requirements defined in Table 3-3

Write and Erase Clock Frequency.

010 = 48 MHz
100 = 30 MHz
110 = 17 MHz
26:24 All other Settings = Reserved
Notes:
1. If more than one Flash component exists, this field must be set to the lowest common
frequency of the different Flash components.
2. If setting to 48 MHz, ensure flash meets timing requirements defined in Table 3-3

Fast Read Clock Frequency. This field identifies the frequency that can be used with the Fast Read
instruction. This field is undefined if the Fast Read Support field is '0'.
010 = 48 MHz
100 = 30 MHz
110 = 17 MHz
23:21
All other Settings = Reserved
Notes:
1. If more than one Flash component exists, this field must be set to the lowest common
frequency of the different Flash components.
2. If setting to 48 MHz, ensure flash meets timing requirements defined in Table 3-3

Fast Read Support.

0 = Fast Read is not Supported
1 = Fast Read is supported

If the Fast Read Support bit is a '1' and a device issues a Direct Read or issues a read command from
the Hardware Sequencer and the length is greater than 4 bytes, then the SPI Flash instruction
should be “Fast Read”. If the Fast Read Support is a '0' or the length is 1-4 bytes, then the SPI Flash
20
instruction should be “Read”.

Reads to the Flash Descriptor always use the Read command independent of the setting of this bit.
Notes:
1. If more than one Flash component exists, this field can only be set to '1' if both components
support Fast Read.
2. It is strongly recommended to set this bit to 1b

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Descriptor Overview

Bits Description

Read Clock Frequency.

110= 17MHz
All other Settings = Reserved
19:17
Note:
1. If more than one Flash component exists, this field must be set to the lowest common
frequency of the different Flash components.

16:8 Reserved

Component 1 Density. (C1DEN) This field identifies the size of the 2nd Flash component connected
directly to the PCH. If there is not 2nd Flash component, the contents of this field should be read as
“1111b”
0000 = 512 KB
0001 = 1 MB
0010 = 2 MB
0011 = 4 MB
7:4 0100 = 8 MB
0101 = 16 MB
0110 = 32 MB
0111 = 64 MB
1000 - 1110 = Reserved

Note: This field is defaulted to “1111b” after reset

Note: C1DEN field will be ignored if FLMAP0.NC bit [9:8] is set to 00 i.e. 1 component only.

Component 0 Density (C0DEN). This field identifies the size of the 1st or only Flash component
connected directly to the PCH.
0000 = 512 KB
0001 = 1 MB
0010 = 2 MB
0011 = 4 MB
3:0 0100 = 8 MB
0101 = 16 MB
0110 = 32 MB
0111 = 64 MB
1000 - 1111 = Reserved
Note: This field is defaulted to “0101b” (16MB) after reset.

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 Descriptor Overview

4.1.2.2 FLILL—Flash Invalid Instructions Register

(Flash Descriptor Records)
Memory Address: FCBA + 004h Size: 32 bits

Bits Description

Invalid Instruction 3.

31:24 Default set to 0xAD

See definition of Invalid Instruction 0

Invalid Instruction 2.

23:16 Default set to 0x60

See definition of Invalid Instruction 0

Invalid Instruction 1.

15:8 Default set to 0x42

See definition of Invalid Instruction 0

Invalid Instruction 0.

Default set to 0x21

7:0 Note: Opcode for an instruction that the Flash Controller should protect against, such as Chip
Erase. This byte should be set to 0 if there are no invalid instructions to protect against for
this field. Opcodes programmed in the Software Sequencing Opcode Menu Configuration
and Prefix-Opcode Configuration are not allowed to use any of the Invalid Instructions
listed in this register.

4.1.2.3 FLILL1—Flash Invalid Instructions Register

(Flash Descriptor Records)
Memory Address: FCBA + 008h Size: 32 bits

Bits Description

Invalid Instruction 7.

31:24 Default set to C7

See definition of Invalid Instruction 0

Invalid Instruction 6.

23:16 Default set to 0xC4

See definition of Invalid Instruction 0

Invalid Instruction 5.

15:8 Default set to 0xB9

See definition of Invalid Instruction 0

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 Descriptor Overview

Bits Description

Invalid Instruction 4.

7:0 Default set to 0xB7

See definition of Invalid Instruction 0

4.1.3 Flash Descriptor Region Section

The following section of the Flash Descriptor is used to identify the different Regions of the NVM image on the
SPI flash.

Flash Regions:
• If a particular region is not using SPI Flash, the particular region should be disabled by setting the Region
Base to all 1's, and the Region Limit to all 0's (base is higher than the limit)
• For each region except FLREG0, the Flash Controller must have a default Region Base of 7FFFh and the
Region Limit to 0000h within the Flash Controller in case the Number of Regions specifies that a region is
not used.

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4.1.3.1 FLREG0—Flash Region 0 (Flash Descriptor) Register

(Flash Descriptor Records)
Memory Address: FRBA + 000h Size: 32 bits

Recommended Value: 00000000h

Bits Description

31 Reserved

Region Limit. This specifies bits 26:12 of the ending address for this Region.

30:16 Notes:
1. Set this field to 0b. This defines the ending address of descriptor as being FFFh.
2. Region limit address Bits[11:0] are assumed to be FFFh

15 Reserved

Region Base. This specifies address bits 26:12 for the Region Base.
14:0
Note: Set this field to all 0s. This defines the descriptor address beginning at 0h.

4.1.3.2 FLREG1—Flash Region 1 (BIOS) Register

(Flash Descriptor Records)
Memory Address: FRBA + 004h Size: 32 bits

Bits Description

31 Reserved

Region Limit. This specifies bits 26:12 of the ending address for this Region.
Notes:
30:16 1. Must be set to 0000h if BIOS region is unused (on Firmware hub)
2. Ensure BIOS region size is a correct reflection of actual BIOS image that will be used in the
platform
3. Region limit address Bits[11:0] are assumed to be FFFh

15 Reserved

Region Base. This specifies address bits 26:12 for the Region Base.
14:0
Note: If the BIOS region is not used, the Region Base must be programmed to 7FFFh

4.1.3.3 FLREG2—Flash Region 2 (Intel® ME) Register

(Flash Descriptor Records)
Memory Address: FRBA + 008h Size: 32 bits

Bits Description

31 Reserved

Region Limit. This specifies bits 26:12 of the ending address for this Region.
Notes:
30:16 1. Ensure size is a correct reflection of actual Intel® ME firmware size that will be used in the
platform
2. Region limit address Bits[11:0] are assumed to be FFFh

15 Reserved

14:0 Region Base. This specifies address bits 26:12 for the Region Base.

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4.1.3.4 FLREG3—Flash Region 3 (GbE) Register

(Flash Descriptor Records)
Memory Address: FRBA + 00Ch Size: 32 bits

Bits Description

31 Reserved

Region Limit. This specifies bits 26:12 of the ending address for this Region.
Notes:
30:16 1. The maximum Region Limit is 128KB above the region base.
2. If the GbE region is not used, the Region Limit must be programmed to 0000h
3. Region limit address Bits[11:0] are assumed to be FFFh

15 Reserved

Region Base. This specifies address bits 26:12 for the Region Base.
14:0
Note: If the GbE region is not used, the Region Base must be programmed to 7FFFh

4.1.3.5 FLREG4—Flash Region 4 (Platform Data) Register

(Flash Descriptor Records)
Memory Address: FRBA + 010h Size: 32 bits

Bits Description

31 Reserved

Region Limit. This specifies bits 26:12 of the ending address for this Region.
Notes:
30:16 1. If PDR Region is not used, the Region Limit must be programmed to 0000h
2. Ensure BIOS region size is a correct reflection of actual BIOS image that will be used in the
platform
3. Region limit address Bits[11:0] are assumed to be FFFh

15 Reserved

Region Base. This specifies address bits 26:12 for the Region Base.
14:0
Note: If the Platform Data region is not used, the Region Base must be programmed to 7FFFh

4.1.3.6 FLREG8—Flash Region 8(Embeded Controller) Register

(Flash Descriptor Records)
Memory Address: FRBA + 020h Size: 32 bits

Bits Description

31 Reserved

30:16 Region Limit (RL): This specifies address bits 26:12 for the Region n
Limit.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREGn.Region Limit, where 7 <= n <= 11

15 Reserved

14:0 Region Base (RB): This specifies address bits 26:12 for the Region n Base
The value in this register is loaded from the contents in the Flash Descriptor. FLREGn.Region Base,
where 7 <= n <= 11

Note: Flash Region 5 (FRBA + 014h), Region 6 (FRBA + 018h), Region 7 (FRBA + 01Ch) and Region 9 (FRBA +
024h) are all reserved in client platform and should set to 7FFFh.

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4.1.4 Flash Descriptor Master Section

4.1.4.1 FLMSTR1—Flash Master 1 (Host CPU/ BIOS)
Memory Address: FMBA + 000h Size: 32 bits

Bits Description

Master Region Write Access: Each bit [31:20] corresponds to Regions [11:0]. If the bit is set,
this master can erase and write that particular region through register accesses.
31:20
Note: Bit 21 and 26 are don’t care as the primary master always has read/write permission to its
primary region

Master Region Read Access: Each bit [19:8] corresponds to Regions [11:0]. If the bit is set, this
master can read that particular region through register accesses.
19:8
Note: Bit 9 and 14 are don’t care as the primary master always read/write permission to its primary
region.

7:0 Reserved

4.1.4.2 FLMSTR2—Flash Master 2 (Intel® ME)

Memory Address: FMBA + 004h Size:32 bits

Bits Description

Master Region Write Access: Each bit [31:20] corresponds to Regions [11:0]. If the bit is set,
this master can erase and write that particular region through register accesses.
31:20
Note: Bit 22 is a don’t care as the primary master always has read/write permission to its primary
region

Master Region Read Access: Each bit [19:8] corresponds to Regions [11:0]. If the bit is set, this
master can read that particular region through register accesses.
19:8
Note: Bit 10 is a don’t care as the primary master always read/write permission to its primary
region.

7:0 Reserved

4.1.4.3 FLMSTR3—Flash Master 3 (GbE)

Memory Address: FMBA + 008h Size:32 bits

Bits Description

Master Region Write Access: Each bit [31:20] corresponds to Regions [11:0]. If the bit is set,
this master can erase and write that particular region through register accesses.
31:20
Note: Bit 23 is a don’t care as the primary master always has read/write permission to its primary
region

Master Region Read Access: Each bit [19:8] corresponds to Regions [11:0]. If the bit is set, this
master can read that particular region through register accesses.
19:8
Note: Bit 11 is a don’t care as the primary master always read/write permission to its primary
region.

7:0 Reserved

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4.1.4.4 FLMSTR4—Flash Master 4 (Reserved)

Memory Address: FMBA + 00Ch Size:32 bits

Bits Description

31:0 Reserved set to ‘0’

4.1.4.5 FLMSTR5—Flash Master 5 (EC)

Memory Address: FMBA + 010h Size:32 bits

Bits Description

Master Region Write Access: Each bit [31:20] corresponds to Regions [11:0]. If the bit is set,
this master can erase and write that particular region through register accesses.
31:20
Note: Bit 28 is a don’t care as the primary master always has read/write permission to its primary
region

Master Region Read Access: Each bit [19:8] corresponds to Regions [11:0]. If the bit is set, this
master can read that particular region through register accesses.
19:8
Note: Bit 16 is a don’t care as the primary master always read/write permission to its primary
region.

7:0 Reserved

4.1.5 PCH / CPU Softstraps

See Chapter 9, “Flash Descriptor PCH / CPU Configuration Section” for details.

4.1.6 Descriptor Upper Map Section

4.1.6.1 FLUMAP1—Flash Upper Map 1
(Flash Descriptor Records)
Memory Address:FDBAR + EFCh Size: 32 bits

Bits Default Description

31:16 0 Reserved

Intel® ME VSCC Table Length (VTL). Identifies the 1s based number of

15:8 1 DWORDS contained in the VSCC Table. Each SPI component entry in the table is 2
DWORDS long.

Intel® ME VSCC Table Base Address (VTBA). This identifies address bits [11:4]
7:0 1
for the VSCC Table portion of the Flash Descriptor. Bits [26:12] and bits [3:0] are 0.

4.1.7 Intel® ME Vendor Specific Component Capabilities Table

Entries in this table allow support for a SPI flash part for Intel Management Engine capabilities including Intel®
Active Management Technology.

Since Flash Partition Boundary Address (FPBA) has been removed, UVSCC and LVSCC has been replaced with
VSCC0 and VSCC1 in Kabylake PCH-LP. VSCC0 is for SPI component 0 and VSCC1 is for SPI component 1.

Each VSCC table entry is composed of two 32 bit fields: JEDEC IDn and the corresponding VSCCn value.

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See 4.4 Intel® ME Vendor-Specific Component Capabilities (Intel® ME VSCC) Table for information on how to
program individual entries.

4.1.7.1 JID0—JEDEC-ID 0 Register

(Flash Descriptor Records)
Memory Address: VTBA + 000h Size: 32 bits

Bits Description

31:24 Reserved

SPI Component Device ID 1. This field identifies the second byte of the Device ID of the SPI Flash
23:16
Component. This is the third byte returned by the Read JEDEC-ID command (opcode 9Fh).

SPI Component Device ID 0. This field identifies the first byte of the Device ID of the SPI Flash
15:8
Component. This is the second byte returned by the Read JEDEC-ID command (opcode 9Fh).

SPI Component Vendor ID. This field identifies the one byte Vendor ID of the SPI Flash
7:0
Component. This is the first byte returned by the Read JEDEC-ID command (opcode 9Fh).

4.1.7.2 VSCC0—Vendor Specific Component Capabilities 0

(Flash Descriptor Records)
Memory Address: VTBA + 004h Size: 32 bits

Note: VSCC0 applies to SPI flash that connected to CS0.

C

Bits Description

31:16 Reserved

Erase Opcode (EO). This field must be programmed with the Flash erase instruction opcode that
15:8
corresponds to the erase size that is in BES.

Quad Enable Requirements (QER)

000 = Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 reads based on instruction.
DQ3 / HOLD# functions as hold during instruction phase.
001 = QE is bit 1 of status register 2. It is set via Write Status with two data bytes where bit 1 of
the second byte is one. It is cleared via Write Status with two data bytes where bit 1 of the
second byte is zero. Writing only one byte to the status register has the side effect of clearing
status register 2, including the QE bit. The 100b code is used if writing one byte to the status
register does not modify status register 2.
010 = QE is bit 6 of status register 1. It is set via Write Status with one data byte where bit 6 is
one. It is cleared via Write Status with one data byte where bit 6 is zero.
011 = QE is bit 7 of status register 2. It is set via Write status register 2 instruction 3Eh with one
7:5 data byte where bit 7 is one. It is cleared via Write status register 2 instruction 3Eh with one
data byte where bit 7 is zero. The status register 2 is read using instruction 3Fh.
100 = QE is bit 1 of status register 2. It is set via Write Status with two data bytes where bit 1 of
the second byte is one. It is cleared via Write Status with two data bytes where bit 1 of the
second byte is zero. In contrast to the 001b code, writing one byte to the status register does
not modify status register 2.
101 = QE is bit 1 of the status register 2. Status register 1 is read using Read Status instruction
05h. Status register 2 is read using instruction 35h. QE is set via Write Status instruction 01h
with two data bytes where bit 1 of the second byte is one. It is cleared via Write Status with
two data bytes where bit 1 of the second byte is zero.
other = reserved
Note: Please refer to Table note#1 below for details.

4:0 Reserved set to 00101b

Notes:
1. The manufacturers information included in the QER list are for guidance purpose. Some manufacturer
devices operate as shown in the table above. Check manufacturer’s data sheet for exact requirements.

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4.1.7.3 JIDn—JEDEC-ID Register n

(Flash Descriptor Records)
Memory Address: VTBA + (n*8)h Size:32 bits
“n” is an integer denoting the index of the Intel® ME VSCC table. See Table 4.1.7.1 for details.

4.1.7.4 VSCCn—Vendor Specific Component Capabilities n

(Flash Descriptor Records)
Memory Address: VTBA + 0C4h + (n*8)h Size: 32 bits
®
“n” is an integer denoting the index of the Intel ME VSCC table. See Table 4.1.7.2 for details.

4.2 OEM Section

Memory Address: F00h Size: 256 Bytes

256 Bytes are reserved at the top of the Flash Descriptor for use by the OEM. The information stored by the
OEM can only be written during the manufacturing process as the Flash Descriptor read/write permissions
must be set to Read Only when the computer leaves the manufacturing floor. The PCH Flash controller does
not read this information. FFh is suggested to reduce programming time.

4.3 Region Access Control

Regions of the flash can be defined from read or write access by setting a protection parameter in the Master
section of the Descriptor. There are only three masters that have the ability to access other regions: CPU/
BIOS, Intel® ME Firmware, and GbE software/driver running on CPU.

Table 4-1. Region Access Control Table Options

Master Read/Write Access

Region (#) CPU / BIOS IFWI (Intel® ME) GbE Controller EC

Descriptor Region
Read Only Read Only Not Accessible Read Only
Bit (0)

CPU / BIOS can

BIOS Region always read from
Not Accessible Not Accessible Not Accessible
Bit(1) and write to BIOS
region prior to EOP

Intel® Management Intel®ME can

Engine Region Read / Write (BIOS always read from
Not Accessible Not Accessible
Only) and write to
Bit (2) Intel®ME region

GbE Region GbE software can

Read / Write (BIOS
Read / Write always read from and Not Accessible
Bit (3) Only)
write to GbE region

PDR Region Read / Write (BIOS

Not Accessible Not Accessible Not Accessible
Bit (4) Only) (Optional)

EC - Embedded EC can always

Read / Write (BIOS
Controller (Optional) Read / Write Not Accessible read from and
Only)
Region Bit (8) write to EC region

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4.3.1 Intel Recommended Permissions for Region Access

The following Intel recommended read/write permissions are necessary to secure Intel® ME and Intel® ME
FW.

Table 4-2. Recommended Read/Write Permissions

Descriptor BIOS Intel® ME GbE PDR
EC Region
Master Access Region Region Region Region Region
Bit8
Bit 0 Bit1 Bit2 Bit3 Bit4

ME read access Y N Y Y N N

ME write access N N Y N N N

GbE read access Y N N Y N N

GbE write access N N N Y N N

BIOS read access Y Y Y Y ‡ †

BIOS write access N Y N Y ‡ †

EC read access Y * N N N Y

EC write access N N N N N Y

Note:
1. ‡ = Host access to PDR is the discretion of the customer. Implementation of PDR is optional.
2. † = Optional BIOS / Host access to EC region is the discretion of the customer.
3. * = Optional EC Read access to BIOS.

The table below shows the values to be inserted into the Flash image tool. The values below will provide the
access levels described in the table above.

Warning: Pre-configuring the flash image to Intel recommended read / write permission through the Intel® FIT tool and
then flashing the resulting image will cause the platform to enter into end-of-manufacturing flow which will
result in the FPFs being permanently set in the PCH if the platform is using production silicon and production
Intel® ME firmware with the PV bit set.

Table 4-3. Recommended Read/Write Settings for Platforms

ME GbE BIOS EC

Read 0b 0000 0000 1101 = 0x00D 0b 0000 0000 1001 = 0x009 0b 000† 000‡ 1111 = 0x†‡F 0b 0001 0000 00*1 = 0x101 or 0x103

Write 0b 0000 0000 0100 = 0x004 0b 0000 0000 1000 = 0x008 0b 000† 000‡ 1010 = 0x†‡A 0b 0001 0000 0000 = 0x100

Note:
1. ‡ = Value dependent on if PDR is implemented and if Host access is desired.
2. † = Optional BIOS / Host access to EC region is the discretion of the customer.
3. * = Optional EC Read access to BIOS.

4.3.2 Overriding Region Access

Once access Intel recommended Flash settings have been put into the flash descriptor, it may be necessary to
update the ME region with a Host program or write a new Flash descriptor.

Assert HDA_SDO HIGH during the rising edge of PWROK to set the Flash descriptor override strap.

This strap should only be visible and available in manufacturing or during product development.

After this strap has been set you can use a host based flash programming tool like FPT.exe to write/read any
area of serial flash that is not protected by Protected Range Registers. Any area of flash protected by Protected
range Registers will still NOT be writeable/readable.

See 6.3 SPI Protected Range Register Recommendations for more details.

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4.4 Intel® ME Vendor-Specific Component Capabilities (Intel® ME

VSCC) Table
The Intel® ME VSCC Table defines how the Intel® ME will communicate with the installed SPI flash if there is
no SFDP table found. This table is defined in the descriptor and is the responsibility of who puts together the
NVM image. VSCCn registers are defined in memory space and must be set by BIOS. This table must define
every flash part that is intended to be used. The size (number of max entries) of the table is defined in 4.1.6.1
FLUMAP1—Flash Upper Map 1 (Flash Descriptor Records). Each Table entry is made of two parts: the JEDEC ID
and VSCC setting. 7

Table 4-4. Jidn - JEDEC ID Portion of Intel® ME VSCC Table

Bits Description

31:24 Reserved.

SPI Component Device ID 1: This identifies the second byte of the Device ID of the SPI Flash
23:16
Component. This is the third byte returned by the Read JEDEC-ID command (opcode 9Fh).

SPI Component Device ID 0: This identifies the first byte of the Device ID of the SPI Flash
15:8
Component. This is the second byte returned by the Read JEDEC-ID command (opcode 9Fh).

SPI Component Vendor ID: This identifies the one byte Vendor ID of the SPI Flash Component.
7:0
This is the first byte returned by the Read JEDEC-ID command (opcode 9Fh).

If using Flash Image Tool (FIT) refer to System Tools user guide in the Intel® ME FW kit and the respective FW
Bring up Guide on how to build the image. If not, refer to 4.1.6.1 FLUMAP1—Flash Upper Map 1 (Flash
Descriptor Records) thru 4.2 OEM Section.

4.4.1 How to Set a VSCC Entry in Intel® ME VSCC Table for Kabylake PCH-LP
Platforms
VSCC0 needs to be programmed in instances where there is only SPI component in the system. When using an
asymmetric flash component (part with two different sets of attributes based on address) VCSCC0 and VSCC1
will need to be used. This includes if the system is intended to support both symmetric AND asymmetric SPI
flash parts.

Refer to 4.4.2 Intel® ME VSCC Table Settings for Kabylake PCH-LP Family Systems.
37H

See text below the table for explanation on how to determine Intel Management Engine VSCC value.

Table 4-5. Vsccn – Vendor-Specific Component Capabilities Portion of the Kabylake PCH-LP Platforms (Sheet
1 of 2)
Bits Description

31:16 Reserved

Erase Opcode (EO). This field must be programmed with the Flash erase instruction opcode that
15:8
corresponds to the erase size that is in BES.

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Table 4-5. Vsccn – Vendor-Specific Component Capabilities Portion of the Kabylake PCH-LP Platforms (Sheet
2 of 2)
Bits Description

Quad Enable Requirements (QER)

000 = Part does not require a Quad Enable bit to be set, either because Quad is not supported or
because the manufacturer permanently enables Quad capability (e.g. Micron, Numonyx).
001 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to status
register clears all bits in register 2, therefore status register writes MUST be two bytes. If
the status register is unlocked and SFDP bits WSR or VSCC WSR is 1 then SPI controller can-
not use the quad output, quad IO features of this part because the hardware will automati-
cally write one byte of zeros to status register with every write/erase. (e.g. Winbond, AMIC,
7:5 Spansion).
010 = Part requires bit 6 of status register 1 to be set to enable quad IO. If the status register is
unlocked and SFDP WSR bit or VSCC WSR is 1 then flash controller cannot use the quad out-
put, quad IO features of this part because the hardware will automatically write one byte of
zeros to status register with every write/erase (e.g. Macronix).
011 = Part requires bit 7 of the configuration register to be set to enable Quad (e.g. Atmel).
100 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to the
status register does not clear the second byte (SST/Microchip, Winbond).

Note: Please refer to Table note#6 below for details.

Write Enable on Write Status (WEWS)

4 0 = 50h is the opcode used to unlock the status register on SPI flash if WSR (bit 3) is set to 1b.
1 = 06h is the opcode used to unlock the status register on SPI flash if WSR (bit 3) is set to 1b.
Note: Please refer to Table Note #4 below for a description how this bit is used.

Write Status Required (WSR)

0 = No automatic write of 00h will be made to the SPI flash’s status register)
3 1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and erase
performed by Intel® ME to the SPI flash.
Note: Please refer to Table Note #5 below for a description how this bit is used.

Write Granularity (WG).

2 0 = 1 Byte
1 = 64 Bytes

Block/Sector Erase Size (BES). This field identifies the erasable sector size for all Flash
components.
00 = 256 Bytes
1:0
01 = 4 K Bytes
10 = 8 K Bytes
11 = 64K Bytes

Notes:
1. Bit 3 (WEWS) and/or bit 4 (WSR) should not be set to ‘1’ if there are non volatile bits in the SPI flash’s
status register. This may lead to premature flash wear out.
2. This is not an atomic (uninterrupted) sequence. The PCH will not wait for the status write to complete
before issuing the next command, potentially causing SPI flash instructions to be disregarded by the
SPI flash part. If the SPI flash component’s status register is non-volatile, then BIOS should issue an
atomic software sequence cycle to unlock the flash part.
3. If both bits 3 (WSR) and 4 (WEWS) are set to 1b, then sequence of 06h 01h 00h is sent to unlock the
SPI flash on EVERY write and erase that Intel Management Engine firmware performs.
4. If bit 3 (WSR) is set to 1b and bit 4 (WEWS) is set to 0b then sequence of 50h 01h 00h is sent to unlock
the SPI flash on EVERY write and erase that Intel Management Engine firmware performs.
5. If bit 3 (WSR) is set to 0b and bit 4 (WEWS) is set to 0b or 1b then sequence of 60h is sent to unlock
the SPI flash on EVERY write and erase that Processor or Intel GbE FW performs.
6. The manufacturers information included in the QER list are for guidance purpose. Some manufacturer
devices operate as shown in the table above. Check manufacturer’s datasheet for exact
requirements.

Erase Opcode (EO) and Block/Sector Erase Size (BSES) should be set based on the flash part and the
firmware on the platform. For Intel® ME enabled platforms this should be 4 KB.

Write Status Required (WSR) or Write Enable on Write Status (WEWS) should be set on flash devices
that require an opcode to enable a write to the status register. Intel® ME Firmware will write a 00h to status
register to unlock the flash part for every erase/write operation. If this bit is set on a flash part that has non-
volatile bits in the status register then it may lead to pre-mature wear out of the flash.

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• Set the WSR bit to 1b and WEWS to 0b if the Enable Write Status Register opcode (50h) is needed to
unlock the status register. Opcodes sequence sent to SPI flash will bit 50h 01h 00h.
• Set the WSR bit to 1b AND WEWS bit to 1b if write enable (06h) will unlock the status register. Opcodes
sequence sent to SPI flash will bit 06h 01h 00h.
• Set the WSR bit to 0b AND WEWS bit to 0b or 1b, if write enable (06h) will unlock the status register.
Opcodes sequence sent to SPI flash will bit 06h
• WSR or WEWS should be not be set on devices that use non volatile memory for their status
register. Setting this bit will cause operations to be ignored, which may cause undesired operation. Ask
target flash vendor if this is the case for the target flash. See 6.1 Unlocking SPI Flash Device Protection for
356H

Kabylake PCH-LP Platform and 6.2 Locking SPI Flash via Status Register for more information.
358H

Erase Opcode (EO) and Block/Sector Erase Size (BES) should be set based on the flash part and the
firmware on the platform.

Write Granularity (WG) bit should be set based on the capabilities of the flash device. If the flash part is
capable of writing 1 to 64 bytes (or more) with the 02h command you can set this bit 0 or 1. Setting this bit
high will result in faster write performance. If flash part only supports single byte write only, then set this bit
to 0.

Bit ranges 31:16 and 7:5 are reserved and should set to all zeros.

4.4.2 Intel® ME VSCC Table Settings for Kabylake PCH-LP Family Systems
To understand general guidelines for BIOS VSCC settings on different SPI flash devices, please refer to
VSCCommn.bin Content application note (VSCCommn_bin Content.pdf under Flash Image Tool directory).

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Serial Flash Discoverable Parameter (SFDP) Overview

5 Serial Flash Discoverable

Parameter (SFDP) Overview

5.1 Introduction
As the feature set of serial flash progresses, there is an increasing amount of
divergence as individual vendors find different solution to adding new functionality such
as speed and addressing.

These guidelines are a standard that will allow for individual vendors to have their value
add features, but will allow for a controller to discover the attributes needed to operate.

5.2 Discoverable Parameter Opcode and Flash Cycle

The discoverable parameter read opcode behaves like a fast read command. The
opcode is 5Ah and the address cycle is 24 bit long. After the opcode 5Ah is clocked in,
there are 24 bit of address clocked in. There will then be eight clock (8 wait states)
before valid data is clocked out. There is flexibility in the number of wait states, but
they must be byte aligned (multiple of 8 wait states).

SFDP read must update at a frequency between 17 MHz and 48 MHz with a single byte
of wait state.

Figure 5-1. SFDP Read Instruction Sequence

CS#

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

CLK
Dis cov ery 24 Bit W ait Sta te s
O pco de Addre ss

SI 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
Da ta By te
D ata Byte Addr + 1h
Hi gh Z
SO 7 6 5 4 3 2 1 0 7

5.3 Parameter Table Supported on PCH

The flash controller first checks for a valid SFDP header. The value of the major and
minor revision fields in the SFDP header are don’t care. If a valid SFDP header is found,
the controller supports auto discovery of the Component Property Parameter Table
(CPPT).

The following capabilities are only supported on PCH if CPPT is successfully discovered
and parameter values indicate that they are supported. These capabilities are not
supported as default.
• Quad I/O Read
• Quad Output Read

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• Dual I/O read

• Block /Sector Erase size

Note: If SFDP is valid and advertises 4 Kbyte erase capability, then BES is taken from the
SFDP table, otherwise it is taken from the BIOS VCSS table.

PCH will also read the following opcode from parameter table and store to PCH is SFDP
is valid and the following function is supported.
• Erase Opcode
• Dual Output Fast Read Opcode
• Dual I/O Fast Read Opcode
• Quad Output Fast Read Opcode
• Quad I/O Fast Read Opcode

5.4 Detailed JEDEC Specification

Please refer to www.jedec.com JESD216 for detailed SFDP specification on SPI.

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Configuring BIOS/GbE for SPI Flash Access

6 Configuring BIOS/GbE for SPI

Flash Access

6.1 Unlocking SPI Flash Device Protection for

Kabylake PCH-LP Platform
BIOS must account for any built in protection from the flash device itself. BIOS must
ensure that any flash based protection will only apply to BIOS region only. It should not
affect the ME or GbE regions.

All the SPI flash devices that meet the SPI flash requirements in the Kabylake PCH-LP
Family External Design Specification (EDS) will be unlocked by writing a 00h to the SPI
flash’s status register. This command must be done via an atomic software sequencing
to account for differences in flash architecture. Atomic cycles are uninterrupted in that
it does not allow other commands to execute until a read status command returns a
‘not busy’ result from the flash.

Some flash vendors implement their status registers in NVM flash (non-volatile
memory). This takes much more time than a write to volatile memory. During this
write, the flash part will ignore all commands but a read to the status register (opcode
05h). The output of the read status register command will tell the PCH when the
transaction is done.

Recommended flash unlocking sequence:

• Write enable (06h) command will have to be in the prefix opcode configuration
register.
• The “write to status register” opcode (01h) will need to be an opcode menu
configuration option.
• Opcode type for write to status register will be ‘01’: a write cycle type with no
address needed.
• The FDATA0 register should to be programmed to 0000 0000h.
• Data Byte Count (DBC) in Software Sequencing Flash Control register should be
000000b. Errors may occur if any non zero value is here.
• Set the Cycle Opcode Pointer (COP) to the “write to status register” opcode.
• Set to Sequence Prefix Opcode Pointer (SPOP) to Write Enable.
• Set the Data Cycle (DS) to 1.
• Set the Atomic Cycle Sequence (ACS) bit to 1.
• To execute sequence, set the SPI Cycle Go bit to 1.

Please see the Serial Peripheral Interface Memory Mapped Configuration

Registers in the Kabylake PCH-LP Family External Design Specification (EDS) for more
detailed information.

Intel Confidential 41
Configuring BIOS/GbE for SPI Flash Access

6.2 Locking SPI Flash via Status Register

Flash vendors that implement their status register with non-volatile memory can be
updated a limited number of times. This means that this register may wear out before
the desired endurance for the rest of the flash. It is highly recommended that BIOS
vendors and customers do NOT use the SPI flash’s status register to protect the flash in
multiple master systems.

BIOS should try to minimize the number of times that the system is locked and
unlocked.

Care should be taken when using status register based SPI flash protection in multiple
master systems such as Intel® ME FW and/or integrated GbE. BIOS must ensure that
any flash based protection will apply to BIOS region only. It should not affect the ME or
GbE regions.

Please contact your desired flash vendor to see if their status register protection bits
volatile or non-volatile. Flash parts implemented with volatile systems do not have this
concern.

6.3 SPI Protected Range Register Recommendations

The PCH has a mechanism to set up to 5 address ranges from HOST access. These are
defined in PR0, PR1, PR2, PR3 and PR4 in the PCH EDS. These address ranges are NOT
unlocked by assertion of Flash descriptor Override.

It is strongly recommended to use a protected range register to lock down the factory
default portion of Intel® ME FW region. The runtime portion should be left unprotected
as to allow BIOS to update it.

It is strongly recommended that if Flash Descriptor Override strap (which can be

checked by reading FDOPSS (0b Flash Descriptor override is set, 1b not set) in
PCH memory space (SPIBAR+C4h bit 13)) is set, do not set a Protected range to
cover the Intel® ME FW factory defaults. This would allow a flashing of a complete
image when the Flash descriptor Override strap is set.

6.4 Recommendations for Flash Configuration

Lockdown and Vendor Component Lock Bits
6.4.1 Flash Configuration Lockdown
It is strongly recommended that BIOS sets the Host and GbE Flash Configuration
Lock-Down (FLOCKDN) bits (located at SPIBAR + 04h and MBAR +04h respectively)
to ‘1’ on production platforms. If these bits are not set, it is possible to make register
changes that can cause undesired host, integrated GbE and Intel® ME functionality as
well as lead to unauthorized flash region access.

Refer to HSFS— Hardware Sequencing Flash Status Register in the Serial

Peripheral Interface Memory Mapped Configuration Registers section and HSFS—
Hardware Sequencing Flash Status Register in the GbE SPI Flash Programing
Registers section in the Kabylake PCH-LP Family External Design Specification (EDS).

Intel Confidential 42
Configuring BIOS/GbE for SPI Flash Access

6.4.2 Vendor Component Lock

It is strongly recommended that BIOS sets the Vendor Component Lock (VCL) bits.
These bits are located in the BIOS/GbE VSCC0 registers. VCL applies the lock to both
VSCC0 and VSCC1 even if VSCC1 is not used. Without the VCL bits set, it is possible to
make Host/GbE VSCC register(s) changes in that can cause undesired host and
integrated GbE SPI flash functionality.

Refer to VSCC— Vendor Specific Component Capabilities Register in the Kabylake

PCH-LP Family External Design Specification (EDS) for more information.

6.5 Host Vendor Specific Component Control

Registers (VSCC)
VSCC are memory mapped registers are used by the PCH when BIOS or Integrate LAN
reads, programs or erases the SPI flash via Hardware sequencing.

Flash Partition Boundary Address (FBPBA) has been removed and UVSCC and LVSCC
has been replaced with VSCC0 and VSCC1 in Kabylake PCH-LP. VSCC0 is for SPI
component 0 and VSCC1 is for SPI component 1. SPI controller will determine which
VSCC (VCSCC0 or VCSCC1) to be used by comparing Flash Linear Address (FLA) with
size of SPI component 0 (C0DEN). When FLA <= C0DEN then VSCC0 will be used;
whereas FLA > C0DEN then VSCC1 will be used If one SPI flash component used in the
system, VSCC0 needs to be set.

Refer to VSCC— Lower Vendor Specific Component Capabilities Register and in

the Kabylake PCH-LP Family External Design Specification (EDS).

See text below the tables for explanation on how to determine VSCC register values.

Table 6-1. VSCC0 - Vendor-Specific Component Capabilities Register for SPI Component
0 (Sheet 1 of 3)
Bit Description

Component Property Parameter Table Valid (CPPTV) - RO:

This bit is set to a 1 if the Flash Controller detects a valid SFDP Component Property Parameter
Table in SPI Component 0
31 If CPPTV bit is ‘0’, software must configure the VSCC register appropriately. If CPPTV bit is ‘1’, the
corresponding parameter values discovered via SFDP will be used. In most cases, software is not
required to configure the VSCC register. However, if the SFDP table indicates an erase size other
than 4k byte, then the software is required to program the VSCC.EO register with the correct erase
opcode.

30:24 Reserved

Vendor Component Lock (VCL): — RW/L:

'0': The lock bit is not set
'1': The Vendor Component Lock bit is set.

23
This register locks itself when set.

This bit applies to both VSCC0 and VSCC1

All bits locked by (VCL) will remained locked until a global reset.

22:16 Reserved

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Configuring BIOS/GbE for SPI Flash Access

Table 6-1. VSCC0 - Vendor-Specific Component Capabilities Register for SPI Component
0 (Sheet 2 of 3)
Bit Description

Erase Opcode (EO)— RW:

This register is programmed with the Flash erase instruction opcode required by the vendor’s Flash
component. Software must program this register if the SFDP table for this component does not
show 4 kByte erase capability
15:8
This register is locked by the Vendor Component Lock (VCL) bit.

Note: If CPPTV is 1 and the SPDP0 table shows 4k erase capability, the SFDP0 erase code is used
instead of this register

Quad Enable Requirements (QER)

000 = Part does not require a Quad Enable bit to be set, either because Quad is not supported or
because the manufacturer permanently enables Quad capability (e.g. Micron, Numonyx).
001 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to status
register clears all bits in register 2, therefore status register writes MUST be two bytes. If the
status register is unlocked and SFDP bits WSR or VSCC WSR is 1 then SPI controller cannot
use the quad output, quad IO features of this part because the hardware will automatically
write one byte of zeros to status register with every write/erase. (e.g. Winbond, AMIC,
Spansion).
7:5
010 = Part requires bit 6 of status register 1 to be set to enable quad IO. If the status register is
unlocked and SFDP WSR bit or VSCC WSR is 1 then flash controller cannot use the quad out-
put, quad IO features of this part because the hardware will automatically write one byte of
zeros to status register with every write/erase (e.g. Macronix).
011 = Part requires bit 7 of the configuration register to be set to enable Quad (e.g. Atmel).
100 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to the
status register does not clear the second byte (SST/Microchip, Winbond).

Note: This register is locked by the Vendor Component Lock (VCL) bit.

Write Enable on Write Status (WEWS) — RW:

‘0’ = 50h will be the opcode used to unlock the status register on the SPI flash if WSR (bit 3) is set
to 1b.
‘1’ = 06h will be the opcode used to unlock the status register on the SPI flash if WSR (bit 3) is set
4 to 1b.

This register is locked by the Vendor Component Lock (VCL) bit.

Note: Please refer to Table 6-3 for a description of how these bits is used.

Write Status Required (WSR) — RW:

‘0’ = No automatic write of 00h will be made to the SPI flash’s status register.
‘1’ = A write of 00h to the SPI flash’s status register will be sent on EVERY write and erase to the
3 SPI flash performed by Host and GbE.

This register is locked by the Vendor Component Lock (VCL) bit.

Note: Please refer to Table 6-3 for a description of how these bits is used.

Write Granularity (WG) — RW:

0: 1 Byte
1: 64 Byte
This register is locked by the Vendor Component Lock (VCL) bit.

2
Notes:
1. If more than one Flash component exists, this field must be set to the lowest common write
granularity of the different Flash components
2. If using 64 B write, BIOS must ensure that multiple byte writes do not occur over 256 B
boundaries. This will lead to corruption as the write will wrap around the page boundary on
the SPI flash part. This is a feature in page writable SPI flash.

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Configuring BIOS/GbE for SPI Flash Access

Table 6-1. VSCC0 - Vendor-Specific Component Capabilities Register for SPI Component
0 (Sheet 3 of 3)
Bit Description

Block/Sector Erase Size (BES)— RW:

This field identifies the erasable sector size for Flash components.
Valid Bit Settings:
00: 256 Byte
01: 4 KByte
1:0 10: 8 KByte
11: 64 K
This register is locked by the Vendor Component Lock (VCL) bit.
Hardware takes no action based on the value of this register. The contents of this register are to be
used only by software and can be read in the HSFSTS.BERASE register in both the BIOS and the
GbE program registers if FLA is less than FPBA.

Table 6-2. VSCC1 - Vendor Specific Component Capabilities Register for SPI Component 1
(Sheet 1 of 2)
Bit Description

Component Property Parameter Table Valid (CPPTV) - RO:

This bit is set to a 1 if the Flash Controller detects a valid SFDP Component Property Parameter
Table in SPI Component 1
31 If CPPTV bit is ‘0’, software must configure the VSCC register appropriately. If CPPTV bit is ‘1’, the
corresponding parameter values discovered via SFDP will be used. In most cases, software is not
required to configure the VSCC register. However, if the SFDP table indicates an erase size other
than 4k byte, then the software is required to program the VSCC.EO register with the correct erase
opcode.

30:16 Reserved

Erase Opcode (EO)— RW:

This register is programmed with the Flash erase instruction opcode required by the vendor’s Flash
15:8
component.
This register is locked by the Vendor Component Lock (VCL) bit.

Quad Enable Requirements (QER)

000 = Part does not require a Quad Enable bit to be set, either because Quad is not supported or
because the manufacturer permanently enables Quad capability (e.g. Micron, Numonyx).
001 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to status
register clears all bits in register 2, therefore status register writes MUST be two bytes. If the
status register is unlocked and SFDP bits WSR or VSCC WSR is 1 then SPI controller cannot
use the quad output, quad IO features of this part because the hardware will automatically
write one byte of zeros to status register with every write/erase. (e.g. Winbond, AMIC,
Spansion).
7:5
010 = Part requires bit 6 of status register 1 to be set to enable quad IO. If the status register is
unlocked and SFDP WSR bit or VSCC WSR is 1 then flash controller cannot use the quad out-
put, quad IO features of this part because the hardware will automatically write one byte of
zeros to status register with every write/erase (e.g. Macronix).
011 = Part requires bit 7 of the configuration register to be set to enable Quad (e.g. Atmel).
100 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to the
status register does not clear the second byte (SST/Microchip, Winbond).

Note: This register is locked by the Vendor Component Lock (VCL) bit.

Write Enable on Write to Status (WEWS) — RW:

‘0’ = 50h will be the opcode used to unlock the status register if WSR (bit 3) is set to 1b.
‘1’ = 06h will be the opcode used to unlock the status register if WSR (bit 3) is set to 1b.
4

This register is locked by the Vendor Component Lock (VCL) bit.

Please refer to Table 6-3 for a description of how these bits is used.

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Configuring BIOS/GbE for SPI Flash Access

Table 6-2. VSCC1 - Vendor Specific Component Capabilities Register for SPI Component 1
(Sheet 2 of 2)
Bit Description

Write Status Required (WSR) — RW:

‘0’ = No automatic write of 00h will be made to the SPI flash’s status register
‘1’ = A write of 00h to the SPI flash’s status register will be sent on EVERY write and erase to the
3 SPI flash performed by Host and GbE.

This register is locked by the Vendor Component Lock (VCL) bit.

Note: Please refer to Table 6-3 for a description of how these bits is used.

Write Granularity (WG) — RW:

0: 1 Byte
1: 64 Byte

This register is locked by the Vendor Component Lock (VCL) bit.

2
If more than one Flash component exists, this field must be set to the lowest common write
granularity of the different Flash components.
If using 64 B write, BIOS must ensure that multiple byte writes do not occur over 256 B
boundaries. This will lead to corruption as the write will wrap around the page boundary on the SPI
flash part. This is a feature in page writeable SPI flash.

Block/Sector Erase Size (BES)— RW: This field identifies the erasable sector size for all Flash
components.
Valid Bit Settings:
00: 256 Byte
01: 4 KByte
10: 8 KByte
1:0 11: 64 K

This register is locked by the Vendor Component Lock (VCL) bit.

Hardware takes no action based on the value of this register. The contents of this register are to be
used only by software and can be read in the HSFSTS.BERASE register in both the BIOS and the
GbE program registers if FLA is less than FPBA.

Erase Opcode (EO) and Block/Sector Erase Size (BSES) should be set based on
the flash part and the firmware on the platform.
• Either Write Status Required (WSR) or Write Enable on Write Status
(WEWS) should be set on flash devices that require an opcode to enable a write to
the status register. BIOS and GbE will write a 00h to the SPI flash’s status register
to unlock the flash part for every erase/write operation. If this bit is set on a flash
part that has non-volatile bits in the status register then it may lead to pre-mature
wear out of the flash and may result in undesired flash operation. Please refer to
Table 6-3 for a description of how these bits is set and what is the expected
operation from the controller during erase/write operation.

Table 6-3. Description of How WSR and WEWS is Used

WSR WEWS Flash Operation

If the Enable Write Status Register opcode (50h) is needed to unlock the status
1b 0b register. Opcodes sequence sent to SPI flash will bit 50h 01h 00h.

If write enable (06h) will unlock the status register. Opcodes sequence sent to
1b 1b
SPI flash will bit 06h 01h 00h.

Sequence of 60h is sent to unlock the SPI flash on EVERY write and erase that
0b 0 or 1b
Processor or Intel GbE FW performs.

Intel Confidential 46
Configuring BIOS/GbE for SPI Flash Access

Note: WSR or WEWS should be not be set on devices that use non volatile memory
for their status register. Setting this bit will cause operations to be ignored, which
may cause undesired operation. Ask target flash vendor if this is the case for the target
flash. See 6.1 Unlocking SPI Flash Device Protection for Kabylake PCH-LP Platform and
356H

6.2 Locking SPI Flash via Status Register for more information.
358H

Write Granularity (WG) bit should be set based on the capabilities of the flash
device. If the flash part is capable of writing 1 to 64 bytes (or more) with the 02h
command you can set this bit 0 or 1. Setting this bit high will result in faster write
performance. If flash part only supports single byte write only, then set this bit to 0.
Setting this bit high requires that BIOS ensure that no multiple byte write operation
does not cross a 256 Byte page boundary, as it will have unintended results. This is a
feature of page programming capable flash parts.

Vendor Component Lock (VCL) should remain unlocked during development, but
locked in shipping platforms. When VCL and FLOCKDN are set, it is possible that you
may not be able to use in system programming methodologies including Intel Flash
Programming Tool if programmed improperly. It will require a system reset to unlock
this register and BIOS not to set this bits. See 6.4 Recommendations for Flash
354H

Configuration Lockdown and Vendor Component Lock Bits for more details.

All reserved bits should set to zeros.

6.6 Host VSCC Register Settings

To understand general guidelines for VSCC settings with different SPI flash devices,
please refer to VSCCommn.bin content application note (VSCCommn_bin
Content.pdf under Flash Image Tool directory). VSCCommn.bin contains SPI devices
vendor ID, device ID and recommended VSCC values.

§§

Intel Confidential 47
Intel® ME Disable for Debug/Flash Burning Purposes

7 Intel® ME Disable for Debug/

Flash Burning Purposes

This section is purely for debug purposes. Intel® ME FW is the only supported
configuration for Kabylake PCH-LP based system.

7.1 Intel® ME Disable

Here are the ways one can disable the Intel® ME for purposes of in system
programming the flash.
1. HDA_SDO (Manufacturing mode jumper or Flash descriptor override jumper)
asserted HIGH on the rising edge of PWROK. Power off or cold reset. Note: this is
only valid as long as you do not specifically set the variable Flash Descriptor
Override Pin-Strap Ignore in the Flash Image Tool to false.

HECI ME region unlock - There is a HECI command that allows Intel® ME FW to boot up
in a temporarily disabled state and allows for a host program to overwrite the ME
region.

Note: Removing the DIMM from channel 0 no longer has any effect on Intel® ME functionality.

7.1.1 Erasing/Programming Intel® ME Region

If CPU/Host has access to ME region, then one could either erase/program the ME
region to all FFh. If there is no access, then one must assert HDA_SDO (Flash
descriptor override strap) HIGH during the rising edge of PWROK. If there are Protected
Range registers set, then you will not be able to program this w/o a BIOS option to turn
off this protected range. (See 6.3 SPI Protected Range Register Recommendations) for
more detail.

This depends on the board booting HW defaults for clock configuration. If any clock
configuration is required for booting the platform that is not in the HW defaults, then
this option may not work for you.

FPT will automatically disable Intel ME when erasing any address in ME region.

§§

Intel Confidential 48
Recommendations for SPI Flash Programming in Manufacturing Environments

8 Recommendations for SPI Flash

Programming in Manufacturing
Environments

It is recommended that the Intel® ME be disabled when you are programming the ME
region. Intel® ME FW performs regular writes/erases to the ME region. Therefore some
bits may be changed after programming. Please note that not all of these options will
be optimal for your manufacturing process.

Any method of programming SPI flash where the system is not powered will
not result in any interference from Intel® ME FW. The following methods are
for Intel® ME FW:
• Program via In Circuit Test – System is not fully powered here.
• Program via external flash burn-in solution.
• Assert HDA_SDO HIGH (Flash Descriptor Override Jumper) on the rising edge of
PWROK. Note: this is only valid as long as you do not specifically disable this
functionality in fixed offset variable.

§§

Intel Confidential 49
 Flash Descriptor PCH / CPU Configuration Section

9 Flash Descriptor PCH / CPU

Configuration Section

The following section describes functionality and how to set soft strapping for a target platform.
Improper setting of soft straps can lead to undesired operation and may lead to returns/recalls.

9.1 PCH Descriptor Record 0 (Flash Descriptor Records)

Flash Address:FPSBA + 000h

Default Flash Address: 100h

FIT
Offset from 0 Bits Description Usage
Visible

32:23 Reserved, set to ‘0’ No

Intel® Platform Trusted Technology Yes

Supported (Intel® PTT)
22
0 = Intel® PTT Enabled (default)
1 = Intel® PTT Disabled

Intel® Trace Hub - Emergency Mode: This option enables ROM Tracing in the base Yes
platform image.
21 0 = ROM Tracing Emergency mode disabled
(default)
1 = ROM Tracing Emergency mode enabled

Deep Sx Enable (Deep_SX_EN): This requires the target platform to support Yes
Deep Sx state
20 0 = Deep Sx is not supported on the platform
1 = Deep Sx is supported on the platform Note: When configuring Deep Sx you must
(default) also set DEEPSX_PLT_CFG_SS.

Intel® ME Reset Capture on CL_RST#: Notes: Signal CL_RST# is only present on Yes
0x100h (MER_CL): mobile PCH
19
0 = PCH CL_RST# does NOT assert when Intel®
ME performs a reset. (default)
1 = PCH CL_RST# asserts when Intel® ME resets.

18 Reserved, set to ‘0’ No

Direct Connect Interface (DCI) Enabled: Yes

17
0 = DCI Disabled (default)
1 = DCI Enabled

16 Reserved, set to ‘0’ Yes

15:2 Reserved, set to ‘0’ No

Intel® Trace Hub Soft Enable: This soft strap enables ROM based tracing in
the ME.
1 Yes
0 = ROM Tracing Soft Disable (default)
Note: Only applicable if Intel® Trace Hub
1 = ROM Tracing Soft Enable Debug Messages strap is also enabled

Firmware ROM Bypass Enable Softstrap: Firmware ROM Bypass Enable Softstrap. Yes
0x100h
0
(Cont) 0 = ROM Bypass disabled (default)
1 = ROM Bypass enabled

Intel Confidential 50
 Flash Descriptor PCH / CPU Configuration Section

9.2 PCH Descriptor Record 1 (Flash Descriptor Records)

Flash Address:FPSBA + 004h

Default Flash Address: 104h

FIT
Offset from 0 Bits Description Usage
Visible

SMBus / SMLink TCO Slave Connection: See: Kabylake Platform Controller Hub Yes
0 = TCO Slave connected to Intel® ME SMBus (PCH-LP) EDS for more details.
0x104h 0 (default)
1 = TCO Slave connected to Intel® ME SMBus and
SMLink0

9.3 PCH Descriptor Record 2 (Flash Descriptor Records)

Flash Address:FPSBA + 005h

Default Flash Address: 105h

FIT
Offset from 0 Bits Description Usage
Visible

Intel® ME SMBus Enable: No

0x105h 0
This bit must always be set to 1.

9.4 PCH Descriptor Record 3 (Flash Descriptor Records)

Flash Address:FPSBA + 006h

Default Flash Address: 106h

FIT
Offset from 0 Bits Description Usage
Visible

0x106h 7:0 Reserved, set to ‘0’ No

9.5 PCH Descriptor Record 4 (Flash Descriptor Records)

Flash Address:FPSBA + 007h

Default Flash Address: 107h

FIT
Offset from 0 Bits Description Usage
Visible

Intel® ME SMBus I2C Address (MESMI2CA): This address is only used by Intel® ME FW for Yes
Defines 7 bit Intel ME SMBus I2C target address testing purposes. If MESMI2CEN (Offset
0x10A
0x107h 6:0
Default set to ‘0’ bit 0) is set to 1 then the address used in this
field must be non-zero and not conflict with any
Note: This field is only used for testing purposes. other devices on the segment.

51 Intel Confidential
 Flash Descriptor PCH / CPU Configuration Section

9.6 PCH Descriptor Record 5 (Flash Descriptor Records)

Flash Address:FPSBA + 008h

Default Flash Address: 108h

FIT
Offset from 0 Bits Description Usage
Visible

Intel® ME SMBus ASD Address (MESMASDA): If MESMASDEN(PCH Descriptor Record 8 Yes

bit 0) is set to’1’ there must be a valid address
Intel® ME SMBus Controller ASD Target Address. for ASD. The address must be determined by
ASD: Alert Sending Device the BIOS developer based on the requirements
below.
Default set to ‘0’ A valid address must be:
• Non-zero value
0x108h 6:0
Note: This field is only applicable if there is an • Must be a unique address on the Host
ASD attached to SMBus and using Intel® SMBus segment
AMT • Be compatible with the master on SMBus -
For example, if the ASD address the
master that needs write thermal
information to an address "xy"h. Then this
field must be set to xy"h.

9.7 PCH Descriptor Record 6 (Flash Descriptor Records)

Flash Address:FPSBA + 009h

Default Flash Address: 109h

FIT
Offset from 0 Bits Description Usage
Visible

Intel® ME SMBus MCTP Address If MESMMCTPAEN (PCHSTRP3 bit 8) is set Yes

(MESMMCTPA): to 1 then the address used in this field must be
Defines 7 bit Intel ME SMBus MCTP target address non-zero and not conflict with any other
devices on the segment.
0x109h 6:0
Default set to ‘0’

Note: This field is only used for testing

purposes.

9.8 PCH Descriptor Record 7 (Flash Descriptor Records)

Flash Address:FPSBA + 00Ah

Default Flash Address: 10Ah

FIT
Offset from 0 Bits Description Usage
Visible

Intel® ME SMBus I2C Address Enable This field should only be set to ’1’ for testing Yes
(MESMI2CEN): purposes

0 = Intel® ME SMBus I2C Address is disabled

0x10Ah 0 (default)
1 = Intel® ME SMBus I2C Address is enabled

Note: This field is only used for testing

purposes.

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 Flash Descriptor PCH / CPU Configuration Section

9.9 PCH Descriptor Record 8 (Flash Descriptor Records)

Flash Address:FPSBA + 00Bh

Default Flash Address: 10Bh

FIT
Offset from 0 Bits Description Usage
Visible

Intel® ME SMBus ASD Address Enable This bit must only be set to ’1’ when there is an Yes
(MESMASDEN): ASD (Alert Sending Device) attached to Host
SMBus. This is only applicable in platforms
0 = Intel® ME SMBus ASD Address is disabled using Intel® AMT.
(default)
0x10Bh 0 Note: This setting is not the same for all
1 = Intel® ME SMBus ASD Address is enabled
designs, is dependent on the board
Note: This field is only applicable if there is an design. The setting of this field must
ASD attached to SMBus and using Intel® be determined by the BIOS developer
AMT and the platform hardware designer.

9.10 PCH Descriptor Record 9 (Flash Descriptor Records)

Flash Address:FPSBA + 00Ch

Default Flash Address: 10Ch

FIT
Offset from 0 Bits Description Usage
Visible

Intel® ME SMBus MCTP Address Enable Yes

(MESMMCTPA):
0 = Intel ME SMBus MCTP Address is disabled
(default)
0x10Ch 0
1 = Intel ME SMBus MCTP Address is enabled

Note: This field is only used for testing

purposes.

9.11 PCH Descriptor Record 10 (Flash Descriptor Records)

Flash Address:FPSBA + 00Dh Size: 8 bit Default value: 00h

Default Flash Address: 10Dh

FIT
Offset from 0 Bits Description Usage
Visible

0x10Dh 0 Reserved, set to ‘0’ No

53 Intel Confidential
 Flash Descriptor PCH / CPU Configuration Section

9.12 PCH Descriptor Record 11 (Flash Descriptor Records)

Flash Address:FPSBA + 00Eh

Default Flash Address: 10Eh

FIT
Offset from 0 Bits Description Usage
Visible

Intel® ME SMBus Subsystem Vendor ID for Yes

ASF (MESMA2UDID):
MESMAUDID[15:0] - Subsystem Vendor ID

The values contained in MESMAUDID[15:0] is

0x10Eh 15:0 provided as bytes 10-11 of the data payload to an
external master when it initiates a Directed GET
UDID Block Read Command to the Alert Sending
Device ASD's address.

Default set to ‘0x0000’

Intel® ME SMBus Subsystem Device ID for Yes

ASF (MESMA2UDID):
MESMAUDID[31:16] - Subsystem Device ID

The values contained in MESMAUDID[31:16] is

0x110h 15:0 provided as bytes 8-9 of the data payload to an
external master when it initiates a Directed GET
UDID Block Read Command to the Alert Sending
Device ASD's address.

Default set to ‘0’

9.13 PCH Descriptor Record 12 (Flash Descriptor Records)

Flash Address:FPSBA + 012h

Default Flash Address: 112h

FIT
Offset from 0 Bits Description Usage
Visible

0x112h 15:0 Reserved, set to ‘0’ No

9.14 PCH Descriptor Record 13 (Flash Descriptor Records)

Flash Address:FPSBA + 016h

Default Flash Address: 116h

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Intel® ME SMBus Frequency (SMB0FRQ): Intel® ME SMBus No

The value of these bits determine the physical bus
0x116h 1:0 speed supported by the HW.

Set to ‘0x1’

Intel Confidential 54
 Flash Descriptor PCH / CPU Configuration Section

9.15 PCH Descriptor Record 14 (Flash Descriptor Records)

Flash Address:FPSBA + 018h

Default Flash Address: 118h

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0x118h 0 Reserved, set to ‘0’ No

9.16 PCH Descriptor Record 15 (Flash Descriptor Records)

Flash Address:FPSBA + 019h

Default Flash Address: 119h

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SMLink0 Enable (SML0_EN): This bit MUST be set to ’1’ when Intel NFC Yes
Configures if SMLink0 segment is enabled enabled on the platform.

0 = Disabled The Intel PHY SMBus controller must be routed

1 = Enabled (default) to this SMLink 0 Segment.

Notes: If not using Intel NFC solution or if disabling it,

1. This bit MUST be set to ‘1’ when utilizing then this segment must be disabled (set to '0').
0x119h 0
integrated LAN controller.
2. This bit MUST be set to ’1’ when utilizing NFC Note: This setting is not the same for all
enabled on the platform. designs, is dependent on the board
3. The SMBus TCO Slave controller must be design. The setting of this field must
routed to this SMLink 0 Segment. be determined by the BIOS developer
4. This segment should be set to 0 in one of the and the platform hardware designer.
following cases:
a. Not using Intel NFC solution
b. Disabled by the user.

9.17 PCH Descriptor Record 16 (Flash Descriptor Records)

Flash Address:FPSBA + 01Ah

Default Flash Address: 11Ah

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0x11Ah 7:0 Reserved, set to ‘0’ No

9.18 PCH Descriptor Record 17 (Flash Descriptor Records)

Flash Address:FPSBA + 01Bh

Default Flash Address: 11Bh

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0x11Bh 7:0 Reserved, set to ‘0’ No

55 Intel Confidential
 Flash Descriptor PCH / CPU Configuration Section

9.19 PCH Descriptor Record 18 (Flash Descriptor Records)

Flash Address:FPSBA + 01Ch

Default Flash Address: 11Ch

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0x11Ch 15:0 Reserved, set to ‘0’ No

9.20 PCH Descriptor Record 19 (Flash Descriptor Records)

Flash Address:FPSBA + 020h

Default Flash Address: 120h

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0x120h 0 Reserved, set to ‘0’ No

9.21 PCH Descriptor Record 20 (Flash Descriptor Records)

Flash Address:FPSBA + 021h

Default Flash Address: 121h

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0x121h 0 Reserved, set to ‘0’ No

9.22 PCH Descriptor Record 21 (Flash Descriptor Records)

Flash Address:FPSBA + 022h

Default Flash Address: 122h

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0x122h 31:0 Reserved, set to ‘0’ No

9.23 PCH Descriptor Record 22 (Flash Descriptor Records)

Flash Address:FPSBA + 026h

Default Flash Address: 126h

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0x126h 31:0 Reserved, set to ‘0’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.24 PCH Descriptor Record 23 (Flash Descriptor Records)

Flash Address:FPSBA + 02Ah

Default Flash Address: 12Ah

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SMLink0 Frequency (SML0FRQ): Speed is dependent on board topology and Yes

These bits determine the physical bus speed layout.
supported by the HW.
0x12Ah 1:0
00 = Reserved
01 = Standard Mode - up to 100 kHz
10 = Fast Mode - up to 400 kHz
11 = Fast Mode Plus - up to 1 MHz (default)

9.25 PCH Descriptor Record 24 (Flash Descriptor Records)

Flash Address:FPSBA + 02Ch

Default Flash Address: 12Ch

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0x12Ch 0 Reserved, set to ‘0’ No

9.26 PCH Descriptor Record 25 (Flash Descriptor Records)

Flash Address:FPSBA + 02Dh

Default Flash Address: 12Dh

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SMLink1 Enable (SML1_EN): This bit must be set to ’1’ if using the PCH's Yes
Configures if SMLink1 segment is enabled Thermal reporting. If setting this bit to ’0’,
there must be an external solution that gathers
temperature information from PCH and
0 = Disabled processor.
0x12Dh 0 1 = Enabled (default)
Note: This setting is not the same for all
Note: This must be set to ’1’ platforms that use designs, is dependent on the board
PCH SMBus based thermal reporting. design. The setting of this field must
be determined by the BIOS developer
and the platform hardware designer.

57 Intel Confidential
 Flash Descriptor PCH / CPU Configuration Section

9.27 PCH Descriptor Record 26 (Flash Descriptor Records)

Flash Address:FPSBA + 02Eh

Default Flash Address: 12Eh

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SMLink1 GP Target Address (SML1GPA): When SML1GPAEN =’1’, there needs to be a Yes
SMLink1 controller General Purpose Target valid GP address in this field. This address used
Address (7:1) here is design specific. The BIOS developer and
/ or platform hardware designer must supply
Notes: an address with the criteria below.
1. This field is not active unless SML1GPAEN is
set to ’1’. A valid address must be:
7:1 2. This address MUST be set if there is a device
on the SMLink1 segment that will use SMBus • Non-zero value
based PCH thermal reporting. • Must be a unique address on the SMLink1
3. If SML1GPAEN =’1’ then this field must be a segment
valid 7 bit, non-zero address that does not • Be compatible with the master on SMLink1
conflict with any other devices on SMLink1 - For example if the GP address the master
segment. that needs read thermal information from
a certain address, then this filed must be
Default set to ‘0’ set accordingly.
0x12Eh
SMLink1 GP Target Address Enable This bit must be set in cases where SMLink1 Yes
(SML1GPAEN): has a master that requires SMBus based
Thermal Reporting that is supplied by the PCH.
SMLink1 controller General Purpose Target Some examples of this master could be an
Address Enable Embedded Controller, a BMC, or any other
SMBus Capable device that needs Processor or
PCH temperature information. If no master on
0 = SMLink1 GP Address is disabled (default)
0 the SMLink1 segment is capable of utilizing
1 = SMLink1 GP Address is enabled
thermal reporting, then this field must be set to
’0’.

This bit MUST set to ’1’ if there is a device on the Note: This setting is not the same for all
SMLink1 segment that will use SMBus based PCH designs, is dependent on the board
thermal reporting. design. The setting of this field must
This bit MUST be set to ’0’ if PCH thermal be determined by the BIOS developer
reporting is not used. and the platform hardware designer.

9.28 PCH Descriptor Record 27 (Flash Descriptor Records)

Flash Address:FPSBA + 02Fh

Default Flash Address: 12Fh

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SMLink1 I2C* Target Address (SML1I2CA): When SML1I2CAEN(PCHSTRP11 bit 24) Yes
=’1’, there needs to be a valid I2C address in
Defines the 7 bit I2C target address for PCH this field. This address used here is design
Thermal Reporting on SMLink1. specific.
The BIOS developer and/or platform hardware
Notes: designer must supply an address with the
1. This field is not active unless SML1I2CAEN is criteria below.
set to ’1’.
2. This address MUST be set if there is a device A valid address must be:
0x12Fh 6:0 on the SMLink1 segment that will use
thermal reporting supplied by PCH. • Non-zero value
3. If SML1I2CAEN =’1’ then this field must be a • Must be a unique address on the SMLink1
valid 7 bit, non-zero address that does not segment
conflict with any other devices on SMLink1 • Be compatible with the master on SMLink1
segment. - For example, if the I2C address the
4. This address can be different for every master that needs write thermal
design, ensure BIOS developer supplies the information to a address "xy"h. Then this
address. filed must be to "xy"h.

Default set to ‘0’

Intel Confidential 58
 Flash Descriptor PCH / CPU Configuration Section

9.29 PCH Descriptor Record 28 (Flash Descriptor Records)

Flash Address:FPSBA + 030h

Default Flash Address: 130h

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0x130h 6:0 Reserved, set to ‘0’ No

9.30 PCH Descriptor Record 29 (Flash Descriptor Records)

Flash Address:FPSBA + 031h

Default Flash Address: 131h

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0x131h 6:0 Reserved, set to ‘0’ No

9.31 PCH Descriptor Record 30 (Flash Descriptor Records)

Flash Address:FPSBA + 032h

Default Flash Address: 132h

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SMLink1 I2C Target Address Enable This bit must be set in cases where SMLink1 Yes
(SML1I2CAEN): has a master that requires SMBus based
Thermal Reporting that is supplied by the PCH.
0 = SMLink1 I2C Address is disabled (default) Some examples of this master could be an
1 = SMLink1 I2C Address is enabled Embedded Controller, a BMC, or any other
SMBus Capable device that needs Processor
and/or PCH temperature information. If no
Notes:
0x132h 0 1. This bit MUST set to ’1’ if there is a device on master on the SMLink1 segment is capable of
the SMLink1 segment that will use PCH utilizing thermal reporting, then this field must
thermal reporting. be set to ’0’.
2. This bit MUST be set to ’0’ if PCH thermal
reporting is not used. Note: This setting is not the same for all
designs, is dependent on the board
design. The setting of this field must
be determined by the BIOS developer
and the platform hardware designer.

9.32 PCH Descriptor Record 31 (Flash Descriptor Records)

Flash Address:FPSBA + 033h

Default Flash Address: 133h

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0x133h 0 Reserved, set to ‘0’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.33 PCH Descriptor Record 32 (Flash Descriptor Records)

Flash Address:FPSBA + 034h

Default Flash Address: 134h

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0x134h 0 Reserved, to ‘0’ No

9.34 PCH Descriptor Record 33 (Flash Descriptor Records)

Flash Address:FPSBA + 035h

Default Flash Address: 135h

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0x135h 0 Reserved, set to ‘0’ No

9.35 PCH Descriptor Record 34 (Flash Descriptor Records)

Flash Address:FPSBA + 036h

Default Flash Address: 136h

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0x136h 31:0 Reserved, set to ‘0’ No

9.36 PCH Descriptor Record 35 (Flash Descriptor Records)

Flash Address:FPSBA + 03Ah

Default Flash Address: 13Ah

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0x13Ah 15:0 Reserved, set to ‘0’ No

9.37 PCH Descriptor Record 36 (Flash Descriptor Records)

Flash Address:FPSBA + 03Eh

Default Flash Address: 13Eh

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SMLink1 Frequency (SML1FRQ) Frequency Yes

00 = Reserved
0x13Eh 1:0
01 = Standard Mode - up to 100 kHz (default)
10 = Fast Mode - up to 400 kHz
11 = Fast Mode Plus - up to 1 MHz

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 Flash Descriptor PCH / CPU Configuration Section

9.38 PCH Descriptor Record 37 (Flash Descriptor Records)

Flash Address:FPSBA + 040h

Default Flash Address: 140h

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0x140h 0 Reserved, set to ‘0’ No

9.39 PCH Descriptor Record 38 (Flash Descriptor Records)

Flash Address:FPSBA + 041h

Default Flash Address: 141h

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GbE MAC SMBus Address: This is the Intel integrated wired MAC’s SMBus Yes
This is the 7 bit SMBus address to accept SMBus address.
cycles from the PHY.
This field must be programmed to 70h.
This field must be programmed to 70h.
0x144h 6:0
GbE PHY SMBus Address and GbE MAC address
have to be programmed to 64h and 70h in
order to ensure proper arbitration of SMBus
communication between the Intel integrated
MAC and PHY.

9.40 PCH Descriptor Record 39 (Flash Descriptor Records)

Flash Address:FPSBA + 045h

Default Flash Address: 145h

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0x145h 6:0 Reserved, set to ‘0’ No

9.41 PCH Descriptor Record 40 (Flash Descriptor Records)

Flash Address:FPSBA + 046h

Default Flash Address: 146h

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0x146h 0 Reserved, set to ‘0’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.42 PCH Descriptor Record 41 (Flash Descriptor Records)

Flash Address:FPSBA + 047h

Default Flash Address: 147h

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Gbe MAC SMBus Address Enable This bit must be set to ’1’ if Intel integrated Yes
(GBEMAC_SMBUS_ADDR_EN): wired LAN solution is used. If not using, or if
0 = Disabled disabling Intel integrated wired LAN solution,
1 = Enabled (default) then this field must be set to ’0’.

0x147h 0 Notes:
1.This bit MUST be set to ’1’ when utilizing Intel
integrated wired LAN.
2.If not using Intel integrated wired LAN solution
or if disabling it, then this segment must be set to
'0'.

9.43 PCH Descriptor Record 42 (Flash Descriptor Records)

Flash Address:FPSBA + 048h

Default Flash Address: 148h

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0x148h 1:0 Reserved, set to ‘0x3’ No

9.44 PCH Descriptor Record 43 (Flash Descriptor Records)

Flash Address:FPSBA + 049h

Default Flash Address: 149h

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0x149h 2:0 Reserved, set to ‘0x2’ No

9.45 PCH Descriptor Record 44 (Flash Descriptor Records)

Flash Address:FPSBA + 04Ch

Default Flash Address: 14Ch

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GbE PHY SMBus Address: This is the Intel PHY’s SMBus address. Yes
This is the 7 bit SMBus address the PHY uses to This field must be programmed to 64h.
accept SMBus cycles from the MAC.
0x14Ch 6:0 GbE PHY SMBus Address and GbE MAC address
This field must be programmed to 64h. have to be programmed to 64h and 70h in
order to ensure proper arbitration of SMBus
communication between the Intel integrated
MAC and PHY.

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 Flash Descriptor PCH / CPU Configuration Section

9.46 PCH Descriptor Record 45 (Flash Descriptor Records)

Flash Address:FPSBA + 04Dh Size: 8 bit Default value: 00h

Default Flash Address: 14Dh

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0x14Dh 6:0 Reserved, set to ‘0’ No

9.47 PCH Descriptor Record 46 (Flash Descriptor Records)

Flash Address:FPSBA + 04Eh

Default Flash Address: 14Eh

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0x14Eh 0 Reserved, set to ‘0’ No

9.48 PCH Descriptor Record 47 (Flash Descriptor Records)

Flash Address:FPSBA + 04Fh

Default Flash Address: 14Fh

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0x14Fh 0 Reserved, set to ‘0’ No

9.49 PCH Descriptor Record 48 (Flash Descriptor Records)

Flash Address:FPSBA + 050h

Default Flash Address: 150h

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0x150h 1:0 Reserved, set to ‘0’ No

9.50 PCH Descriptor Record 49 (Flash Descriptor Records)

Flash Address:FPSBA + 051h

Default Flash Address: 151h

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0x151h 2:0 Reserved, set to ‘0’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.51 PCH Descriptor Record 50 (Flash Descriptor Records)

Flash Address:FPSBA + 054h

Default Flash Address: 154h

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7:6 Reserved, set to ‘0’ No

®
Intel RST for PCIe-C3 Select x2 or x4: This is used to configure the platform for the Yes
Intel® RST for PCIe interface to either x2 or x4
lane operation on PCIe Controller 3 (Port 9-
00 = Reserved 12).
01 = Intel® RST for PCIe-C3 configured for x2
5:4
(default) Note:
10 = Intel® RST for PCIe-C3 configured for x4 1. Only 2 concurrent SATA Express devices
11 = Reserved supported for Kabylake-LP
0x154h
Intel® RST for PCIe-C2 Select x2 or x4: This is used to configure the platform for the Yes
Intel® RST for PCIe interface to either x2 or x4
lane operation on PCIe Controller 2 (Port 5-
00 = Reserved 8).
3:2 01 = Intel® RST for PCIe-C2 configured for x2
(default) Note:
10 = Intel® RST for PCIe-C2 configured for x4 1. Only 2 concurrent SATA Express devices
11 = Reserved supported for Kabylake-LP.

1:0 Reserved, set to ‘0x1’ No

9.52 PCH Descriptor Record 51 (Flash Descriptor Records)

Flash Address:FPSBA + 055h

Default Flash Address: 155h

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5:4 Intel® RST for PCIe Ctrl 3 Strap: This is used to configure the platform for the No
00 = Reserved Intel® RST for PCIe interface to either x2 or x4
lane operation on PCIe Controller 3 (Port 9-
01 = Reserved 12).
10 = 2x2 (default)
11 = 1x4 Note:
1. Only 3 concurrent SATA Express devices
supported for Kabylake-H.
2. When enabling the Intel® RST for PCIe
interface this setting must match the port
configuration PCIe Controller 3 (Port 9-
12) and Intel® RST for PCIe Controller
3.

3:2 Intel® RST for PCIe Ctrl 2 Strap: This is used to configure the platform for the No
00 = Reserved Intel® RST for PCIe interface to either x2 or x4
lane operation on PCIe Controller 2 (Port 5-
01 = Reserved 8).
10 = 2x2 (default)
11 = 1x4 Note:
1. Only 3 concurrent SATA Express devices
supported for Kabylake-H
2. When enabling the Intel® RST for PCIe
interface this setting must match the port
configuration PCIe Controller 2 (Port 5-
8) and Intel® RST for PCIe Controller
2.

0x155h 1:0 Reserved, set to ‘0x2’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.53 PCH Descriptor Record 52 (Flash Descriptor Records)

Flash Address:FPSBA + 058h

Default Flash Address: 158h

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Visible

5:2 Reserved, set to ‘0’ No

0x158h
1:0 Reserved, set to ‘0x2’ No

9.54 PCH Descriptor Record 53 (Flash Descriptor Records)

Flash Address:FPSBA + 05Ch

Default Flash Address: 15Ch

FIT
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Visible

5:4 Reserved, set to ‘0’ No

Intel® RST for PCIe Controller 2: This is used to configure the platform for the Yes
00 = Reserved Intel® RST for PCIe interface to either x2 or x4
lane operation on PCIe Controller 2 (Port 5-
01 = Reserved 8).
10 = 2x2 (default)
11 = 1x4 Note:
1. Only 2 concurrent SATA Express devices
0x15Ch 3:2 supported for Kabylake-LP.
2. The x1 is required to meet PCIe
specification requirement but is not a
supported SATA Express configuration.
3. When enabling the Intel® RST for PCIe
interface this setting must match the port
configuration PCIe Controller 2 (Port 5-
8) and Intel® RST for PCIe Controller
2.

1:0 Reserved, set to ‘0’ No

65 Intel Confidential
 Flash Descriptor PCH / CPU Configuration Section

9.55 PCH Descriptor Record 54 (Flash Descriptor Records)

Flash Address:FPSBA + 060h

Default Flash Address: 160h

FIT
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Visible

Intel® RST for PCIe Controller 3: This is used to configure the platform for the Yes
00 = Reserved Intel® RST for PCIe interface to either x2 or x4
lane operation on PCIe Controller 3 (Port 9-
01 = Reserved 12).
10 = 2x2 (default)
11 = 1x4 Note:
1. Only 2 concurrent SATA Express devices
supported for Kabylake-LP.
5:4 2. The x1 is required to meet PCIe
specification requirement but is not a
0x160h supported SATA Express configuration.
3. When enabling the Intel® RST for PCIe
interface this setting must match the port
configuration PCIe Controller 3 (Port 9-
12) and Intel® RST for PCIe Controller
3.
4. Kabylake-Y only supports x2 mode
configuration on this controller.

3:2 Reserved, set to ‘0’ No

1:0 Reserved, set to ‘0’ No

Intel Confidential 66
 Flash Descriptor PCH / CPU Configuration Section

9.56 PCH Descriptor Record 55 (Flash Descriptor Records)

Flash Address:FPSBA + 064h

Default Flash Address: 164h

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LAN PHY Power Control GPD11 Signal LAN PHY Power Control: LANPHYPC should Yes
Configuration: be connected to LAN_DISABLE_N on the PHY.
PCH will drive LANPHYPC. low to put the PHY
into a low power state when functionality is not
00 = Use as GPD11
needed.
7:6 01 = Use as LANPHYPC (default)
Note:
LANPHYPC can only be driven low if SLP_LAN# is
deasserted.
Signal can instead be used as GPD11.

SLP_WLAN# / GPD9 Signal Configuration: WLAN Sub-System Sleep Control: When Yes
SLP_WLAN# is de-asserted it indicates that the
PHY device must be powered. When
0 = Use as SLP_WLAN# (default)
5 SLP_WLAN# is asserted, power can be shut off
1 = Use as GPD9 to the PHY device. SLP_WLAN# will always be
deasserted in S0 and
0x164h anytime SLP_A# is de-asserted.

4:3 Reserved, set to ‘0’ No

SLP_A# / GPD6 Signal Configuration: Yes

2 0 = Use as SLP_A# (default)
1 = Use as GPD6

SLP_S4# / GPD5 Signal Configuration: Yes

1
0 = Use as SLP_S4# (default)
1 = Use as GPD5

SLP_S3# / GPD4 Signal Configuration: Yes

0
0 = Use as SLP_S3# (default)
1 = Use as GPD4

9.57 PCH Descriptor Record 56 (Flash Descriptor Records)

Flash Address:FPSBA + 065h

Default Flash Address: 165h

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SLP_S5# / GDP10 Signal Configuration: Yes

0x165h 0 0 = Use as SLP_S5# (default)
1 = Use as GPD10

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 Flash Descriptor PCH / CPU Configuration Section

9.58 PCH Descriptor Record 57 (Flash Descriptor Records)

Flash Address:FPSBA + 068h

Default Flash Address: 168h

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SATA / PCIe GP Select for Port 2 This strap must also be configured when No
(SATA_PCIE_GP2): setting the PCIe/SATA Combo Port 3 Strap
(PCIE_SATA_P3_Flex)
00 = PCIe Port 12 is statically assigned to SATA
Port 2 Note: This strap and the PCIe/SATA Combo
01 = PCIe Port 12 is statically assigned to PCIe (or Port 3 Strap (PCIE_SATA_P3_Flex) and
GbE) (default) (SATA_PCIE_GP2) must match for proper
5:4 port function.
10 = Reserved
11 = Assigned based on the polarity for
Note: For unused SATA/PCIe* Combo Lanes,
SATAXPCIE2
Flex I/O Lanes that can be configured
as PCIe* or SATA, the lanes must be
statically assigned to SATA or PCIe*.
These unused SATA/PCIe* Combo
Lanes must not be assigned as polarity
based.

SATA / PCIe GP Select for Port 1 This strap must also be configured when No
(SATA_PCIE_GP1): setting the PCIe/SATA Combo Port 1 Strap
(PCIE_SATA_P1_Flex) or PCIe/SATA Combo
Port 2 Strap (PCIE_SATA_P2_Flex).
00 = PCIe Port 8 / PCIe Port 11 is statically
assigned to SATA Port 1 Note: This strap and the PCIe/SATA Combo
01 = PCIe Port 8 / PCIe Port 11 is statically Port 1 Strap (PCIE_SATA_P1_Flex) or PCIe/
assigned to PCIe (or GbE) SATA Combo Port 2 Strap
(PCIE_SATA_P2_Flex) and
10 = Reserved (SATA_PCIE_SP1) must match for proper
0x168h 3:2
11 = Assigned based on the polarity for port function.
SATAXPCIE1 (default)
Note: For unused SATA/PCIe* Combo Lanes,
Flex I/O Lanes that can be configured
as PCIe* or SATA, the lanes must be
statically assigned to SATA or PCIe*.
These unused SATA/PCIe* Combo
Lanes must not be assigned as polarity
based.

SATA / PCIe GP Select for Port 0 This strap must also be configured when No
(SATA_PCIE_GP0): setting the PCIe/SATA Combo Port 0 strap
(PCIE_SATA_P0_Flex).
00 = PCIe Port 7 is statically assigned to SATA
Port 0 (default) Note: This strap and the PCIe/SATA Combo
01 = PCIe Port 7 is statically assigned to PCIe (or Port 0 strap (PCIE_SATA_P0_Flex) and
GbE) (SATA_PCIE_SP0) must match for proper
1:0 port function.
10 = Reserved
11 = Assigned based on the polarity for
Note: For unused SATA/PCIe* Combo Lanes,
SATAXPCIE0
Flex I/O Lanes that can be configured
as PCIe* or SATA, the lanes must be
statically assigned to SATA or PCIe*.
These unused SATA/PCIe* Combo
Lanes must not be assigned as polarity
based.

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 Flash Descriptor PCH / CPU Configuration Section

9.59 PCH Descriptor Record 58 (Flash Descriptor Records)

Flash Address:FPSBA + 06Ch

Default Flash Address: 16Ch

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7:5 Reserved, set to ‘0’ No

USB3/ SSIC Combo Port 1 Configuration This strap must also be configured when No
(USB3_SSIC_P1_STRP) setting the USB3 / SSIC Combo Port 1 strap
(USB3_SSIC_P1_Flex).
0 = Statically assigned to USB3 (default)
1 = Statically assigned to SSIC
0x16Ch 4 Note: This strap and the USB3 / SSIC Combo
Port 1 strap (USB3_SSIC_P1_Flex) must
match forproper port function.

3:0 Reserved, set to ‘0’ No

9.60 PCH Descriptor Record 59 (Flash Descriptor Records)

Flash Address:FPSBA + 06Dh

Default Flash Address: 16Dh

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0x16Dh 7:0 Reserved, set to ‘0’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.61 PCH Descriptor Record 60 (Flash Descriptor Records)

Flash Address:FPSBA + 06Eh

Default Flash Address: 16Eh

FIT
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7:6 Reserved, set to ‘0’ No

5:4 Reserved, set to ‘0’ No

USB3 / PCIe Combo Port 1 Strap

(PCIE_USB3_P1_STRP) This strap must also be configured when
setting the USB3 / PCIe Combo Port 1 strap
00 = Statically assigned to USB3 (default prior to
(PCIE_USB3_P1_Flex).
strap pull)
3:2 No
01 = Statically assigned to PCI Express (or GbE)
Note: This strap and the USB3 / PCIe Combo
(default)
Port 1 strap (PCIE_USB3_P1_Flex) must
0x16Eh 10 = Reserved match forproper port function.
11 = Reserved

USB3 / PCIe Combo Port 0 Strap

(PCIE_USB3_P0_STRP) This strap must also be configured when
setting the USB3 / PCIe Combo Port 0 strap
00 = Statically assigned to USB3 (default prior to
(PCIE_USB3_P0_Flex).
strap pull)
1:0 No
01 = Statically assigned to PCI Express (or GbE)
Note: This strap and the USB3 / PCIe Combo
(default)
Port 0 strap (PCIE_USB3_P0_Flex) must
10 = Reserved match forproper port function.
11 = Reserved

9.62 PCH Descriptor Record 61 (Flash Descriptor Records)

Flash Address:FPSBA + 070h

Default Flash Address: 170h

FIT
Offset from 0 Bits Description Usage
Visible

0x170h 31:0 Reserved, set to ‘0’ No

9.63 PCH Descriptor Record 62 (Flash Descriptor Records)

Flash Address:FPSBA + 074h Size: 8 bit Default value: 0Eh

Default Flash Address: 174h

FIT
Offset from 0 Bits Description Usage
Visible

3:1 Reserved, set to ‘111b’ No

0x174h
0 Reserved, set to ‘0’ No

Intel Confidential 70
 Flash Descriptor PCH / CPU Configuration Section

9.64 PCH Descriptor Record 63 (Flash Descriptor Records)

Flash Address:FPSBA + 078h

Default Flash Address: 178h

FIT
Offset from 0 Bits Description Usage
Visible

BIOS Guard protections override enable. This setting allows BIOS Guard to bypass the Yes
SPI Flash controller protections such as
protected range registers and top swap.
0 = BIOS Guard Fault Tolerant Update Capability
1 is disabled (default)
Note: For detail please review Intel®
1 = BIOS guard Fault Tolerant Update Capability
Platform Protection Technology with
0x178h is enabled
BIOS Guard 2.0 BIOS Specification
regarding Fault Tolerant Update (FTU)

TPM Over SPI Bus Enable (TOS): Yes

0 0 = TPM is not on SPI (default)
1 = TPM is on SPI

9.65 PCH Descriptor Record 64 (Flash Descriptor Records)

Flash Address:FPSBA + 07Ch

Default Flash Address: 17Ch

FIT
Offset from 0 Bits Description Usage
Visible

7 Reserved, set to ‘0’ No

® ®
Intel PHY Over PCIe Enable This bit MUST be set to ’1’ if using Intel Yes
(PHY_PCIE_EN): integrated wired LAN solution.
If not using, or if disabling Intel® integrated
0 = Intel integrated wired MAC/PHY wired LAN solution then set this to ’0’.
communication is not enabled over PCI Express*.
6 1 = The PCI Express* port selected by the
PHY_PCIEPORT_SEL soft strap to be used by
Intel® PHY (default)
Notes:
This bit must be “1” if using Intel integrated wired
LAN solution.

GBE PCIe* Port Select (GBE_PCIEPORTSEL): This field tells the PCH which PCI Express* port Yes
an Intel® PHY is connected.
This strap defines the GbE port. If PHY_PCIE_EN is =’0’, then this field is
0x17Ch
000 = PORT3 ignored.
001 = PORT4
010 = PORT5 (default) Notes:
5:3 011 = PORT9 This setting is not the same for all designs, is
100 = PORT10 dependent on the board design. The platform
101-111b = Reserved hardware designer or schematic review can
determine what PCIe Port the Intel wired PHY is
Note: In order to access all HSIO control routed.
registers, one must access them before
End of Post.

DMI / PCIe Port Staggering Enable: Yes

2
0 = Disabled
1 = Enabled (default)

1:0 Reserved, set to ‘0’ No

71 Intel Confidential
 Flash Descriptor PCH / CPU Configuration Section

9.66 PCH Descriptor Record 65 (Flash Descriptor Records)

Flash Address:FPSBA + 07Dh

Default Flash Address: 17Dh

FIT
Offset from 0 Bits Description Usage
Visible

7:6 Reserved, set to ‘0’ No

SATA / PCIe Combo Port 2 Strap This setting determine if PCIe/SATA Comb Port Yes
(PCIE_SATA_P2_Flex): 2 is configured natively for SATA or PCIe.
00 = PCIe Port 11 is statically assigned to SATA If the strap setting is configured to ‘11’ the
Port 1 Combo Port behavior is determined by the
01 = PCIe Port 11 is statically assigned to PCIe (or Combo Port2 Select Polarity strap
GbE) (default) (PSCPSP_P2_STRP).
10 = Reserved
11 = Assigned based on the polarity of Note: The settings for this strap and the SATA
/ PCIe Select for Port 1(SATA_PCIE_SP1) and
5:4 SATAXPCIE1 determined by PSCPSP_P2_STRP (SATA_PCIE_GP1) strap must match for
proper port function.

Note: For unused SATA/PCIe* Combo Lanes,

Flex I/O Lanes that can be configured
as PCIe* or SATA, the lanes must be
statically assigned to SATA or PCIe*.
These unused SATA/PCIe* Combo
Lanes must not be assigned as polarity
based.

SATA / PCIe Combo Port 1 Strap This setting determine if PCIe/SATA Comb Port Yes
(PCIE_SATA_P1_Flex): 1 is configured natively for SATA or PCIe.
00 = PCIe Port 8 is statically assigned to SATA If the strap setting is configured to ‘11’ the
Port 1 Combo Port behavior is determined by the
01 = PCIe Port 8 is statically assigned to PCIe (or Combo Port1 Select Polarity strap
GbE) (PSCPSP_P1_STRP).
10 = Reserved
11 = Assigned based on the polarity of Note: The settings for this strap and the SATA
0x17Dh / PCIe Select for Port 1 (SATA_PCIE_SP1)
3:2 SATAXPCIE1 determined by PSCPSP_P1_STRP and (SATA_PCIE_GP1) strap must match for
(default) proper port function.

Note: For unused SATA/PCIe* Combo Lanes,

Flex I/O Lanes that can be configured
as PCIe* or SATA, the lanes must be
statically assigned to SATA or PCIe*.
These unused SATA/PCIe* Combo
Lanes must not be assigned as polarity
based.

SATA / PCIe Combo Port 0 Strap This setting determine if PCIe/SATA Comb Port Yes
(PCIE_SATA_P0_Flex): 0 is configured natively for SATA or PCIe.
00 = PCIe Port 7 is statically assigned to SATA If the strap setting is configured to ‘11’ the
Port 0 (default) Combo Port behavior is determined by the
01 = PCIe Port 7 is statically assigned to PCIe (or Combo Port0 Select Polarity strap
GbE) (PSCPSP_P0_STRP).
10 = Reserved
11 = Assigned based on the polarity of Note: The settings for this strap and the SATA
/ PCIe Select for Port 0 (SATA_PCIE_SP0)
1:0 SATAXPCIE0 determined by PSCPSP_P0_STRP and (SATA_PCIE_GP0) must match for
proper port function.

Note: For unused SATA/PCIe* Combo Lanes,

Flex I/O Lanes that can be configured
as PCIe* or SATA, the lanes must be
statically assigned to SATA or PCIe*.
These unused SATA/PCIe* Combo
Lanes must not be assigned as polarity
based.

Intel Confidential 72
 Flash Descriptor PCH / CPU Configuration Section

9.67 PCH Descriptor Record 66 (Flash Descriptor Records)

Flash Address:FPSBA + 07Eh

Default Flash Address: 17Eh

FIT
Offset from 0 Bits Description Usage
Visible

7:5 Reserved, set to ‘0’ No

USB3 / SSIC Combo Port 1 This setting determine if USB3 / SSIC Combo Yes
(USB3_SSIC_P1_Flex): Port 1 is configured natively for USB3 or SSIC.

0x0 = USB3 Port 2 (default) Note: The settings for this strap and the USB3
0x1 = SSIC Port 1 / SSIC Select for Port 1
0x17Eh 4 (USB3_SSIC_P1_STRP) strap must match
for proper port function.
Note: For SSIC USB3_SSIC_CFG needs to be
set to 0x0.
Note: For USB3 USB3_SSIC_CFG needs to be
set to 0x1

3:0 Reserved, set to ‘0’ No

9.68 PCH Descriptor Record 67 (Flash Descriptor Records)

Flash Address:FPSBA + 07Fh

Default Flash Address: 17Fh

FIT
Offset from 0 Bits Description Usage
Visible

0x17Fh 7:0 Reserved, set to ‘0’ No

9.69 PCH Descriptor Record 68 (Flash Descriptor Records)

Flash Address:FPSBA + 80h

Default Flash Address: 180h

FIT
Offset from 0 Bits Description Usage
Visible

7:2 Reserved, set to ‘0’ No

SATA / PCIe Combo Port 3 Strap This setting determines if PCIe/SATA Comb Port Yes
(PCIE_SATA_P3_Flex): 3 is configured natively for SATA or PCIe.
00 = PCIe Port 12 is statically assigned to SATA If the strap setting is configured to ‘11’ the
Port 2 Combo Port behavior is determined by the
01 = PCIe Port 12 is statically assigned to PCIe (or Combo Port Select Polarity strap
GbE) (default) (PSCPSP_P3_STRP).
10 = Reserved
11 = Assigned based on the polarity of Note: The settings for this strap and the SATA
0x180h SATAXPCIE2 determined by PSCPSP_P3_STRP / PCIe Select for Port 2(SATA_PCIE_SP2) and
1:0 (SATA_PCIE_GP2) must match for proper
port function.

Note: For unused SATA/PCIe* Combo Lanes,

Flex I/O Lanes that can be configured
as PCIe* or SATA, the lanes must be
statically assigned to SATA or PCIe*.
These unused SATA/PCIe* Combo
Lanes must not be assigned as polarity
based.

73 Intel Confidential
 Flash Descriptor PCH / CPU Configuration Section

9.70 PCH Descriptor Record 69 (Flash Descriptor Records)

Flash Address:FPSBA + 81h

Default Flash Address: 181h

FIT
Offset from 0 Bits Description Usage
Visible

0x181h 7:0 Reserved, set to ‘0’ No

9.71 PCH Descriptor Record 70 (Flash Descriptor Records)

Flash Address:FPSBA + 82h

Default Flash Address: 182h

FIT
Offset from 0 Bits Description Usage
Visible

7:4 Reserved, set to ‘0’ No

USB3 / PCIe Combo Port 1 This setting determine if USB3 / PCIe Combo Yes
(PCIE_USB3_P1_Flex): Port 1 is configured natively for USB3 or PCIe.
00 = Statically assigned to USB3 Port 6
3:2 01 = Statically assigned to PCIe Port 2 (or GbE) Note: The settings for this strap and the USB3
(default) / PCIe Select for Port 1
(PCIE_USB3_P1_STRP) strap must match
10 = Reserved. for proper port function.
0x182h 11 = Reserved.

USB3 / PCIe Combo Port 0 This setting determine if USB3 / PCIe Combo Yes
(PCIE_USB3_P0_Flex): Port 0 is configured natively for USB3 or PCIe.
00 = Statically assigned to USB3 Port 5
1:0 01 = Statically assigned to PCIe Port1 (or GbE) Note: The settings for this strap and the USB3
(default) / PCIe Select for Port 0
(PCIE_USB3_P0_STRP) strap must match
10 = Reserved. for proper port function.
11 = Reserved.

9.72 PCH Descriptor Record 71 (Flash Descriptor Records)

Flash Address:FPSBA + 83h

Default Flash Address: 183h

FIT
Offset from 0 Bits Description Usage
Visible

0x183h 7:0 Reserved, set to ‘0’ No

Intel Confidential 74
 Flash Descriptor PCH / CPU Configuration Section

9.73 PCH Descriptor Record 72 (Flash Descriptor Records)

Flash Address:FPSBA + 84h

Default Flash Address: 184h

FIT
Offset from 0 Bits Description Usage
Visible

7:4 Reserved, set to ‘0’ No

Polarity Select SATA / PCIe Combo Port 3 This strap is used to determine the Yes
(PSCPSP_P3_STRP): configuration the native mode configuration for
0x0 = Combo Port 3 is set to PCIe mode when the PCIe/SATA Combo Port 3.
Combo Port Select pin is ‘0’ and SATA when Note: This setting only has effect when PCIe/
Combo Port Select pin is ‘1’ (default) SATA Combo Port 3 (PCIE_SATA_P3_STRP)
0x1 = Combo Port 3 is set to SATA mode when the is configured to ‘11’
3 Combo Port Select pin is ‘0’ and PCIe when Combo
Port Select pin is ‘1’ When configuring this strap you must also
configure SATA / PCIe GPIO Polarity Port 2
(SPS2) to the same setting.
Note: This strap is expected to be set to ‘0x1’
when the combo port is mapped to NGFF M.2 or
eSATA connector and set to ‘0x0’ when the combo
port is mapped to mSATA connector.

Polarity Select SATA / PCIe Combo Port 2 This strap is used to determine the Yes
(PSCPSP_P2_STRP): configuration the native mode configuration for
0x0 = Combo Port 2 is set to PCIe mode when the PCIe/SATA Combo Port 2.
Combo Port Select pin is ‘0’ and SATA when Note: This setting only has effect when PCIe/
Combo Port Select pin is ‘1’ (default) SATA Combo Port 2 (PCIE_SATA_P2_STRP)
0x1 = Combo Port 2 is set to SATA mode when the is configured to ‘11’
2 Combo Port Select pin is ‘0’ and PCIe when Combo
Port Select pin is ‘1’ When configuring this strap you must also
configure SATA / PCIe GPIO Polarity Port 1
(SPS1) to the same setting.
Note: This strap is expected to be set to ‘0x1’
when the combo port is mapped to NGFF M.2 or
eSATA connector and set to ‘0x0’ when the combo
0x184h port is mapped to mSATA connector.

Polarity Select SATA / PCIe Combo Port 1 This strap is used to determine the Yes
(PSCPSP_P1_STRP): configuration the native mode configuration for
0x0 = Combo Port 1 is set to PCIe mode when the PCIe/SATA Combo Port 1.
Combo Port Select pin is ‘0’ and SATA when Note: This setting only has effect when PCIe/
Combo Port Select pin is ‘1’ (default) SATA Combo Port 1 (PCIE_SATA_P1_STRP)is
0x1 = Combo Port 1 is set to SATA mode when the configured to ‘11’
1 Combo Port Select pin is ‘0’ and PCIe when Combo
Port Select pin is ‘1’ When configuring this strap you must also
configure SATA / PCIe GPIO Polarity Port 1
(SPS1) to the same setting.
Note: This strap is expected to be set to ‘0x1’
when the combo port is mapped to NGFF M.2 or
eSATA connector and set to ‘0x0’ when the combo
port is mapped to mSATA connector.

Polarity Select SATA / PCIe Combo Port 0 This strap is used to determine the Yes
(PSCPSP_P0_STRP): configuration the native mode configuration for
0x0 = Combo Port 0 is set to PCIe mode when the PCIe/SATA Combo Port 0.
Combo Port Select pin is ‘0’ and SATA when Note: This setting only has effect when PCIe/
Combo Port Select pin is ‘1’ (default) SATA Combo Port 0 (PCIE_SATA_P0_STRP)
0x1 = Combo Port 0 is set to SATA mode when the is configured to ‘11’
0 Combo Port Select pin is ‘0’ and PCIe when Combo
Port Select pin is ‘1’ When configuring this strap you must also
configure SATA / PCIe GPIO Polarity Port 0
(SPS0)to the same setting.
Note: This strap is expected to be set to ‘0x1’
when the combo port is mapped to NGFF M.2 or
eSATA connector and set to ‘0x0’ when the combo
port is mapped to mSATA connector.

75 Intel Confidential
 Flash Descriptor PCH / CPU Configuration Section

9.74 PCH Descriptor Record 73 (Flash Descriptor Records)

Flash Address:FPSBA + 85h

Default Flash Address: 185h

FIT
Offset from 0 Bits Description Usage
Visible

0x185h 7:0 Reserved, set to ‘0’ No

9.75 PCH Descriptor Record 74 (Flash Descriptor Records)

Flash Address:FPSBA + 86h

Default Flash Address: 186h

FIT
Offset from 0 Bits Description Usage
Visible

0x186h 7:0 Reserved, set to ‘0’ No

9.76 PCH Descriptor Record 75 (Flash Descriptor Records)

Flash Address:FPSBA + 87h

Default Flash Address: 187h

FIT
Offset from 0 Bits Description Usage
Visible

0x187h 7:0 Reserved, set to ‘0’ No

9.77 PCH Descriptor Record 76 (Flash Descriptor Records)

Flash Address:FPSBA + 88h

Default Flash Address: 188h

FIT
Offset from 0 Bits Description Usage
Visible

0x188h 0 Reserved, set to ‘0’ No

Intel Confidential 76
 Flash Descriptor PCH / CPU Configuration Section

9.78 PCH Descriptor Record 77 (Flash Descriptor Records)

Flash Address:FPSBA + 8Ch

Default Flash Address: 18Ch

FIT
Offset from 0 Bits Description Usage
Visible

7:6 Reserved. Set to 0x1 No

SATA / PCIe Select for Port 2 This strap must also be configured when No
(SATA_PCIE_SP2): setting the PCIe/SATA Combo Port 3 Strap
(PCIE_SATA_P3_Flex)
00 = PCIe Port 12 is statically assigned to SATA
Port 1 Note: This strap and the PCIe/SATA Combo
01 = PCIe Port 12 is statically assigned to PCIe (or Port 3 Strap (PCIE_SATA_P3_Flex) and
GbE) (default) (SATA_PCIE_GP2) must match for proper
5:4 port function.
10 = Reserved
11 = Assigned based on the polarity for
Note: For unused SATA/PCIe* Combo Lanes,
SATAXPCIE2
Flex I/O Lanes that can be configured
as PCIe* or SATA, the lanes must be
statically assigned to SATA or PCIe*.
These unused SATA/PCIe* Combo
Lanes must not be assigned as polarity
based.

SATA / PCIe Select for Port 1 This strap must also be configured when No
(SATA_PCIE_SP1): setting the PCIe/SATA Combo Port 1 Strap
(PCIE_SATA_P1_Flex) or PCIe/SATA Combo
Port 2 Strap (PCIE_SATA_P2_Flex).
00 = PCIe Port 8 / PCIe Port 11 is statically
assigned to SATA Port 1 Note: This strap and the PCIe/SATA Combo
01 = PCIe Port 8 / PCIe Port 11 is statically Port 1 Strap (PCIE_SATA_P1_Flex) or PCIe/
assigned to PCIe (or GbE) SATA Combo Port 2 Strap
0x18Ch (PCIE_SATA_P2_Flex) and
10 = Reserved (SATA_PCIE_GP1) must match for proper
3:2
11 = Assigned based on the polarity for port function.
SATAXPCIE1 (default)
Note: For unused SATA/PCIe* Combo Lanes,
Flex I/O Lanes that can be configured
as PCIe* or SATA, the lanes must be
statically assigned to SATA or PCIe*.
These unused SATA/PCIe* Combo
Lanes must not be assigned as polarity
based.

SATA / PCIe Select for Port 0 This strap must also be configured when No
(SATA_PCIE_SP0): setting the PCIe/SATA Combo Port 0 strap
(PCIE_SATA_P0_Flex).
00 = PCIe Port 7 is statically assigned to SATA
Port 0 (default) Note: This strap and the PCIe/SATA Combo
01 = PCIe Port 7 is statically assigned to PCIe (or Port 0 strap (PCIE_SATA_P0_Flex) and
GbE) (SATA_PCIE_GP0) must match for proper
1:0 port function.
10 = Reserved
11 = Assigned based on the polarity for
Note: For unused SATA/PCIe* Combo Lanes,
SATAXPCIE0
Flex I/O Lanes that can be configured
as PCIe* or SATA, the lanes must be
statically assigned to SATA or PCIe*.
These unused SATA/PCIe* Combo
Lanes must not be assigned as polarity
based.

77 Intel Confidential
 Flash Descriptor PCH / CPU Configuration Section

9.79 PCH Descriptor Record 78 (Flash Descriptor Records)

Flash Address:FPSBA + 8Dh

Default Flash Address: 18Dh

FIT
Offset from 0 Bits Description Usage
Visible

7 Reserved. Set to 0x0 No

SATA / PCIe GPIO Polarity Port 2 (SPS2): This strap must also be configured if PCIe/ No
SATA Combo Port 3 Strap
(PCIE_SATA_P3_Flex) is configured to ‘11’
0x0 = GPIO Polarity Port 2 is set to PCIe mode
when the SATAXPCIE2 pin is ‘0’ and SATA when
Note: This setting only has effect when SATA /
SATAXPCIE2 pin is ‘1’ (default) PCIe Select for Port 3 (SATA_PCIE_SP2) is
6 0x1 = GPIO Polarity Port 2 is set to SATA mode configured to ‘11’
when the SATAXPCIE2 pin is ‘0’ and PCIe when
SATAXPCIE2 pin is ‘1’ Note: This strap and the Polarity Select SATA /
PCIe Combo Port 3
(PSCPSP_P3_STRP) must match for proper
port function.

SATA / PCIe GPIO Polarity Port 1 (SPS1): This strap must also be configured if PCIe/ No
SATA Combo Port 1 Strap
(PCIE_SATA_P1_Flex) or PCIe/SATA
0x0 = GPIO Polarity Port 1 is set to PCIe mode Combo Port 2 Strap (PCIE_SATA_P2_Flex)
when the SATAXPCIE1 pin is ‘0’ and SATA when is configured to ‘11’
SATAXPCIE1 pin is ‘1’ (default)
0x18Dh
5 0x1 = GPIO Polarity Port 1 is set to SATA mode Note: This setting only has effect when SATA /
when the SATAXPCIE1 pin is ‘0’ and PCIe when PCIe Select for Port 1 (SATA_PCIE_SP2) is
SATAXPCIE1 pin is ‘1’ configured to ‘11’

Note: This strap and the Polarity Select SATA /

PCIe Combo Port 1 (PSCPSP_P2_STRP) must
match for proper port function.

SATA / PCIe GPIO Polarity Port 0 (SPS0): This strap must also be configured if PCIe/ No
SATA Combo Port 0 strap
(PCIE_SATA_P0_Flex) is configured to ‘11’
0x0 = GPIO Polarity Port 0 is set to PCIe mode
when the SATAXPCIE0 pin is ‘0’ and SATA when
Note: This setting only has effect when SATA /
4 SATAXPCIE0 pin is ‘1’ (default) PCIe Select for Port 0 (SATA_PCIE_SP0) is
0x1 = GPIO Polarity Port 0 is set to SATA mode configured to ‘11’
when the SATAXPCIE0 pin is ‘0’ and PCIe when
SATAXPCIE0 pin is ‘1’ Note: This strap and the Polarity Select SATA /
PCIe Combo Port 0 (PSCPSP_P0_STRP) must
match for proper port function.

3:0 Reserved, set to ‘0x5’ No

9.80 PCH Descriptor Record 79 (Flash Descriptor Records)

Flash Address:FPSBA + 8Eh

Default Flash Address: 18Eh

FIT
Offset from 0 Bits Description Usage
Visible

0x18Eh 1:0 Reserved, set to ‘0’ No

Intel Confidential 78
 Flash Descriptor PCH / CPU Configuration Section

9.81 PCH Descriptor Record 80 (Flash Descriptor Records)

Flash Address:FPSBA + 90h

Default Flash Address: 190h

FIT
Offset from 0 Bits Description Usage
Visible

7:2 Reserved set to ‘0x24’ No

0x190h
1:0 Reserved, set to ‘0x1’ No

9.82 PCH Descriptor Record 81 (Flash Descriptor Records)

Flash Address:FPSBA + 91h

Default Flash Address: 191h

FIT
Offset from 0 Bits Description Usage
Visible

7 Reserved, set to ‘0x1’ No

0x191h
6:0 Reserved, set to ‘0x70’ No

9.83 PCH Descriptor Record 82 (Flash Descriptor Records)

Flash Address:FPSBA + 92h

Default Flash Address: 192h

FIT
Offset from 0 Bits Description Usage
Visible

7:3 Reserved set to ‘0x01’ No

PHY Connection (PHYCON): This field must be set to “10” if Intel® Yes
This field determines if Intel® wired PHY is integrated wired LAN solution is used.
connected. If not using, or if disabling Intel® integrated
0x192h wired LAN solution, then field must be set to
2:0 “00”.
000 = No PHY connected
001= PHY on SMBus
010 = PHY on SMLink0 (default)
011 = PHY on SMLink1

9.84 PCH Descriptor Record 83 (Flash Descriptor Records)

Flash Address:FPSBA + 93h

Default Flash Address: 193h

FIT
Offset from 0 Bits Description Usage
Visible

7:4 Reserved, set to ‘0xf’ No

0x193h 3:2 Reserved, set to ‘0x3’ No

1:0 Reserved, set to ‘0x3’ No

79 Intel Confidential
 Flash Descriptor PCH / CPU Configuration Section

9.85 PCH Descriptor Record 84 (Flash Descriptor Records)

Flash Address:FPSBA + 94h

Default Flash Address: 194h

FIT
Offset from 0 Bits Description Usage
Visible

7:4 Reserved, set to ‘0xf’ No

3 Reserved, set to ‘0’ No

0x194h
2 Reserved set to ‘0x1’ No

1:0 Reserved, set to ‘0x3’ No

9.86 PCH Descriptor Record 85 (Flash Descriptor Records)

Flash Address:FPSBA + 95h

Default Flash Address: 195h

FIT
Offset from 0 Bits Description Usage
Visible

7:2 Reserved, set to ‘0x3f’ No

0x195h
1:0 Reserved, set to ‘0’ No

9.87 PCH Descriptor Record 86 (Flash Descriptor Records)

Flash Address:FPSBA + 96h

Default Flash Address: 196h

FIT
Offset from 0 Bits Description Usage
Visible

7:2 Reserved, set to ‘0x3f’ No

0x196h
1:0 Reserved, set to ‘0’ No

9.88 PCH Descriptor Record 87 (Flash Descriptor Records)

Flash Address:FPSBA + 97h

Default Flash Address: 197h

FIT
Offset from 0 Bits Description Usage
Visible

7:2 Reserved, set to ‘0x3f’ No

0x197h
1:0 Reserved, set to ‘0’ No

Intel Confidential 80
 Flash Descriptor PCH / CPU Configuration Section

9.89 PCH Descriptor Record 88 (Flash Descriptor Records)

Flash Address:FPSBA + 98h

Default Flash Address: 198h

FIT
Offset from 0 Bits Description Usage
Visible

0x198h 31:0 Reserved, set to ‘0’ No

9.90 PCH Descriptor Record 89 (Flash Descriptor Records)

Flash Address:FPSBA + 9Ch

Default Flash Address: 19Ch

FIT
Offset from 0 Bits Description Usage
Visible

0x19Ch 7:0 Reserved, set to ‘0’ No

9.91 PCH Descriptor Record 90 (Flash Descriptor Records)

Flash Address:FPSBA + 9Dh

Default Flash Address: 19Dh

FIT
Offset from 0 Bits Description Usage
Visible

7:5 Reserved, set to ‘0x0’ No

PCIe Controller 1 (Port 1-4): Setting of this field depend on what PCIe ports Yes
Straps to set the default value of the PCI Express 1-4 configurations are desired by the board
manufacturer.
Port Configuration 1 register covering PCIe ports
1-4.

00 = 4x1 Note: This field must be determined by the

4:3
01 = 1x2, 2x1 PCI Express port requirements of the
design. The platform hardware
10 = 2x2 designer must determine this setting.
11 = 1x4 (default)

0x19Dh Note: Refer to EDS for PCIe supported port

configurations.

PCIe Controller 1 Lane Reversal: This bit controls lane reversal behavior for PCIe Yes
Controller 1.
0 = PCIe Lanes are not reversed. (default)
PCI Express port lane reversal can be done to
1 = PCIe Lanes are reversed.
2 aid in the laying out of the board.

Note: Refer to EDS supported Lane reversal

Note: This setting is dependent on the board
configuration.
design. The platform hardware designer must
determine if this port needs lane reversal.

1:0 Reserved, set to ‘0’ No

81 Intel Confidential
 Flash Descriptor PCH / CPU Configuration Section

9.92 PCH Descriptor Record 91 (Flash Descriptor Records)

Flash Address:FPSBA + 9Eh

Default Flash Address: 19Eh

FIT
Offset from 0 Bits Description Usage
Visible

0x19Eh 7:0 Reserved, set to ‘0’ No

9.93 PCH Descriptor Record 92 (Flash Descriptor Records)

Flash Address:FPSBA + 9Fh

Default Flash Address: 19Fh

FIT
Offset from 0 Bits Description Usage
Visible

0x19Fh 7:0 Reserved, set to ‘0’ No

9.94 PCH Descriptor Record 93 (Flash Descriptor Records)

Flash Address:FPSBA + A0h

Default Flash Address: 1A0h

FIT
Offset from 0 Bits Description Usage
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0x1A0h 7:0 Reserved, set to ‘0’ No

9.95 PCH Descriptor Record 94 (Flash Descriptor Records)

Flash Address:FPSBA + A1h

Default Flash Address: 1A1h

FIT
Offset from 0 Bits Description Usage
Visible

0x1A1h 7:0 Reserved, set to ‘0’ No

9.96 PCH Descriptor Record 95 (Flash Descriptor Records)

Flash Address:FPSBA + A2h

Default Flash Address: 1A2h

FIT
Offset from 0 Bits Description Usage
Visible

0x1A2h 7:0 Reserved, set to ‘0’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.97 PCH Descriptor Record 96 (Flash Descriptor Records)

Flash Address:FPSBA + A3h

Default Flash Address: 1A3h

FIT
Offset from 0 Bits Description Usage
Visible

0x1A3h 7:0 Reserved, set to ‘0’ No

9.98 PCH Descriptor Record 97 (Flash Descriptor Records)

Flash Address:FPSBA + A4h

Default Flash Address: 1A4h

FIT
Offset from 0 Bits Description Usage
Visible

0x1A4h 7:0 Reserved, set to ‘0’ No

9.99 PCH Descriptor Record 98 (Flash Descriptor Records)

Flash Address:FPSBA + A5h

Default Flash Address: 1A5h

FIT
Offset from 0 Bits Description Usage
Visible

7:5 Reserved, set to ‘0’ No

PCIe Controller 2 (Port 5-8): Setting of this field depend on what PCIe ports Yes
Straps to set the default value of the PCI Express 5-8 configurations are desired by the board
Port Configuration 2 register covering PCIe ports manufacturer.
5-8.

4:3 00 = 4x1 (default) Note: This field must be determined by the

01 = 1x2, 2x1 PCI Express port requirements of the
10 = 2x2 design. The platform hardware
designer must determine this setting.
11 = 1x4
Note: Refer to EDS for PCIe supported port
0x1A5h configurations.

PCIe Controller 2 Lane Reversal: This bit controls lane reversal behavior for PCIe Yes
Controller 2.
0 = PCIe Lanes are not reversed. (default)
PCI Express port lane reversal can be done to
1 = PCIe Lanes are reversed.
2 aid in the laying out of the board.
Note: Refer to EDS supported Lane reversal
Note: This setting is dependent on the board
configuration.
design. The platform hardware
designer must determine if this port
needs lane reversal.

1:0 Reserved, set to ‘0’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.100 PCH Descriptor Record 99 (Flash Descriptor Records)

Flash Address:FPSBA + A6h

Default Flash Address: 1A6h

FIT
Offset from 0 Bits Description Usage
Visible

0x1A6h 7:0 Reserved, set to ‘0’ No

9.101 PCH Descriptor Record 100 (Flash Descriptor Records)

Flash Address:FPSBA + A7h

Default Flash Address: 1A7h

FIT
Offset from 0 Bits Description Usage
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PCIe Controller 2 Port 4 SRIS: This is used to configures the platform Intel® Yes
RST for PCIe (SATA Express) interface on PCIe
Controller 2.
0x0 = Disabled (default)
7 0x1 = Enabled Note:
1. Only 2 concurrent SATA Express devices
supported for Kabylake-LP.
2. The x1 is required to meet PCIe
specification requirement but is not a
supported SATA Express configuration.

PCIe Controller 2 Port 3 SRIS: This is used to configures the platform Intel® Yes
RST for PCIe (SATA Express) interface on PCIe
Controller 2.
0x0 = Disabled (default)
6 0x1 = Enabled Note:
1. Only 2 concurrent SATA Express devices
supported for Kabylake-LP.
2. The x1 is required to meet PCIe
specification requirement but is not a
supported SATA Express configuration.

0x1A7h PCIe Controller 2 Port 2 SRIS: This is used to configures the platform Intel® Yes
RST for PCIe (SATA Express) interface on PCIe
Controller 2.
0x0 = Disabled (default)
5 0x1 = Enabled Note:
1. Only 2 concurrent SATA Express devices
supported for Kabylake-LP.
2. The x1 is required to meet PCIe
specification requirement but is not a
supported SATA Express configuration.

PCIe Controller 2 Port 1 SRIS: This is used to configures the platform Intel® Yes
RST for PCIe (SATA Express) interface on PCIe
Controller 2.
0x0 = Disabled (default)
4 0x1 = Enabled Note:
1. Only 2 concurrent SATA Express devices
supported for Kabylake-LP.
2. The x1 is required to meet PCIe
specification requirement but is not a
supported SATA Express configuration.

3:0 Reserved, set to ‘0’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.102 PCH Descriptor Record 101 (Flash Descriptor Records)

Flash Address:FPSBA + A8h

Default Flash Address: 1A8h

FIT
Offset from 0 Bits Description Usage
Visible

0x1A8h 7:0 Reserved, set to ‘0’ No

9.103 PCH Descriptor Record 102 (Flash Descriptor Records)

Flash Address:FPSBA + A9h

Default Flash Address: 1A9h

FIT
Offset from 0 Bits Description Usage
Visible

0x1A9h 7:0 Reserved, set to ‘0’ No

9.104 PCH Descriptor Record 103 (Flash Descriptor Records)

Flash Address:FPSBA + AAh

Default Flash Address: 1AAh

FIT
Offset from 0 Bits Description Usage
Visible

0x1AAh 7:0 Reserved, set to ‘0’ No

9.105 PCH Descriptor Record 104 (Flash Descriptor Records)

Flash Address:FPSBA + ABh

Default Flash Address: 1ABh

FIT
Offset from 0 Bits Description Usage
Visible

0x1ABh 7:0 Reserved, set to ‘0’ No

9.106 PCH Descriptor Record 105 (Flash Descriptor Records)

Flash Address:FPSBA + ACh

Default Flash Address: 1ACh

FIT
Offset from 0 Bits Description Usage
Visible

0x1ACh 7:0 Reserved, set to ‘0’ No

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9.107 PCH Descriptor Record 106 (Flash Descriptor Records)

Flash Address:FPSBA + ADh

Default Flash Address: 1ADh

FIT
Offset from 0 Bits Description Usage
Visible

7:5 Reserved, set to ‘0’ No

PCIe Controller 3 (Port 9-12): Setting of this field depend on what PCIe ports Yes
Straps to set the default value of the PCI Express 9-12 configurations are desired by the board
Port Configuration 3 register covering PCIe ports manufacturer.
9-12.

00 = 4x1 (default)
01 = 1x2, 2x1 Note: This field must be determined by the
PCI Express port requirements of the
4:3 10 = 2x2 design. The platform hardware
11 = 1x4 designer must determine this setting.

Note: Refer to EDS for PCIe supported port

configurations.
0x1ADh Note: For Kabylake-LP Base U and Premium Y
PCIe Controller 3 has only Port 9-10 and
is limited to 1x2, 2x1 port configuration
only.

PCIe Controller 3 Lane Reversal: This bit controls lane reversal behavior for PCIe Yes
Controller 3.
0 = PCIe Lanes are not reversed. (default)
1 = PCIe Lanes are reversed. PCI Express port lane reversal can be done to
2 aid in the laying out of the board.

Note: Refer to EDS supported Lane reversal

Note: This setting is dependent on the board
configuration.
design. The platform hardware designer must
determine if this port needs lane reversal.

1:0 Reserved, set to ‘0’ No

9.108 PCH Descriptor Record 107 (Flash Descriptor Records)

Flash Address:FPSBA + AEh

Default Flash Address: 1AEh

FIT
Offset from 0 Bits Description Usage
Visible

0x1AEh 7:0 Reserved, set to ‘0’ No

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9.109 PCH Descriptor Record 108 (Flash Descriptor Records)

Flash Address:FPSBA + AFh

Default Flash Address: 1AFh

FIT
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PCIe Controller 3 Port 4 SRIS Enable: This is used to configures the platform Intel® Yes
RST for PCIe (SATA Express) interface on PCIe
Controller 3.
0x0 = Disabled (default)
7 0x1 = Enabled Note:
1. Only 2 concurrent SATA Express devices
supported for Kabylake-LP.
2. The x1 is required to meet PCIe
specification requirement but is not a
supported SATA Express configuration.

PCIe Controller 3 Port 3 SRIS Enable: This is used to configures the platform Intel® Yes
RST for PCIe (SATA Express) interface on PCIe
Controller 3.
0x0 = Disabled (default)
6 0x1 = Enabled Note:
1. Only 2 concurrent SATA Express devices
supported for Kabylake-LP.
2. The x1 is required to meet PCIe
specification requirement but is not a
supported SATA Express configuration.

0x1AFh PCIe Controller 3 Port 2 SRIS Enable: This is used to configures the platform Intel® Yes
RST for PCIe (SATA Express) interface on PCIe
Controller 3.
0x0 = Disabled (default)
5 0x1 = Enabled Note:
1. Only 2 concurrent SATA Express devices
supported for Kabylake-LP.
2. The x1 is required to meet PCIe
specification requirement but is not a
supported SATA Express configuration.

PCIe Controller 3 Port 1 SRIS Enable: This is used to configures the platform Intel® Yes
RST for PCIe (SATA Express) interface on PCIe
Controller 3.
0x0 = Disabled (default)
4 0x1 = Enabled Note:
1. Only 2 concurrent SATA Express devices
supported for Kabylake-LP.
2. The x1 is required to meet PCIe
specification requirement but is not a
supported SATA Express configuration.

3:0 Reserved, set to ‘0’ No

9.110 PCH Descriptor Record 109 (Flash Descriptor Records)

Flash Address:FPSBA + B0h

Default Flash Address: 1B0h

FIT
Offset from 0 Bits Description Usage
Visible

0x1B0h 7:0 Reserved, set to ‘0’ No

87 Intel Confidential
 Flash Descriptor PCH / CPU Configuration Section

9.111 PCH Descriptor Record 110 (Flash Descriptor Records)

Flash Address:FPSBA + B1h

Default Flash Address: 1B1h

FIT
Offset from 0 Bits Description Usage
Visible

0x1B1h 7:0 Reserved, set to ‘0’ No

9.112 PCH Descriptor Record 111 (Flash Descriptor Records)

Flash Address:FPSBA + B2h

Default Flash Address: 1B2h

FIT
Offset from 0 Bits Description Usage
Visible

0x1B2h 7:0 Reserved, set to ‘0’ No

9.113 PCH Descriptor Record 112 (Flash Descriptor Records)

Flash Address:FPSBA + B3h

Default Flash Address: 1B3h

FIT
Offset from 0 Bits Description Usage
Visible

0x1B3h 7:0 Reserved, set to ‘0’ No

9.114 PCH Descriptor Record 113 (Flash Descriptor Records)

Flash Address:FPSBA + B4h

Default Flash Address: 1B4h

FIT
Offset from 0 Bits Description Usage
Visible

31:7 Reserved, set to ‘0’ No

0x1B4h 6 Reserved, set to ‘0x1’ No

5:0 Reserved, set to ‘0x7’ No

Intel Confidential 88
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9.115 PCH Descriptor Record 114 (Flash Descriptor Records)

Flash Address:FPSBA + B8h

Default Flash Address: 1B8h

FIT
Offset from 0 Bits Description Usage
Visible

7:6 Reserved, set to ‘0’ No

XHCI Port 5 Ownership Yes

(XHCI_PORT5_OWNERSHIP_STRAP):
Strap to decide XHCI Port 6 Ownership between
XHCI/PCIe/CSI.
5

0x0 = XHCI Port 6 configured as XHCI

0x1 = XHCI Port 6 configures as Non-XHCI
(default)

XHCI Port 4 Ownership Yes

(XHCI_PORT4_OWNERSHIP_STRAP):
Strap to decide XHCI Port 5 Ownership between
XHCI/PCIe/CSI.
4

0x0 = XHCI Port 5 configured as XHCI

0x1 = XHCI Port 5 configures as Non-XHCI
(default)

XHCI Port 3 Ownership Yes

(XHCI_PORT3_OWNERSHIP_STRAP):
Strap to decide XHCI Port 4 Ownership between
3 XHCI/PCIe/CSI.

0x1B8h 0x0 = XHCI Port 4 configured as XHCI (default)

0x1 = XHCI Port 4 configures as Non-XHCI

XHCI Port 2 Ownership Yes

(XHCI_PORT2_OWNERSHIP_STRAP):
Strap to decide XHCI Port 3 Ownership between
2 XHCI/PCIe/CSI.

0x0 = XHCI Port 3 configured as XHCI (default)

0x1 = XHCI Port 3 configures as Non-XHCI

XHCI Port 1 Ownership Yes

(XHCI_PORT1_OWNERSHIP_STRAP):
Strap to decide XHCI Port 2 Ownership between
1 XHCI/PCIe/CSI.

0x0 = XHCI Port 2 configured as XHCI (default)

0x1 = XHCI Port 2 configures as Non-XHCI

XHCI Port 0 Ownership Yes

(XHCI_PORT0_OWNERSHIP_STRAP):
Strap to decide XHCI Port 1 Ownership between
0 XHCI/PCIe/CSI.

0x0 = XHCI Port 1 configured as XHCI (default)

0x1 = XHCI Port 1 configures as Non-XHCI

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9.116 PCH Descriptor Record 115 (Flash Descriptor Records)

Flash Address:FPSBA + B9h

Default Flash Address: 1B9h

FIT
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Visible

7:2 Reserved, set to ‘0’ No

USB3 / SSIC Port 1 Configuration This strap must be configured when setting No
(USB3_SSIC_PORT1_STRAP): USB3 / SSIC Combo Port 1 strap
Strap to decide Port 1 Ownership between USB3/ (USB3_SSIC_P1_Flex).
0x1B9h 1 SSIC.
Note: This strap and the USB3 / SSIC Combo
0x0 = Port 1 configured for USB3 (default) Port 1 strap (USB3_SSIC_P1_Flex) must
match for proper port function.
0x1 = Port 1 configured for SSIC

0 Reserved, set to ‘0’ Yes

9.117 PCH Descriptor Record 116 (Flash Descriptor Records)

Flash Address:FPSBA + BAh

Default Flash Address: 1BAh

FIT
Offset from 0 Bits Description Usage
Visible

0x1BAh 7:0 Reserved, set to ‘0’ No

9.118 PCH Descriptor Record 117 (Flash Descriptor Records)

Flash Address:FPSBA + BCh

Default Flash Address: 1BCh

FIT
Offset from 0 Bits Description Usage
Visible

7:6 Reserved, set to ‘0’ No

0x1BCh 5:4 Reserved, set to ‘0x3’ No

3:0 Reserved, set to ‘0xf’ No

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9.119 PCH Descriptor Record 118 (Flash Descriptor Records)

Flash Address:FPSBA + BDh

Default Flash Address: 1BDh

FIT
Offset from 0 Bits Description Usage
Visible

7:4 Reserved, set to ‘0’ No

PROCPWRGD and SYS_PWROK high to tPCH46: PROCPWRGD and SYS_PWROK high to Yes
SUS_STAT# de-assertion (tPCH46): SUS_STAT# deassertion. Refer to EDS for
details.

3:2 00 = 1 ms (default)
01 = Reserved
10 = 5 ms
0x1BDh 11 = 2 ms

PCH clock output stable to PROCPWRGD high tPCH45: PCH clock output stable to Yes
(tPCH45): PROCPWRGD high. Refer to EDS for details.

1:0 00 = 100 ms
01 = 50 ms
10 = 5 ms
11 = 1 ms (default)

9.120 PCH Descriptor Record 119 (Flash Descriptor Records)

Flash Address:FPSBA + BEh

Default Flash Address: 1BEh

FIT
Offset from 0 Bits Description Usage
Visible

7 Reserved, set to ‘0’ No

APWROK Timing (APWROK_TIMING): This soft strap determines the time between Yes
the SLP_A# pin de-asserting and the APWROK
timer expiration.
00 = 2 ms (default)
6:5
01 = 4 ms
10 = 8 ms
11 = 16 ms

Deep Sx Enable (DEEPSX_PLT_CFG_SS): This requires the target platform to support Yes
Deep SX state
0x1BEh
4 0 =The platform does not support DeepSx.
1 =The platform supports DeepSx (default) Note: When configuring Deep Sx you must
also set Deep_SX_EN.

LAN PHY Power Up Time This bit determines how long the delay for LAN Yes
(LAN_PHY_PU_TIME): PHY to power up after de-assertion of
3 SLP_LAN#.
0 =100ms (default)
1 =50ms

2:0 Reserved, set to ‘0’ No

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9.121 PCH Descriptor Record 120 (Flash Descriptor Records)

Flash Address:FPSBA + BFh

Default Flash Address: 1BFh

FIT
Offset from 0 Bits Description Usage
Visible

7:4 Reserved, set to ‘0’ No

®
3 Intel Trace Hub Debug Messages Enable: This setting enables debug messages on the Yes
Intel® Trace Hub.
0 = PCH Tracing debug messages Disabled
(default) Note: You will also need to set the Intel® Trace
1 = PCH Tracing debug messages Enabled Hub Soft Enable to “Enabled”
0x1BFh
2:1 Reserved, set to ‘0’ No

PCIe Power Stable Timer (tPCH33): Board dependent. Yes

Default is disabled, Platform is required to
0 0 = tPCH33 timer is disabled (default) ensure timing of PWROK and SYS_PWROK in
such a way that it satisfies the PCIe timing
1 = PCH will count 99ms from PWROK assertion
requirement of power stable to reset de-
before PLTRST# is de-asserted.
assertion.

9.122 PCH Descriptor Record 121 (Flash Descriptor Records)

Flash Address:FPSBA + C0h

Default Flash Address: 1C0h

FIT
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Integrated Sensor Hub Supported: Yes

7
0 = Enable Integrated Sensor Hub
1 = Disable Integrated Sensor Hub (default)

6:1 Reserved, set to ‘0’ No

Intel® Integrated wired LAN Enable This must be set to '0' if the platform is using Yes
(IWL_EN): the Intel® Integrated wired LAN solution.
This must be set to ’1’ if not using the Intel®
0x1C0h
Integrated wired LAN solution or if disabling it.
0 = Enabled Intel® Integrated wired LAN Solution
(default)
0 1 = Disabled Intel® Integrated wired LAN Solution

Note:
This must be set to '0' if the platform is using
Intel's integrated wired LAN solution. Set to ’1’ if
not using Intel integrated wired LAN solution or if
disabling it.

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9.123 PCH Descriptor Record 122 (Flash Descriptor Records)

Flash Address:FPSBA + C1h

Default Flash Address: 1C1h

FIT
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Visible

0x1C1h 7:0 Reserved, set to ‘0’ No

9.124 PCH Descriptor Record 123 (Flash Descriptor Records)

Flash Address:FPSBA + C2h

Default Flash Address: 1C2h

FIT
Offset from 0 Bits Description Usage
Visible

0x1C2h 7:0 Reserved, set to ‘0’ No

9.125 PCH Descriptor Record 124 (Flash Descriptor Records)

Flash Address:FPSBA + C3h

Default Flash Address: 1C3h

FIT
Offset from 0 Bits Description Usage
Visible

0x1C3h 7:0 Reserved, set to ‘0’ No

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9.126 PCH Descriptor Record 125 (Flash Descriptor Records)

Flash Address:FPSBA + C4h

Default Flash Address: 1C4h

FIT
Offset from 0 Bits Description Usage
Visible

31 Reserved, set to ‘0’ No

SLP_S0# Tunnel (SLP_S0_TUNNEL_DIS): This setting enables / disabled the SLP_S0# Yes
tunneling over the eSPI to EC interface.
30 0 = SLP_S0# Tunnel enabled (default)
Note: On eSPI enabled platforms this should
1 = SLP_S0# Tunnel disabled
be set to disabled for proper Sleep S0
operation.

29:5 Reserved, set to ‘0’ No

USB3 / SSIC Configuration This strap must be configured when setting No

(USB3_SSIC_CFG) USB3 / SSIC Combo Port 1 strap
4 (USB3_SSIC_P1_Flex).
0 = SSIC Enabled
1 = USB3 Enabled (default)
0x1C4h 3 Reserved, set to ‘0’ No

OPI Link Voltage Strap (OPD_LVO_STRP): This strap must be configured when setting OPI No
Link Speed strap (OPD_LVO).
0 = 0.85 Volts (default)
2:1 Note: This strap and the OPI Link Speed strap
1 = 0.95 Volts
(OPD_LVO) must match the same voltage
configuration setting for proper platform
operation function.

OPI Link Speed Strap (OPDMI_STRP): This strap must be configured when setting OPI No
Link Speed strap (OPDMI_TLS).
0 = GT2 Link Speed (default)
0 Note: This strap and the OPI Link Speed strap
1 = GT4 Link Speed
(OPDMI_TLS) must match the same GT
configuration setting for proper platform
operation function.

9.127 PCH Descriptor Record 126 (Flash Descriptor Records)

Flash Address:FPSBA + C8h

Default Flash Address: 1C8h

FIT
Offset from 0 Bits Description Usage
Visible

0x1C8h 7:0 Reserved, set to ‘0’ No

9.128 PCH Descriptor Record 127 (Flash Descriptor Records)

Flash Address:FPSBA + C9h

Default Flash Address: 1C9h

FIT
Offset from 0 Bits Description Usage
Visible

0x1C9h 7:0 Reserved, set to ‘0’ No

Intel Confidential 94
 Flash Descriptor PCH / CPU Configuration Section

9.129 PCH Descriptor Record 128 (Flash Descriptor Records)

Flash Address:FPSBA + CAh

Default Flash Address: 1CAh

FIT
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Visible

7 Reserved, set to ‘0’ No

0x1CAh
6:0 Reserved, set to ‘0x64’ No

9.130 PCH Descriptor Record 129 (Flash Descriptor Records)

Flash Address:FPSBA + CBh

Default Flash Address: 1CBh

FIT
Offset from 0 Bits Description Usage
Visible

7:3 Reserved, set to ‘0’ No

0x1CBh
2:0 Reserved, set to ‘0x2’ No

9.131 PCH Descriptor Record 130 (Flash Descriptor Records)

Flash Address:FPSBA + CCh

Default Flash Address: 1CCh

FIT
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Visible

0x1CCh 31:0 Reserved, set to ‘0x0’ No

9.132 PCH Descriptor Record 131 (Flash Descriptor Records)

Flash Address:FPSBA + D0h

Default Flash Address: 1D0h

FIT
Offset from 0 Bits Description Usage
Visible

0x1D0h 7:0 Reserved, set to ‘0’ No

9.133 PCH Descriptor Record 132 (Flash Descriptor Records)

Flash Address:FPSBA + D1h

Default Flash Address: 1D1h

FIT
Offset from 0 Bits Description Usage
Visible

0x1D1h 7:0 Reserved, set to ‘0xf4’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.134 PCH Descriptor Record 133 (Flash Descriptor Records)

Flash Address:FPSBA + D2h

Default Flash Address: 1D2h

FIT
Offset from 0 Bits Description Usage
Visible

7:4 Reserved, set to ‘0x6’ No

0x1D2h
3:0 Reserved, set to ‘0x1’ No

9.135 PCH Descriptor Record 134 (Flash Descriptor Records)

Flash Address:FPSBA + D3h

Default Flash Address: 1D3h

FIT
Offset from 0 Bits Description Usage
Visible

0x1D3h 7:0 Reserved, set to ‘0x9’ No

9.136 PCH Descriptor Record 135 (Flash Descriptor Records)

Flash Address:FPSBA + D4h

Default Flash Address: 1D4h

FIT
Offset from 0 Bits Description Usage
Visible

0x1D4h 7:0 Reserved, set to ‘0x19’ No

9.137 PCH Descriptor Record 136 (Flash Descriptor Records)

Flash Address:FPSBA + D8h

Default Flash Address: 1D8h

FIT
Offset from 0 Bits Description Usage
Visible

0x1D8h 7:0 Reserved, set to ‘0x79’ No

9.138 PCH Descriptor Record 137 (Flash Descriptor Records)

Flash Address:FPSBA + D9h

Default Flash Address: 1D9h

FIT
Offset from 0 Bits Description Usage
Visible

0x1D9h 7:0 Reserved, set to ‘0x55’ No

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9.139 PCH Descriptor Record 138 (Flash Descriptor Records)

Flash Address:FPSBA + DAh

Default Flash Address: 1DAh

FIT
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Visible

0x1DAh 7:0 Reserved, set to ‘0x55’ No

9.140 PCH Descriptor Record 139 (Flash Descriptor Records)

Flash Address:FPSBA + DBh

Default Flash Address: 1DBh

FIT
Offset from 0 Bits Description Usage
Visible

0x1DBh 6:0 Reserved, set to ‘0x55’ No

9.141 PCH Descriptor Record 140 (Flash Descriptor Records)

Flash Address:FPSBA + DCh

Default Flash Address: 1DCh

FIT
Offset from 0 Bits Description Usage
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0x1DCh 7:0 Reserved, set to ‘0x1f’ No

9.142 PCH Descriptor Record 141 (Flash Descriptor Records)

Flash Address:FPSBA + DDh

Default Flash Address: 1DDh

FIT
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Visible

0x1DDh 1:0 Reserved, set to ‘0x1’ No

9.143 PCH Descriptor Record 142 (Flash Descriptor Records)

Flash Address:FPSBA + DEh

Default Flash Address: 1DEh

FIT
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Visible

0x1DEh 7:0 Reserved, set to ‘0’ No

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9.144 PCH Descriptor Record 143 (Flash Descriptor Records)

Flash Address:FPSBA + DFh

Default Flash Address: 1DFh

FIT
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0x1DFh 1:0 Reserved, set to ‘0’ No

9.145 PCH Descriptor Record 144 (Flash Descriptor Records)

Flash Address:FPSBA + E0h

Default Flash Address: 1E0h

FIT
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Visible

0x1E0h 3:0 Reserved, set to ‘0x3’ No

9.146 PCH Descriptor Record 145 (Flash Descriptor Records)

Flash Address:FPSBA + E1h

Default Flash Address: 1E1h

FIT
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Visible

0x1E1h 4:0 Reserved, set to ‘0x07’ No

9.147 PCH Descriptor Record 146 (Flash Descriptor Records)

Flash Address:FPSBA + E2h

Default Flash Address: 1E2h

FIT
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Visible

0x1E2h 2:0 Reserved, set to ‘0x1’ No

9.148 PCH Descriptor Record 147 (Flash Descriptor Records)

Flash Address:FPSBA + E3h

Default Flash Address: 1E3h

FIT
Offset from 0 Bits Description Usage
Visible

6:3 Reserved, set to ‘0x1’ No

0x1E3h
2:0 Reserved, set to ‘0x2’ No

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9.149 PCH Descriptor Record 148 (Flash Descriptor Records)

Flash Address:FPSBA + E4h

Default Flash Address: 1E4h

FIT
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Visible

0x1E4h 2:0 Reserved, set to ‘0’ No

9.150 PCH Descriptor Record 149 (Flash Descriptor Records)

Flash Address:FPSBA + E5h

Default Flash Address: 1E5h

FIT
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Visible

0x1E5h 1:0 Reserved, set to ‘0x2’ No

9.151 PCH Descriptor Record 150 (Flash Descriptor Records)

Flash Address:FPSBA + E6h

Default Flash Address: 1E6h

FIT
Offset from 0 Bits Description Usage
Visible

0x1E6h 7:0 Reserved, set to ‘0’ No

9.152 PCH Descriptor Record 151 (Flash Descriptor Records)

Flash Address:FPSBA + E7h

Default Flash Address: 1E7h

FIT
Offset from 0 Bits Description Usage
Visible

0x1E7h 1:0 Reserved, set to ‘0’ No

9.153 PCH Descriptor Record 152 (Flash Descriptor Records)

Flash Address:FPSBA + E8h

Default Flash Address: 1E8h

FIT
Offset from 0 Bits Description Usage
Visible

0x1E8h 7:0 Reserved, set to ‘0x09’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.154 PCH Descriptor Record 153 (Flash Descriptor Records)

Flash Address:FPSBA + E9h

Default Flash Address: 1E9h

FIT
Offset from 0 Bits Description Usage
Visible

0x1E9h 1:0 Reserved, set to ‘0’ No

9.155 PCH Descriptor Record 154 (Flash Descriptor Records)

Flash Address:FPSBA + EAh Size: 8 bit Default value: 01h

Default Flash Address: 1EAh

FIT
Offset from 0 Bits Description Usage
Visible

7:6 Reserved, set to ‘0’ No

5:3 Reserved, set to ‘0x1’ No

0x1EAh
2 Reserved, set to ‘0x1’ No

1:0 Reserved, set to ‘0x3’ No

9.156 PCH Descriptor Record 155 (Flash Descriptor Records)

Flash Address:FPSBA + EBh

Default Flash Address: 1EBh

FIT
Offset from 0 Bits Description Usage
Visible

7:2 Reserved, set to ‘0’ No

0x1EBh 1 Reserved, set to ‘0x1’ No

0 Reserved, set to ‘0’ No

9.157 PCH Descriptor Record 156 (Flash Descriptor Records)

Flash Address:FPSBA + ECh

Default Flash Address: 1ECh

FIT
Offset from 0 Bits Description Usage
Visible

0x1ECh 15:0 Reserved, set to ‘0’ No

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9.158 PCH Descriptor Record 157 (Flash Descriptor Records)

Flash Address:FPSBA + EEh

Default Flash Address: 1EEh

FIT
Offset from 0 Bits Description Usage
Visible

0x1EEh 7:0 Reserved, set to ‘0xff’ No

9.159 PCH Descriptor Record 158 (Flash Descriptor Records)

Flash Address:FPSBA + EFh

Default Flash Address: 1EFh

FIT
Offset from 0 Bits Description Usage
Visible

0x1EFh 7:0 Reserved, set to ‘0’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.160 PCH Descriptor Record 159 (Flash Descriptor Records)

Flash Address:FPSBA + F0h

Default Flash Address: 1F0h

FIT
Offset from 0 Bits Description Usage
Visible
7 Reserved, set to ‘0’ No
Top Swap Block size (TSBS): his allows for the system to use alternate code Yes
000 = 64 KB. Invert A16 if Top Swap is enabled in order to boot a platform based upon the Top
(Default) Swap (GPIO66/SDIO_D0 pulled low during the
rising edge of PWROK.) strap being asserted.
001 = 128 KB. Invert A17 if Top Swap is enabled
Top Swap inverts an address on access to SPI
010 = 256 KB. Invert A18 if Top Swap is enabled
and firmware hub, so the processor fetches the
011 = 512 KB. Invert A19 if Top Swap is enabled alternate Top Swap block instead of the original
100 = 1 MB. Invert A20 if Top Swap is enabled boot-block. The size of the Top Swap block and
101 - 111: Reserved. setting of this field must be determined by the
BIOS developer. If this is not set correctly, then
6:4 Note: BIOS boot-block recovery mechanism will not
This setting is dependent on BIOS architecture work.
and can be different per design. The BIOS
developer for the target platform has to determine
Note:
this value.
This setting is not the same for all designs, is
Note: dependent on the architecture of BIOS. The
If FWH is set as Boot BIOS destination then PCH setting of this field must be determined by the
only supports 64 KB Top Swap block size. This BIOS developer.
value has to be determined by how BIOS
implements Boot-Block.
Quad I/O Read Enable (QIORE): This soft strap only has effect if Quad Output Yes
0 = Quad I/O Read is disabled (default) Read is discovered as supported via the SFDP
0x1F0h
3 1 = Quad I/O Read is enabled If parameter table is not detected via SFDP,
this bit has no effect and Quad I/O Read is
controlled via the Flash Descriptor Component
Section. Dual Output Fast Read Support Bit
Quad Output Read Enable (QORE): This soft strap only has effect if Quad Output Yes
0 = Quad Output Read is disabled (default) Read is discovered as supported via the SFDP
2 1 = Quad Output Read is enabled If parameter table is not detected via SFDP,
this bit has no effect and Quad Output Read is
controlled via the Flash Descriptor Component
Section. Dual Output Fast Read Support Bit
1 Dual I/O Read Enable (DIORE): this soft strap only has effect if Dual I/O Read Yes
0 = Dual I/O Read is disabled (Default) is discovered as supported via the SFDP
1 = Dual I/O Read is enabled If parameter table is not detected via SFDP,
this bit has no effect and Dual Output I/O Read
is controlled via the Flash Descriptor
Component Section. Dual Output Fast Read
Support Bit
0 Dual Output Read Enable (DORE): This soft strap only has effect if Dual Output Yes
0 = Dual Output Read is disabled (Default) read is discovered as supported via the SFDP.
1 = Dual Output Read is enabled If parameter table is not detected via SFDP,
this bit has no effect and Dual Output Read is
controlled via the Flash Descriptor Component
Section. Dual Output Fast Read Support Bit

9.161 PCH Descriptor Record 160 (Flash Descriptor Records)

Flash Address:FPSBA + F1h

Default Flash Address: 1F1h

FIT
Offset from 0 Bits Description Usage
Visible

0x1F1h 7:0 Reserved, set to ‘0’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.162 PCH Descriptor Record 161 (Flash Descriptor Records)

Flash Address:FPSBA + F2h

Default Flash Address: 1F2h

FIT
Offset from 0 Bits Description Usage
Visible

7 SPI Voltage Select (SPI_1p8volt_sel): This strap sets the internal control signal on the Yes
pad for either 1.8 or 3.3 V operation.
0 = SPI supply voltage set to 3.3 volts (default)
Note:
1 = SPI supply voltage set to 1.8 volts
The strap defaults to 1.8V mode before the soft
0x1F2h straps are loaded, i.e. before the actual supply
voltage is known. This is because the pad
performance is slightly better when assuming
1.8V when the actual is 3.3V than vice-versa.

6:0 Reserved, set to ‘0’ No

9.163 PCH Descriptor Record 162 (Flash Descriptor Records)

Flash Address:FPSBA + F3h

Default Flash Address: 1F3h

FIT
Offset from 0 Bits Description Usage
Visible

0x1F3h 7:0 Reserved, set to ‘0’ No

9.164 PCH Descriptor Record 163 (Flash Descriptor Records)

Flash Address:FPSBA + F4h

Default Flash Address: 1F4h

FIT
Offset from 0 Bits Description Usage
Visible

7 Reserved, set to ‘0’ No

0x1F4h 6:4 Reserved, default to 100b No

3:0 Reserved, set to ‘0x5’ No

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 Flash Descriptor PCH / CPU Configuration Section

9.165 PCH Descriptor Record 164 (Flash Descriptor Records)

Flash Address:FPSBA + F5h

Default Flash Address: 1F5h

FIT
Offset from 0 Bits Description Usage
Visible

7:3 Reserved, set to ‘0x10’ No

TPM Clock Frequency (STCF): This field identifies the frequency that should Yes
This field is defined with a broad range to support be used with the TPM on SPI. This field is
both SOC and PCH implementations. The listed undefined if the TPM on SPI is disabled by
frequencies are approximate. softstrap

000 = Reserved
001 = Reserved
010 = 48MHz
0x1F5h 011 = Reserved
2:0
100 = 30 MHz
101 = Reserved
110 = 17 MHz (default)
111 = reserved

Notes:
This field identifies the serial clock frequency for
TPM on SPI. This field is undefined if the TPM on
SPI is disabled either by soft-strap or fuse.

9.166 PCH Descriptor Record 165 (Flash Descriptor Records)

Flash Address:FPSBA + F6h

Default Flash Address: 1F6h

FIT
Offset from 0 Bits Description Usage
Visible

0x1F6h 7:0 Reserved, set to ‘0’ No

9.167 PCH Descriptor Record 166 (Flash Descriptor Records)

Flash Address:FPSBA + F7h

Default Flash Address: 1F7h

FIT
Offset from 0 Bits Description Usage
Visible

0x1F7h 7:0 Reserved, set to ‘0’ No

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9.168 PCH Descriptor Record 167 (Flash Descriptor Records)

Flash Address:FPSBA + F8h

Default Flash Address: 1F8h

FIT
Offset from 0 Bits Description Usage
Visible

0x1F8h 31:0 Reserved, set to ‘0’ No

9.169 PCH Descriptor Record 168 (Flash Descriptor Records)

Flash Address:FPSBA + FCh

Default Flash Address: 1FCh

FIT
Offset from 0 Bits Description Usage
Visible

7:6 Reserved, set to ‘0’ No

eSPI / EC Bus Frequency: Yes

For Slave 0 (EC/BMC): Indicates the maximum
frequency of the eSPI bus that is supported by the
eSPI Master and platform configuration (trace
length, number of Slaves, etc.). The actual
frequency of the eSPI bus will be the minimum of
this field and the Slave's maximum frequency
advertised in its General Capabilities register.

5:3
0x0 = 20MHz
0x1 = 24MHz
0x2 = 30 MHz
0x3 = 48MHz
0x4 = 60MHz (default)
05x = Reserved
0x6 = Reserved
0x7 = Reserved
0x1FCh 2 eSPI / EC Boot Enable: For setting ‘0’ the PCH (eSPI) will wait for Yes
SLAVE_BOOT_LOAD_DONE Virtual Wire to be
asserted before proceeding with the rest of the
0 = PCH will wait for EC (Slave 0) to load its boot
boot flow; EC is required to assert this VW
code via MAFS
whether or not it loads its code from PCH Flash.
1 = PCH will not wait for EC (Slave 0) to load its
boot code via MASF (default) For setting ‘1’ PCH (eSPI) will not gate its boot
flow for EC to boot its code;
EC_BOOT_LOAD_DONE is internally forced
asserted immediately.

1 eSPI / EC OOB Channel Enable: Yes

0 = OOB Channel is enabled if EC (Slave 0)

supports it (default)
1 = OOB Channel is disabled

0 eSPI / EC Peripheral Channel Enable: Yes

0 = Peripheral / LPC channel enabled if EC

(Slave 0) supports it (default)
1 = Peripheral / LPC channel is disabled

105 Intel Confidential

 Flash Descriptor PCH / CPU Configuration Section

9.170 PCH Descriptor Record 169 (Flash Descriptor Records)

Flash Address:FPSBA + FDh

Default Flash Address: 1FDh

FIT
Offset from 0 Bits Description Usage
Visible

7:5 eSPI / EC Slave Device Max Virtual Wire Yes

Channels:

0x0 = eSPI / EC set to 8 VW Channels (default)

0x1 = eSPI / EC set to 4 VW Channels
0x2 = eSPI / EC set to 2 VW Channels
0x3 = eSPI / EC set to 1 VW Channel
0x4 = Reserved
0x5 = Reserved
0x6 = Reserved
0x7 = Reserved

Note: HW max is 8, but soft-strap can force it

down for debug or otherwise.

4 eSPI / EC Slave Device Enable: Yes

0 = CS1# (Slave 1) is disabled (default)

1 = CS1# (Slave 1) is enabled

eSPI / EC Maximum I/O Mode: Yes

0x1FDh
Indicates the maximum IO Mode (Single/Dual/
Quad) of the eSPI bus that is supported by the
eSPI Master and specific platform configuration.
The actual IO Mode of the eSPI bus will be the
minimum of this field and the Slave's maximum
IO Mode advertised in its General Capabilities
3:2
register.

0x0 = Single IO Mode

0x1 = Single and Dual IO Mode
0x2 = Single and Quad IO Mode
0x3 = Single, Dual and Quad I/O (default)

1 Reserved, set to ‘0x1’ No

eSPI / EC CRC Check Enable: Yes

For Slave 0 (EC/BMC)
0
0 = CRC Checking enabled
1 = CRC checking disabled (default)

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9.171 PCH Descriptor Record 170 (Flash Descriptor Records)

Flash Address:FPSBA + FEh

Default Flash Address: 1FEh

FIT
Offset from 0 Bits Description Usage
Visible

eSPI / EC Slave Device Virtual Wire Channel Yes

Enable:
7
0 = VW Channel is enabled if EC (Slave 1)
supports it (Default)
1 = VW Channel is disabled

6 Reserved, set to ‘0’ No

eSPI / EC Slave Device CRC Check Enable: Yes

For Slave 0 (EC/BMC)
5
0 = CRC Checking enabled (default)
1 = CRC checking disabled

eSPI / EC Slave Device Maximum I/O Mode: Yes

Indicates the maximum IO Mode (Single/Dual/
Quad) of the eSPI bus that is supported by the
eSPI Master and specific platform configuration.
The actual IO Mode of the eSPI bus will be the
minimum of this field and the Slave's maximum
4:3 IO Mode advertised in its General Capabilities
register.
0x1FEh
0x0 = Single IO Mode (default)
0x1 = Single and Dual IO Mode
0x2 = Single and Quad IO Mode
0x3 = Single, Dual and Quad I/O

eSPI / EC Slave Device Bus Frequency: Yes

For Slave 0 (EC/BMC): Indicates the maximum
frequency of the eSPI bus that is supported by the
eSPI Master and platform configuration (trace
length, number of Slaves, etc.). The actual
frequency of the eSPI bus will be the minimum of
this field and the Slave's maximum frequency
advertised in its General Capabilities register.
2:0
0x0 = 20MHz (default)
0x1 = 24MHz
0x2 = 30 MHz
0x3 = 48MHz
0x4 = 60MHz
05x = Reserved
0x6 = Reserved
0x7 = Reserved

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 Flash Descriptor PCH / CPU Configuration Section

9.172 PCH Descriptor Record 171 (Flash Descriptor Records)

Flash Address:FPSBA + FFh

Default Flash Address: 1FFh

FIT
Offset from 0 Bits Description Usage
Visible

eSPI / EC Slave Device Max Read Request Yes

Payload size for OOB Channel:
This setting allows the eSPI / EC HW maximum
read request OOB payload size (128 bytes) to be
overridden for debug or other usage. All sizes
below are address aligned.

0x0 = Max Read Request size 64 bytes (default)

0x1 = Max Read Request size 128 bytes
7:5 0x2 = Max Read Request size 256 bytes
0x3 = Max Read Request size 512 bytes
0x4 = Max Read Request size 1024 bytes
0x5 = Max Read Request size 2048 bytes
0x6 = Max Read Request size 4096
0x7 = Reserved

Notes:
This encoding does NOT match the eSPI
Specifications.

eSPI / EC Slave Device Max Read Request Yes

Payload size for Peripheral Channel:
This setting allows the eSPI / EC HW maximum
read request Master Attach Flash Channel payload
size (64 bytes) to be overridden for debug or
other usage. All sizes below are address aligned.
0x1FFh
0x0 = Max Read Request size 64 bytes (default)
0x1 = Max Read Request size 128 bytes
4:2 0x2 = Max Read Request size 256 bytes
0x3 = Max Read Request size 512 bytes
0x4 = Max Read Request size 1024 bytes
0x5 = Max Read Request size 2048 bytes
0x6 = Max Read Request size 4096
0x7 = Reserved

Notes:
This encoding does NOT match the eSPI
Specifications.

eSPI / EC Slave Device OOB Channel Enable: Yes

1 0 = OOB Channel is enabled if EC (Slave 1)

supports it (default)
1 = OOB Channel is disabled

eSPI / EC Slave Device Peripheral Channel Yes

Enable:

0
0 = Peripheral / LPC channel enabled if EC
(Slave 1) supports it (default)
1 = Peripheral / LPC channel is disabled

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9.173 PCH Descriptor Record 172 (Flash Descriptor Records)

Flash Address:FPSBA + 100h

Default Flash Address: 200h

FIT
Offset from 0 Bits Description Usage
Visible

0x200h 7:0 Reserved, set to ‘0’ No

9.174 PCH Descriptor Record 173 (Flash Descriptor Records)

Flash Address:FPSBA + 101h

Default Flash Address: 201h

FIT
Offset from 0 Bits Description Usage
Visible

7 Reserved, set to ‘0’ No

eSPI / EC Max Read Request Payload size for Yes

OOB Channel:
This setting allows the eSPI / EC HW maximum
read request OOB payload size (128 bytes) to be
overridden for debug or other usage. All sizes
below are address aligned.

0x0 = Max Read Request size 64 bytes (default)

0x1 = Max Read Request size 128 bytes
6:4 0x2 = Max Read Request size 256 bytes
0x3 = Max Read Request size 512 bytes
0x4 = Max Read Request size 1024 bytes
0x201h 0x5 = Max Read Request size 2048 bytes
0x6 = Max Read Request size 4096
0x7 = Reserved

Note:
This encoding does NOT match the eSPI
Specifications.

3:1 Reserved, set to ‘0’ No

eSPI / EC Max Outstanding Request for Yes

Master Attached Flash Channel:

0
0 = Maximum of 2 outstanding requests allowed
(default)
1 = Maximum of 1 outstanding requests allowed

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 Flash Descriptor PCH / CPU Configuration Section

9.175 PCH Descriptor Record 174 (Flash Descriptor Records)

Flash Address:FPSBA + 102h

Default Flash Address: 202h

FIT
Offset from 0 Bits Description Usage
Visible

7 Reserved, set to ‘0’ No

When enabled this setting will divide eSPI clock Yes

frequency by 8.
eSPI Low Frequency Debug Override:
6 Note: This setting should only be used for
0 = eSPI Low Frequency Debug Override Enabled
debugging purposes. Leaving this
1 = eSPI Low Frequency Debug Override Disabled setting enable will impact eSPI
performance.

5:3 Reserved, set to ‘0’ No

eSPI / EC Max Read Request Payload size for Yes

Peripheral Channel:
This setting allows the eSPI / EC HW maximum
read request payload size (64 bytes) to be
overridden for debug or other usage. All sizes
0x202h
below are address aligned.

0x0 = Max Read Request size 64 bytes (default)

0x1 = Max Read Request size 128 bytes
2:0 0x2 = Max Read Request size 256 bytes
0x3 = Max Read Request size 512 bytes
0x4 = Max Read Request size 1024 bytes
0x5 = Max Read Request size 2048 bytes
0x6 = Max Read Request size 4096
0x7 = Reserved

Note:
This encoding does NOT match the eSPI
Specifications.

9.176 PCH Descriptor Record 175 (Flash Descriptor Records)

Flash Address:FPSBA + 103h

Default Flash Address: 203h

FIT
Offset from 0 Bits Description Usage
Visible

7:3 Reserved, set to ‘0’ No

eSPI / EC Max Virtual Wire Channels: Yes

Max Virtual Wire (WV) / IRQ Channel Count; HW
max is 8, however soft-strap can force it down for
debug or other usage.

0x0 = eSPI / EC set to 8 VW Channels (default)

0x203h
2:0 0x1 = eSPI / EC set to 4 VW Channels
0x2 = eSPI / EC set to 2 VW Channels
0x3 = eSPI / EC set to 1 VW Channel
0x4 = Reserved
0x5 = Reserved
0x6 = Reserved
0x7 = Reserved

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 Flash Descriptor PCH / CPU Configuration Section

9.177 PCH Descriptor Record 176 (Flash Descriptor Records)

Flash Address:FPSBA + 104h

Default Flash Address: 204h

FIT
Offset from 0 Bits Description Usage
Visible

7:4 Reserved, set to ‘0xf’ No

3 Reserved, set to ‘0’ No

0x204h
2 Reserved, set to ‘0x1’ No

1:0 Reserved, set to ‘0’ No

9.178 PCH Descriptor Record 177 (Flash Descriptor Records)

Flash Address:FPSBA + 105h

Default Flash Address: 205h

FIT
Offset from 0 Bits Description Usage
Visible

7 Reserved, set to ‘0’ No

OPI Link Width (OPDMI_LW): This setting configures the OPI Link Width. For Yes
further details see the Kabylake PCH EDS.
000 = 1 Lane
6:4
001 = 2 Lanes
010 = 4 Lanes
011 = 8 Lanes (default)

0x205h OPI Link Speed (OPDMI_TLS): This strap must be configured when setting OPI Yes
Link Speed Strap (OPDMI_STRP).
0x2 = GT2 Link Speed (default)
0x3 = GT4 Link Speed Note: This strap and the OPI Link Speed Strap
(OPDMI_STRP) must match the same GT
3:0
configuration setting for proper platform
operation function.

This setting configures the OPI Link Width. For

further details see the Kabylake PCH EDS.

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 Flash Descriptor PCH / CPU Configuration Section

9.179 PCH Descriptor Record 178 (Flash Descriptor Records)

Flash Address:FPSBA + 106h

Default Flash Address: 206h

FIT
Offset from 0 Bits Description Usage
Visible

7:6 Reserved, set to ‘0’ No

DMI Lane Reversal (DMILR): This field is used only when DMI Lanes are Yes
reversed on the layout. This
0 = DMI Lanes are not reversed.(default) usually only is done on layout constrained
boards where reversing lanes
1 = DMI Lanes are reversed.
help routing.
5

0x206h Note: This setting is dependent on the board

design. The platform
hardware designer must determine if DMI
needs lane reversal.

4 Reserved, set to ‘0’ No

3:2 Reserved, set to ‘0x1’ No

1:0 Reserved, set to ‘0’ No

9.180 PCH Descriptor Record 179 (Flash Descriptor Records)

Flash Address:FPSBA + 107h

Default Flash Address: 207h

FIT
Offset from 0 Bits Description Usage
Visible

7:1 Reserved, set to ‘0’ No

OPI Link Voltage (OPD_LVO): This strap must be configured when setting OPI Yes
Link Speed strap (OPD_LVO_STRP).
0 = 0.95 Volts
1 = 0.85 Volts (default) Note: This strap and the OPI Link Speed strap
0x207h (OPD_LVO_STRP) must match the same
0
voltage configuration setting for proper
platform operation function.

This setting configures the OPI Link Voltage.

For further details see Kabylake PCH EDS.

Intel Confidential 112

 Flash Descriptor PCH / CPU Configuration Section

9.181 Kabylake-R CPU Descriptor Record 0 (Flash Descriptor

Records)
Flash Address:FCPUSBA + 000h

Default Flash Address: 300h

FIT
Offset from 0 Bits Description Usage
Visible

31:14 Reserved, set to ‘0x0’ No

JTAG Power Disable: This setting determines if JTAG power will be Yes
maintained on C10 or lower power states.

13 0 = Disable JTAG Power for C10 and deeper states

Note: This strap is intended for debugging
(Default)
purposed only.
1 = Enable JTAG Power for C10 and deeper states

Processor Boot Max Frequency: This setting determines if the processor will Yes
operate at maximum frequency at power-on
and boot.
12 0 = Disable Boot Max Frequency
1 = Enable Boot Max Frequency (Default) Note: This strap is intended for debugging
purposed only.

Flex Ratio: This setting controls the maximum processor Yes

non-turbo ratio.

11:6 ‘0x0’ (Default)

Note: This strap is intended for debugging
purposed only. See BIOS Spec for more details
on maximum processor non-turbo ratio
configuration.
0x300h BIST Initialization: This setting determines if BIST will be run at Yes
platform reset after BIOS requested actions.
5
0 = Disable BIST at Reset (Default)
Note: This strap is intended for debugging
1 = Enable BIST at Reset purposed only.

4 Reserved, set to ‘0x0’ No

Number of Active Cores: This setting controls the number of active Yes
processor cores.

0 = All Cores active (Default)

3:1 1 = One core active
2 = Two cores active Note: This strap is intended for debugging
purposed only. See BIOS Spec for more details
3 = Three cores active
on enabling / disabling processor cores.
4 = Four cores active

Disable Hyper threading: This setting control enabling / disabling of Yes

Hyper threading.

0 0 = Enable Hyper Threading (Default)

Note: This strap is intended for debugging
1 = Disable Hyper Threading purposed only. See BIOS Spec for more details
on enabling / disabling Hyper threading

113 Intel Confidential

 Flash Descriptor PCH / CPU Configuration Section

9.182 Kabylake-R CPU Descriptor Record 1 (Flash Descriptor

Records)
Flash Address:FCPUSBA + 004h

Default Flash Address: 304h

FIT
Offset from 0 Bits Description Usage
Visible

Platform IMON Disable: Note: This strap should be left at the Yes
31 recommended default setting.

‘0x0’ (Default)

SVID Presence: This setting determine if SVID rails are present Yes
on the platform. See Processor EDS for details.
30
0 = SVID is present (Default)
1 = No SVID is present

29:25 Reserved, set to ‘0’ No

GT_S VR Type: This setting determines the GT slice domain VR Yes

type. See Processor EDS for details.
24
0 = GT slice domain VR type SVID (Default)
1 = GT slice domain VR type is fixed VR

GT_S Power Plane Topology: This setting determines the GT slice power Yes
plane topology. See Processor EDS for details.
23:20
‘0x1’ (Default)
Note: This strap should be left at the
recommended default setting.

GT_US VR Type: This setting determines the GT Unslice domain Yes

VR type. See Processor EDS for details.
19
0 = GT Unslice domain VR type SVID (Default)
1 = GT Unslice domain VR type is fixed VR
0x304h
GT_US Power Plane Topology: This setting determines the GT Unslice power Yes
plane topology. See Processor EDS for details.
18:15
‘0x1’ (Default)
Note: This strap should be left at the
recommended default setting.

Ring VR Type: This setting determines the Ring domain VR Yes

type. See Processor EDS for details.
14
0 = Ring domain VR Type SVID (Default)
1 = Ring domain VR type is fixed VR

Ring Power Plane Topology: This setting determines the Ring power plane Yes
topology. See Processor EDS for details.
13:10
‘0x0’ (Default)
Note: This strap should be left at the
recommended default setting.

IA Power Plane VR: This setting determines the IA core domain VR Yes
type. See Processor EDS for details.
9
0 = IA core domain VR Type SVID (Default)
1 = IA core domain VR type is fixed VR

IA Power Plane Topology: This setting determines the IA power plane Yes
topology. See Processor EDS for details.
8:5
‘0x0’ (Default)
Note: This strap should be left at the
recommended default setting.

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 Flash Descriptor PCH / CPU Configuration Section

FIT
Offset from 0 Bits Description Usage
Visible

SA VR Type: This setting determines the SA core domain VR Yes

type. See Processor EDS “VccSA DC
Specifications” for details.
4 0 = SA core domain VR Type SVID (Default)
1 = SA core domain VR type is fixed VR Note: SKL-S uses Fixed VR
Note: SKL-H uses SVID
0x304h
(Cont) SA Power Plane Topology: This setting determines the SA power plane Yes
topology. See Processor EDS for details.

3:0 ‘0x2’ (Default)

Note: This strap should be left at the
recommended default setting.

115 Intel Confidential

 Flash Descriptor PCH / CPU Configuration Section

9.183 Kabylake-R CPU Descriptor Record 2 (Flash Descriptor

Records)
Flash Address:FCPUSBA + 008h

Default Flash Address: 308h

FIT
Offset from 0 Bits Description Usage
Visible

SE Key Mode: Note: This strap should be left at the Yes

31:28 recommended default setting.
‘0x0’ (Default)

27:10 Reserved set to ‘0’ No

EDRAM VR Type: This setting determines the eOPIO domain VR Yes

type. See Processor EDS for details.

9 0 = EDRAM core domain VR Type SVID

1 = EDRAM core domain VR type is fixed VR
(Default)

EDRAM Power Plane Topology: This setting determines the EDRAM power Yes
plane topology. See Processor EDS for details.
0x308h 8:5
‘0x0’ (Default)
Note: This strap should be left at the
recommended default setting.

eOPIO VR Type: This setting determines the eOPIO domain VR Yes

type. See Processor EDS for details.

4 0 = eOPIO domain VR Type SVID

1 = eOPIO core domain VR type is fixed VR
(Default)

eOPIO Power Plane Topology: This setting determines the eOPIO power plane Yes
topology. See Processor EDS for details.
3:0
‘0x0’ (Default)
Note: This strap should be left at the
recommended default setting.

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10 Configuration Dependencies

10.1 Descriptor Configuration Setting Enabling Dependencies

This chapter outlines the descriptor configuration dependencies for enabling Kabylake Hardware I/O,
Bus and GPIO components.

10.1.1 High Speed IO (HSIO) Port Enabling

Below diagram provides better illustration on HSIO muxing and next table shows how to enable each
mux functionality on HSIO lane.

Note: Refer to EDS for exact number HSIO lane# supported. Some SKUs may have less HSIO lane. Get full
understanding on HSIO lane muxing architecture from EDS.

Note: GbE enabling is only allowed on the HSIO lanes shown in the diagram one at a time.

Note: SATA#1Only 1 are only allowed at one time on HSIO Lanes shown in the diagram.

The table below gives examples of how to enable each mux functionality on the HSIO lanes:

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Table 10-1. HSIO Lane Muxing Selection (Sheet 1 of 3)

HSIO Lane (Port#) Strap Offset (value) Description

Straps to decide XHCI Port 0 Ownership between

FPSBA + 0b8h[0] = 0x0
XHCI/PCIe/CSI
Lane 1 (USB P1)
Straps to decide Port 0 Ownership between
FPSBA + 0b9h[0] = 0x0
USB3/SSIC
USB3/SSIC Combo Port 1 Strap
FPSBA + 06ch[4] = 0x0
(USB3_SSIC_P1_STRP)
FPSBA + 07eh[4] = 0x0 USB3/ SSIC Combo Port 1 Strap
Lane 2 (USB P2) Straps to decide XHCI Port 1 Ownership between
FPSBA + 0b8h[1] = 0x0
XHCI/PCIe/CSI
Straps to decide Port 1 Ownership between
FPSBA + 0b9h[1] = 0x0
USB3/SSIC
USB3/SSIC Combo Port 1 Strap
FPSBA + 06ch[4] = 0x1
(USB3_SSIC_P1_STRP)
FPSBA + 07eh[4] = 0x1 USB3/ SSIC Combo Port 1 Strap
Lane 2 (SSIC P1) Straps to decide XHCI Port 1 Ownership between
FPSBA + 0b8h[1] = 0x0
XHCI/PCIe/CSI
Straps to decide Port 1 Ownership between
FPSBA + 0b9h[1] = 0x1
USB3/SSIC
USB3/SSIC Combo Port 2 Strap
FPSBA + 06ch[5] = 0x0
(USB3_SSIC_P2_STRP)
FPSBA + 07eh[5] = 0x0 USB3/ SSIC Combo Port 2 Strap
Lane 3 (USB P3) Straps to decide XHCI Port 2 Ownership between
FPSBA + 0b8h[2] = 0x0
XHCI/PCIe/CSI
Straps to decide Port 2 Ownership between
FPSBA + 0b9h[2] = 0x0
USB3/SSIC
Lane 3 (SSIC P2)
Straps to decide XHCI Port 3 Ownership between
FPSBA + 0b8h[3] = 0x0
XHCI/PCIe/CSI
Lane 4 (USB P4)
Straps to decide Port 3 Ownership between
FPSBA + 0b9h[3] = 0x0
USB3/SSIC
PCIe/USB3 Combo Port 0 Strap
FPSBA + 06eh[1:0] = 0x0
(PCIE_USB3_P0_STRP)
FPSBA + 082h[1:0] = 0x0 PCIe/USB3 Combo Port 0 Strap
Lane 5 (USB P5)
Straps to decide XHCI Port 4 Ownership between
FPSBA + 0b8h[4] = 0x0
XHCI/PCIe/CSI
FPSBA + 0b9h[4]=0x0 Straps to decide Port 4 Ownership to USB3
PCIe/USB3 Combo Port 0 Strap
FPSBA + 06eh[1:0] = 0x1
(PCIE_USB3_P0_STRP)
Lane 5 (PCIe P1) FPSBA + 082h[1:0] = 0x1 PCIe/USB3 Combo Port 0 Strap
Straps to decide XHCI Port 4 Ownership between
FPSBA + 0b8h[4] = 0x1
XHCI/PCIe/CSI

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Table 10-1. HSIO Lane Muxing Selection (Sheet 2 of 3)

HSIO Lane (Port#) Strap Offset (value) Description

PCIe/USB3 Combo Port 1 Strap

FPSBA + 06eh[3:2] = 0x0
(PCIE_USB3_P0_STRP)
FPSBA + 082h[3:2] = 0x0 PCIe/USB3 Combo Port 1 Strap
Lane 6 (USB P6)
Straps to decide XHCI Port 5 Ownership between
FPSBA + 0b8h[5] = 0x0
XHCI/PCIe/CSI
FPSBA + 0b9h[5] = 0x0 Straps to decide Port 5 Ownership to USB3
PCIe/USB3 Combo Port 1 Strap
FPSBA + 06eh[3:2] = 0x1
(PCIE_USB3_P0_STRP)
Lane 6 (PCIe P2) FPSBA + 082h[3:2] = 0x1 PCIe/USB3 Combo Port 1 Strap
Straps to decide XHCI Port 5 Ownership between
FPSBA + 0b8h[5] = 0x1
XHCI/PCIe/CSI
Lane 7 (PCIe P3) No muxing
Lane 8 (PCIe P4) No muxing
Lane 9 (PCIe P5) No muxing
Lane 10 (PCIe P6) No muxing
FPSBA + 068h[1:0] = 0x0 SATA / PCIe GP Select for Port 0

Lane 11 (SATA P0) FPSBA + 07dh[1:0] = 0x0 PCIe/SATA Combo Port 0 Strap
FPSBA + 08ch[1:0] = 0x0 SATA_PCIE_Select_for_Port_0
FPSBA + 068h[1:0] = 0x1 SATA / PCIe GP Select for Port 0

Lane 11 (PCIe P7) FPSBA + 07dh[1:0] = 0x1 PCIe/SATA Combo Port 0 Strap
FPSBA + 08ch[1:0] = 0x1 SATA_PCIE_Select_for_Port_0
Lane 12 (SATA P1) FPSBA + 068h[3:2] = 0x0 SATA / PCIe GP Select for Port 1
Note: SATA mode only FPSBA + 07dh[3:2] = 0x0 PCIe/SATA Combo Port 1 Strap
choose between Lane12
or Lane15 at one time FPSBA + 08ch[3:2] = 0x0 SATA_PCIE_Select_for_Port_1

FPSBA + 068h[3:2] = 0x1 SATA / PCIe GP Select for Port 1

Lane 12 (PCIe P8) FPSBA + 07dh[3:2] = 0x1 PCIe/SATA Combo Port 1 Strap
FPSBA + 08ch[3:2] = 0x1 SATA_PCIE_Select_for_Port_1
Lane 13 (PCIe P9) No strap for muxing
Lane 14 (PCIe P10) No strap for muxing
Lane 15 (SATA P1) FPSBA + 068h[3:2] = 0x0 SATA / PCIe GP Select for Port 1
(Only SKL-U) FPSBA + 07dh[5:4] = 0x0 PCIe/SATA Combo Port 2 Strap
Note: SATA mode only
choose between Lane12 FPSBA + 08ch[3:2] = 0x0 SATA_PCIE_Select_for_Port_1
or Lane15 at one time
FPSBA + 068h[3:2] = 0x1 SATA / PCIe GP Select for Port 1
Lane 15 (PCIe P11)
FPSBA + 07dh[5:4] = 0x1 PCIe/SATA Combo Port 2 Strap
(Only SKL-U)
FPSBA + 08ch[3:2] = 0x1 SATA_PCIE_Select_for_Port_1
FPSBA + 068h[5:4] = 0x0 SATA / PCIe GP Select for Port 2
Lane 16 (SATA P2)
FPSBA + 080h[1:0] = 0x0 PCIE/SATA Combo Port 3 Strap
(Only SKL-U)
FPSBA + 08ch[5:4] = 0x0 SATA_PCIE_Select_for_Port_2

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Table 10-1. HSIO Lane Muxing Selection (Sheet 3 of 3)

HSIO Lane (Port#) Strap Offset (value) Description

FPSBA + 068h[5:4] = 0x1 SATA / PCIe GP Select for Port 2

Lane 16 (PCIe P12)
FPSBA + 080h[1:0] = 0x1 PCIE/SATA Combo Port 3 Strap
(Only SKL-U)
FPSBA + 08ch[5:4] = 0x1 SATA_PCIE_Select_for_Port_2

10.1.1.1 Configuring PCIe on HSIO

For PCIe Controller #1:
Recommended Steps Straps

1. Configure HSIO lane to be

Refer HSIO Muxing Table
PCIe.
2. Configure PCIe lane, x1, x2
FPSBA + 09dh[4:3]
or x4

3. Configure PCIe lane Reversal FPSBA + 0E1h[2]

For PCIe Controller #2:

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Recommended Steps Straps

1. Configure HSIO lane to be

Refer HSIO Muxing Table
PCIe.
2. Configure PCIe lane, x1, x2
FPSBA + 0a5h[4:3]
or x4

3. Configure PCIe lane Reversal FPSBA + 0E9h[2]

For PCIe Controller #3:

Recommended Steps Straps

1. Configure HSIO lane to be

Refer HSIO Muxing Table
PCIe.
2. Configure PCIe lane, x1, x2
FPSBA + 0adh[4:3]
or x4

3. Configure PCIe lane Reversal FPSBA + 0F1h[2]

3. Configure PCIe lane Reversal FPSBA + 101h[2]

3. Configure PCIe lane Reversal FPSBA + 161h[2]

4. Secondary Gen3 PLL FPSBA + 0CBh[7]

10.1.1.2 Configure Intel® RST on PCIe

Configure Intel RST on PCIe Controller #2:

Recommended Steps Straps

1. Configure HSIO lane to be

Refer HSIO Muxing Table
PCIe.
00 - NAND Cycle Router A1
configured for PCIe NAND x1
2. Configure PCIe lane, to
01 - NAND Cycle Router A1
Intel RST supported lane x2 or FPSBA + 054h[3:2]
configured for PCIe NAND x2
x4
10 - NAND Cycle Router A1
configured for PCIe NAND x4
CFG1x4, 2'b11
CFG2x2, 2'b10
FPSBA + 055h[3:2]
CFG1x22x1, 2'b01
CFG4x1, 2'b00
CFG1x4, 2'b11
CFG2x2, 2'b10
FPSBA + 05Ch[3:2]
CFG1x22x1, 2'b01
CFG4x1, 2'b00

Configure Intel RST on PCIe Controller #3:

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Configure Intel RST on PCIe Controller #26:

Recommended Steps Straps

1. Configure HSIO lane to be

Refer HSIO Muxing Table
PCIe.
00 - NAND Cycle Router A1
configured for PCIe NAND x1
2. Configure PCIe lane, to
01 - NAND Cycle Router A1
Intel RST supported lane x2 or FPSBA + 054h[5:4]
configured for PCIe NAND x2
x4
10 - NAND Cycle Router A1
configured for PCIe NAND x4
CFG1x4, 2'b11
CFG2x2, 2'b10
FPSBA + 055h[5:4]
CFG1x22x1, 2'b01
CFG4x1, 2'b00
CFG1x4, 2'b11
CFG2x2, 2'b10
FPSBA + 060h[5:4]
CFG1x22x1, 2'b01
CFG4x1, 2'b00

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10.1.2 Intel® Integrated LAN Controller Enabling

If Yes:
Offset from 0 Bits Required Value Descriptor Configuration Parameter

0x144h 6:0 0x70h GbE MAC SMBus Address

0x147h 0 1b Gbe MAC SMBus Address Enable

0x149h 2:0 0x2h Reserved

0x148h 1:0 0x3h Reserved

0x17Ch 6 1b Intel Phy Over PCIe Enable

0x17Ch 5:3 Design dependent GBE PCIe* Port Select

000 = PORT3
001 = PORT4
010 = PORT5
011 = PORT9
100 = PORT10

0x193h 3 1b LC SMBus add enable GbE_ADDREN

0x193h 2 1b LCD SMBus add enable PHY_ADDREN

0x192h 7:3 0x01h Reserved

0x192h 2:0 0x3h PHY Connection

0x191h 7 0x1h Reserved

0x191h 6:0 0x70h Reserved

0x190h 7:2 0x24h Reserved

0x190h 1:0 0x3h Reserved

0x194h 2 0x1h Reserved

0x1C0h 0 0b Intel® Integrated wired LAN Enable

0x164h 7:6 01b LAN PHY Power Control GDP11 Signal Configuration
Note: For non-Intel Wired LAN, set to 00b

10.1.3 Intel® Wireless LAN Controller Enabling

If Yes:

First step, follow HSIO mux table to enable PCIe port that connect to Wireless LAN.

Set PCIe config accordingly, x1

Then set below straps.

Offset from 0 Bits Required Value Descriptor Configuration Parameter

0x164h 5 0b SLP_WLAN# / GDP9 Signal Configuration

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10.1.4 Deep Sx Enabling Dependencies

To enable:
Offset from 0 Bits Required Value Descriptor Configuration Parameter

0x100h 20 1b Deep Sx Enable

0x1BEh 4 1b DEEPSX_PLT_CFG_SS
[See Descriptor Configuration Chapter Section 9.1 for
details]

To disable:
Offset from 0 Bits Required Value Descriptor Configuration Parameter

0x100h 20 0b Deep Sx Enable

0x1BEh 4 0b DEEPSX_PLT_CFG_SS
[See Descriptor Configuration Chapter Section 9.1 for
details]

10.1.5 Intel® SMBus Enabling

To enable SMBus:
Offset from 0 Bits Required Value Descriptor Configuration Parameter

0x105h 0 1b Intel® ME SMBus Enable

®
0x107h 6:0 User input Intel ME SMBus I2C Address
®
0x108h 6:0 User Input Intel ME SMBus ASD Address
[See Descriptor Configuration Chapter Section for details]

0x109h 6:0 User Input Intel® ME SMBus MCTP Address

0x10Ah 0 1b Intel® ME SMBus I2C Address Enable. To enable = 1b

0x10Bh 0 1b Intel® ME SMBus ASD Address Enable

0x10Ch 0 1b Intel® ME SMBus MCTP Address Enable

0x10Eh 15:0 User input Intel® ME SMBus Subsystem Vendor & Device
ID for ASF [31:16]
[See Descriptor Configuration Chapter Section for details]

0x116h 1:0 11 Intel® ME SMBus Frequency

b

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10.1.6 SMLink0 Enabling Dependencies

To enable SMLink0:
Offset from 0 Bits Required Value Descriptor Configuration Parameter

0x119h 0 1b Intel® ME SMLink0 Enable

0x11Bh 6:0 User input Intel® ME SMBus I2C Address

0x11Ch 6:0 User Input Intel® ME SMBus ASD Address

[See Descriptor Configuration Chapter Section for details]

0x11Dh 6:0 User Input Intel® ME SMBus MCTP Address

0x11Eh 0 1b Intel® ME SMBus I2C Address Enable. To enable = 1b

0x11Fh 0 1b Intel® ME SMBus ASD Address Enable

0x120h 0 1b Intel® ME SMBus MCTP Address Enable

0x123h 15:0 User input Intel® ME SMBus Subsystem Vendor & Device
ID for ASF [31:16]
[See Descriptor Configuration Chapter Section for details]

0x12Ah 1:0 11 Intel® ME SMBus Frequency

b

10.1.7 SMLink1 Enabling Dependencies

To enable SMLink1:
Offset from 0 Bits Required Value Descriptor Configuration Parameter
®
0x12Dh 0 1b Intel ME SMLink1 Enable
®
0x12Fh 6:0 User input Intel ME SMBus I2C Address

0x130h 6:0 User Input Intel®ME SMBus ASD Address

[See Descriptor Configuration Chapter Section for details]

0x131h 6:0 User Input Intel® ME SMBus MCTP Address

0x132h 0 1b Intel® ME SMBus I2C Address Enable. To enable = 1b

0x133h 0 1b Intel® ME SMBus ASD Address Enable

0x134h 0 1b Intel® ME SMBus MCTP Address Enable

0x13Bh 15:0 User input Intel® ME SMBus Subsystem Vendor & Device
ID for ASF [31:16]
[See Descriptor Configuration Chapter Section for details]

0x13Eh 1:0 11 Intel® ME SMBus Frequency

b

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10.1.8 TPM over SPI Enabling Dependencies

To enable TPM over SPI,
Offset from 0 Bits Required Value Descriptor Configuration Parameter

0x178h 0 1b TPM Over SPI Bus Enable

0x1F5h User select TPM Clock Frequency

2:0 [See Descriptor Configuration Chapter Section 9.165 for
details]

To disable TPM over SPI,

Offset from 0 Bits Required Value Descriptor Configuration Parameter

0x178h 0 0b TPM Over SPI Bus Enable

10.1.9 mSATA/M.2 / SATA Express Enabling

10.1.9.1 SATA0 / PCIe7 mSATA /M.2 / SATA Express Enabling HSIO
Port 0 if to run on configurable mode by SATAXPCIE0 (e.g. mSATA/M.2 / SATA Express)
Offset from 0 Bits Required Value Descriptor Configuration Parameter

0x168h 1:0 11b SATA / PCIe GP Select for Port 0

0x17Dh 1:0 11b PCIe / SATA Combo Port 0 Strap

0x18Ch 1:0 11b SATA / PCIe Select for Port 0

0x184h 0b Polarity Select SATA / PCIe Combo Port 0

(PSCPSP_P0_STRP)
0
When SATAXPCIE0 /SATAGP0 =‘0’ - PCIe Mode
When SATAXPCIE0 /SATAGP0=‘1’ -SATA Mode

0x18Dh 0b SATA / PCIe GPIO Polarity Port 0 (SPS0)

4 When SATAXPCIE0 /SATAGP0 =‘0’ - PCIe Mode
When SATAXPCIE0 /SATAGP0=‘1’ - SATA Mode

Or

0x184h 1b Polarity Select SATA / PCIe Combo Port 0

(PSCPSP_P0_STRP)
0
When SATAXPCIE0 /SATAGP0 =‘0’ - SATA Mode
When SATAXPCIE0 /SATAGP0 =‘1’ - PCIe Mode

0x18Dh 1b SATA / PCIe GPIO Polarity Port 0 (SPS0)

4 When SATAXPCIE0 /SATAGP0 =‘0’ - SATA Mode
When SATAXPCIE0 /SATAGP0 =‘1’ - PCIe Mode

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10.1.9.2 SATA1A / PCIe8 mSATA /M.2 / SATA Express Enabling

Port 1, if to run on configurable mode by SATAXPCIE1 (e.g. mSATA /M.2 / SATA Express)
Offset from 0 Bits Required Value Descriptor Configuration Parameter

0x168h 3:2 11b SATA / PCIe GP Select for Port 1

0x17Dh 3:2 11b PCIe / SATA Combo Port 1 Strap

0x18Ch 3:2 11b SATA / PCIe Select for Port 1

0x184h 0b Polarity Select SATA / PCIe Combo Port 1

(PSCPSP_P1_STRP)
1
When SATAXPCIE1 /SATAGP1 =‘0’ - PCIe Mode
When SATAXPCIE1 /SATAGP1 =‘1’ -SATA Mode

0x18Dh 0b SATA / PCIe GPIO Polarity Port 1 (SPS1)

5 When SATAXPCIE1 /SATAGP1 =‘0’ - PCIe Mode
When SATAXPCIE1 /SATAGP1 =‘1’ -SATA Mode

Or

0x184h 1b Polarity Select SATA / PCIe Combo Port 1

(PSCPSP_P1_STRP)
1
When SATAXPCIE1 /SATAGP1 =‘0’ - SATA Mode
When SATAXPCIE1 /SATAGP1 =‘1’ -PCIe Mode

0x18Dh 1b SATA / PCIe GPIO Polarity Port 1 (SPS1)

5 When SATAXPCIE1 /SATAGP1 =‘0’ - SATA Mode
When SATAXPCIE1 /SATAGP1 =‘1’ -PCIe Mode

10.1.9.3 SATA1B / PCIe11 mSATA /M.2 / SATA Express Enabling

Port2, if to run on configurable mode by SATAXPCIE1 (e.g. mSATA /M.2 / SATA Express)
Offset from 0 Bits Required Value Descriptor Configuration Parameter

0x168h 3:2 11b SATA / PCIe GP Select for Port 1

0x17Dh 5:4 11b PCIe / SATA Combo Port 2 Strap

0x18Ch 3:2 11b SATA / PCIe Select for Port 1

0x184h 0b Polarity Select SATA / PCIe Combo Port 2

(PSCPSP_P2_STRP)
2
When SATAXPCIE1 /SATAGP1 =‘0’ - PCIe Mode
When SATAXPCIE1 /SATAGP1 =‘1’ -SATA Mode

0x18Dh 0b SATA / PCIe GPIO Polarity Port 1 (SPS1)

5 When SATAXPCIE1 /SATAGP1 =‘0’ - PCIe Mode
When SATAXPCIE1 /SATAGP1 =‘1’ -SATA Mode

Or

0x184h 1b Polarity Select SATA / PCIe Combo Port 2

(PSCPSP_P2_STRP)
2
When SATAXPCIE1 /SATAGP1 =‘0’ - SATA Mode
When SATAXPCIE1 /SATAGP1 =‘1’ -PCIe Mode

0x18Dh 1b SATA / PCIe GPIO Polarity Port 1 (SPS1)

5 When SATAXPCIE1 /SATAGP1 =‘0’ - SATA Mode
When SATAXPCIE1 /SATAGP1 =‘1’ -PCIe Mode

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10.1.9.4 SATA2 / PCIe12 mSATA /M.2 / SATA Express Enabling

Port 3, if to run on configurable mode by SATAXPCIE2 (e.g. mSATA /M.2 / SATA Express)
Offset from 0 Bits Required Value Descriptor Configuration Parameter

0x168h 5:4 11b SATA / PCIe GP Select for Port 2

0x180h 1:0 11b PCIe / SATA Combo Port 3 Strap

0x18Ch 5:4 11b SATA / PCIe Select for Port 3

0x184h 0b Polarity Select SATA / PCIe Combo Port 3

(PSCPSP_P3_STRP)
3
When SATAXPCIE2 /SATAGP2 =‘0’ - PCIe Mode
When SATAXPCIE2 /SATAGP2 =‘1’ -SATA Mode

0x18Dh 0b SATA / PCIe GPIO Polarity Port 3 (SPS3)

6 When SATAXPCIE2 /SATAGP2 =‘0’ - PCIe Mode
When SATAXPCIE2 /SATAGP2 =‘1’ -SATA Mode

Or

0x184h 1b Polarity Select SATA / PCIe Combo Port 3

(PSCPSP_P3_STRP)
3
When SATAXPCIE2 /SATAGP2=‘0’ - SATA Mode
When SATAXPCIE2 /SATAGP2 =‘1’ -PCIe Mode

0x18Dh 1b SATA / PCIe GPIO Polarity Port 3 (SPS3)

6 When SATAXPCIE2 /SATAGP2=‘0’ - SATA Mode
When SATAXPCIE2 /SATAGP2=‘1’ - PCIe Mode

§§

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FAQ and Troubleshooting

A FAQ and Troubleshooting

A.1 FAQ
Q: How do I find the Flash Programming Tool (FPT) and Flash Image Tool
(FIT) for my platform?

A: The aforementioned flash tools are included in the system tools directory in Intel®
ME FW kit. Please ensure that you download the appropriate kit for the target
platform.

Target Platform Name In VIP Kit Name

Kabylake Kabylake Platform Intel® Management Engine 11.X (use latest version)

Q: How do I build an Image for my Intel PCH based platform?

A: Kabylake PCH-LPH family based platforms, you can follow the appropriate
instructions in the FW Bringup Guide which is located in the root directory of the
appropriate Intel® ME KIT.

Q: Is my flash part supported by the Flash Programming Tool (FPT)? How can
I add support for a new flash to FPT?

A: Look at fparts.txt to see if the intended flash part is present. If the intended flash
part meets the guidelines defined in the Kabylake PCH-LP Family External Design
Specification (EDS), Intel® Management Engine (Intel® ME) Firmware SPI Flash
Requirements and support may be added to FPT by adding an entry for the part into
the Fparts.txt file.

Q: Is my flash part supported by Intel® ME Firmware? How can I add support

for a new flash to Intel® ME Firmware?

A: As long as the SPI flash devices meets the requirements defined in the Kabylake
PCH-LP Family External Design Specification (EDS), support may be added for the
device. BIOS will have to set up the Host VSCC registers. The Intel Management
Engine VSCC table in the descriptor will also have to be set up in order to get Intel®
ME firmware to work.

Adding support does not imply validation or guarantee a flash part will work.
Platform designers/integrators will have to validate all flash parts with their
platforms to ensure full functionality and reliability.

Q: Do I have to use SFDP enabled SPI flash parts?

A: Yes you will need to use SFDP enabled SPI flash parts regardless of using the VSCC
table entries Kabylake does not support VSCC only SPI flash parts.

Q: Why does FPT/verify fail for my system even when I wrote nothing to
flash?

A: Intel® ME Firmware performs periodic writes to SPI flash when it is active. Due to
this the ME region may not match the source file. There are also other system
activities beside the Intel® ME that can change the data on the flash vs the original
image. For example, the GbE check sum is updated on flash part whenever the
value is incorrect.

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Q: How can I overwrite the descriptor when FPT does not have write access?
How can I overwrite a region that is locked down by descriptor
protections? How do I write to flash space that is not defined by the
descriptor?

A: By asserting HDA_SDO (flash descriptor override strap) low on the rising edge of
PWROK, you can read, write and erase all of SPI flash space regardless of
descriptor protections. Any protections imposed by BIOS or directly to the SPI flash
part still apply. This should only be used in debug or manufacturing environments.
End customers should NOT receive systems with this strap engaged.

Q: I have two flash parts installed on the board. Why does fpt /i only show
one flash part?

A: Kabylake PCH-LP will not recognize the second SPI flash part unless it is in
descriptor mode and the Component section of the descriptor properly describes
the flash. Another possibility is that you have two different flash parts and the
second flash part is not defined in fparts.txt.

A.2 Troubleshooting
Q: I’m seeing the following error:

Intel(R) Flash Programming Tool. Version: x.x.x.xxxx

Copyright (c) 2007-2015, Intel Corporation. All rights reserved.
Platform: Intel(R) Qxx Express Chipset
Reading HSFSTS register... Flash Descriptor: Invalid

--- Flash Devices Found ---

Error: Timedout waiting for hardware to complete read operation!

S S SSFSTS register: 0x00

Error: Timedout waiting for hardware to complete read operation!

S S SSFSTS register: 0x00

Error: Timedout waiting for hardware to complete read operation!

S S SSFSTS register: 0x00

Error: Failed to read the device ID from the flash part!

A: You may be using the wrong version of FPT. Please ensure that you are using the
flash tools that were provided in the kit for the target systems.

Q: What does following FPT error message mean?

Error: The host does not have write access to the target flash memory!

A: In order for FPT to read or write to a given region, BIOS/Host must have read/write
permissions to that target region. This access is set in the descriptor. Look closely
at all the addresses defined in the output of FPT /i. If there are any gaps in flash
space defined you cannot perform a full flash write. You have to update region by
region. Refer to 4.3 Region Access Control for more information. You may have to
reflash the descriptor to get the proper access.

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FAQ and Troubleshooting

Q: What does following FPT error message mean?

Error: Flash program registers are locked! HSFSTS[15] (FLOCKDN).

A: The Flash Configuration Lock-Down (FLCOKDN) bit was set HSFS (hardware
sequencing flash status register). This locks down all the program registers in the
ICH. If your BIOS and descriptor do not set up Hardware Sequencing, you will have
to leave this bit unset in order to use FPT. You may have to upgrade the latest
version of FPT as older versions do not support Hardware Sequencing. Please refer
to Hardware Sequencing Flash Status Register in the Kabylake PCH-LP Family
External Design Specification (EDS) for the location for the HSFS. Try reflashing the
SPI device with a 3rd Party programmer. If you still see this error message, please
contact your BIOS vendor to ensure that they are not setting this bit.

Q: What does following FPT error message mean?

Error: There is no supported SPI flash device installed.

A: See the answer to the question above: Is my flash part supported by the Flash
Programming Tool (FPT)? How can I add support for a new flash to FPT?

If the tool correctly identifies the flash part installed and still gives an error
message like:

--- Flash Devices Found ---

SPI1234 ID:0x123456 Size: 4096KB (32768Kb)
Device ID: 0xFFFF not supported.

Error 405: There is no supported SPI flash device installed

This error will result when the descriptor has two flash parts defined. Edit the image
via FIT/FITC and set the number of flash components to 1.

See 6.4 Recommendations for Flash Configuration Lockdown and Vendor

Component Lock Bits for Opcodes required for FPT operation.

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