Memory Test Concepts

Abstract

Increasing numbers of analog and digital semiconductors contain large amounts of

memory circuitry. Because failures of these memories tend to dominate the
testing results of those semiconductors, and because analysis of memory failures
is an excellent tool to understand failures of other parts of these chips, it is
important for all test engineers to understand how to test memories. This
seminar is an introduction to memory test concepts that does not discuss testing
in terms of any specific tester model.

Discussion

In modern semiconductors, a large part of device circuitry is usually digital

logic, which sometimes operates on digitized analog inputs, and this circuitry
almost always includes memory arrays. Testing these memory arrays is an
essential part of testing these semiconductors. This seminar will discuss
memory test concepts.

First, what is memory?

It is digital circuitry that stores ones and zeros.

What are the characteristics of a memory?

Each memory storage location is called an address. At each address, a specific
number of bits are stored as data. Separate control signals are used decide
whether to read, write, or just retain the data.

What types of memory are there?

Volatile memory:
This is any memory that loses data when its power is turned off. This memory
type is more commonly called Random Access Memory (RAM). The two main types are
Static and Dynamic. Static RAMs (SRAMs) retain data as long as power is
applied to them. The data stored in Dynamic RAMs (DRAMs) gradually decays and
must be periodically refreshed. There are many variations of each of these
memory types. Members of the DRAM family include Synchronous DRAM, Double Data
Rate SDRAM, and Rambus (TM). The SRAM family is usually differentiated as
synchronous or asynchronous. Some speciality memory such as Content-
Addressable-Memory and multi-port memories are usually created with SRAM
circuitry.

Non-volatile memory:
This memory will retain data through periods without power. The most common
types of these memories are: ROM, EPROM, EEPROM, and flash. Read-Only-Memory is
produced with its data programmed into it and cannot be changed. Erasable
Programmable Read Only Memory is erased by exposing it to a long period of
ultraviolet light. Electrically Erasable Read-Only-Memory can be erased with an
electric signal, though that operation is slow. Flash memories are EEPROMs that
can be written faster, in a “flash”. The EEPROM and flash varieties of non-
volatile memories can be both written and read, although their reading speed
takes nanoseconds and their writing speed takes microseconds.
What is special about testing memory?

With the simplest digital circuits, you check all combinations of the inputs.
These combinations form a logic truth table. More complicated digital circuits
have specific states they can take on and specific transitions between states.
For instance, microprocessors have a set of opcodes and any other numeric value
in the opcode field is illegal. When logic for these types is designed, the
circuit design software usually creates a set of test vectors, so testing is
often not much more than using these vectors to apply inputs and compare the
device outputs to the expected outputs.

Each storage element in a memory can take on either logic level and can make any
logic transition, independent of all other storage elements. In other words,
there is no such thing as an illegal data pattern to write to or read from a
memory. Therefore, memories must be tested for all states. They must also be
tested to check that changes at one storage element do not affect any other
storage elements.

In addition, memories must be tested that they retain data. In the case of
DRAMs, there is a specification for the retention time. For SRAMs and non-
volatile memories, the retention period is infinite, which makes it harder to
test.

What is special about embedded memory test?

The term embedded memory means that the memory array is surrounded by logic
circuits, so it is not accessible under normal conditions. This is a very
common design when memory arrays are used as part of a large digital circuit.
Adding direct access to this internal memory array is rarely done, as it adds
complexity to the design and extra pins to the device packaging.

Embedded memories are tested in the same way as stand-alone memories, with the
only difference being how the embedded memory can addressed. Sometimes the
device designers provide a test mode to directly access the memory array and
sometimes logic vectors must be designed which use other on-board logic to send
the correct sequence of ones and zeros to the memory to test it. If you hear
you must test embedded memory, your first question should be how this memory
array can be accessed independent of the logic circuits surrounding it.

Why is embedded memory test important?

The yield of semiconductor devices with memory tends to be determined by the

yield of the memory arrays in those devices. That is because memory arrays have
a denser layout than analog or most digital logic. Also, all logic states and
transitions of a memory array must be functional. There are no illegal states
of a memory array.

Bitmaps, which are pictures of fails by address, are a useful tool for
understanding how to improve yield. Seeing that a single bit, or a whole row,
or other physical orientations of fails have occurred can give useful clues to
the cause of test failures.

Won't Built-In-Self-Test replace external memory testing?

The high cost of Automatic Test Equipment, which is both the cost of purchase
and the costs of operation and programming, has prompted people to look at
Built-In-Self-Test (BIST). The first characteristic of BIST is it takes up chip
area. For high volume, cost-sensitive devices, it is cheaper to offload this
task to a piece of test equipment that is amortized over all devices. Where
per-device cost is not a primary concern, using BIST may reduce the capital
costs for test equipment. The big companies that are successful in high volume
production of memory and processor chips have usually avoided lots of BIST.
Many companies have decided that BIST is a useful complement to ATE.

An important question with BIST is what test patterns it is running. Memory

testing is only as effective as the tests that are run. Perhaps the device is
designed so the BIST algorithms can be upgraded as failure modes are found in
the future? Many large companies have an engineering lab whose job is to
receive and analyze customer returns. Their work often results in new tests for
the production test program. The best BIST designs should be able to
incorporate this type of process improvement.

BIST can be run at the full operating speed of the device, which can be faster
than that of available ATE, and its speed is not limited by the need to get
signals into and out of the device under test. For this reason, adding BIST to
a device can be a good idea. Most BIST designs depend on ATE to initiate the
self test and evaluate its result.

How are memories tested?

RAMs need to write each address and read it. RAMs can have pattern sensitive
faults, which means that writing or reading some addresses can affect other
addresses. That means that not only must each address be written and read, but
that the order in which addresses are accessed is important. Memory testing is
done with patterns, which are sequences of addresses and data. ATE designed for
memory test usually includes an algorithmic pattern generator, which can
calculate addresses and data as the test is conducted, avoiding the use of
stored vectors.

Flash memories are read like RAMs, but operate differently for writing. When
the device is erased, it contains all ones. Addresses containing zeros must be
written, but addresses that should continue to be all ones are skipped. This
means flash memory testing is a series of patterns that write some addresses,
then other patterns that read the device.

Memory patterns

Memories are tested with patterns, which are sequences of addresses and data for
each address. The simplest pattern to consider is a solid zero and ones
pattern. First, each address is written to zeros, then each address is read for
zeros. Next, each address is written to ones, then each address is read for
ones. This pattern will detect stuck-at faults, but it does not guarantee that
each address can be uniquely accessed, or that data transitions at one address
do not affect other addresses.

In the 1970s, there was quite a bit of academic research into the optimum
pattern for memory test. Eventually it was concluded that there was no single
pattern that would completely test a memory. A variety of patterns are required
to find all the faults of a memory array.

Patterns are sometimes designed based on an abstract model of a memory, looking

at which data transitions can change which memory cells. Other patterns result
from an analysis of the circuitry in the memory, and others are developed as
simplified versions of real-world memory operations that failed to operate
correctly. A common question asked by people new to memory test is "what
patterns should I use?". There is not a simple answer to this question most of
the time.

Many companies have a library of patterns that have been found to be effective
in finding memory faults. Some people have experimented with pseudo-random test
patterns, though device manufacturers feel that the faults they identify can
always be also found with a non-random pattern.

Understanding the order in which memory addresses should be tested requires

knowledge of their internal layout, which should start with a discussion of
address scrambling.

Address scrambling

Memory pattern sequences of data and addressing are designed based on an

understanding of which memory cells are close to one another. For a bad oxide
layer to allow charge to leak from one transistor to another or for data
transitions to capacitively couple into another conductive path, circuit
elements must be physically near each other.

Many memories are designed with address scrambling. That means a sequentially
incrementing series of addresses delivered to the memory may not access
contiguous memory cells within the memory. Scrambling may be done to simplify
decoder design, saving silicon area. A common type of scrambling is known as
mirroring. This is when addresses numerically increase over some area of the
memory, then decrease. For instance, this address sequence illustrates
mirroring:
0 1 2 3 4 5 6 7 15 14 13 12 11 10 9 8
Mirroring may be the result of circuitry being reversed so two circuit areas can
share power or ground connections. Complicated scrambling is more common in
DRAMs, both because there are more cost pressures on DRAMs, forcing designers to
minimize silicon area. The flip-flop circuits in SRAMs can drive larger
capacitive loads than the capacitors in DRAMs, which makes it less important to
compress the physical layout of SRAMs.

Most memory pattern generators include circuitry that can be programmed with the
scrambling algorithm. When this is the case, memory patterns are designed
without considering the actual physical layout of the memory array, then the
physical scrambling information is implemented with the tester's address
scrambler.

When programming the scrambler, remember that the decoders of the memory can
result in the data being routed to a different location from what one might
expect by simply numbering the internal addresses sequentially. The tester's
address scrambler should be programmed with the reverse of this change. There
are some memories which have different scrambling schemes for different data
input/output lines. It is impossible to accommodate this during test, as only
one address is simultaneously applied to all data inputs and outputs.
It is very common for the test engineer to have trouble getting complete
scrambling information in a form that is easily usable in a test program. This
appears to be because device designers and test engineers tend to think of
memory array internal design in completely different ways. For some complicated
memories, to may be true that no single designer understands the complete
address scrambling algorithm. In these cases, as many of the designers as
needed must be interviewed. The test engineer must completely understand all
the internal scrambling.

Data topological inversion

Some memories, usually DRAMs, change the stored voltage as a function of

address. For instance, if a logic zero is written to a memory, a low voltage
will not be stored at all addresses. Instead, data is inverted as a function of
the device topology. If this is the case, it is important to compensate for it
in the memory test. Otherwise, patterns that were designed to write a one into
a background of zeros may actually be writing a one into a background of
alternating ones and zeros, so the test will not be doing what was intended.

SRAMs have two bitlines for each memory cell, one carrying true data and one
carrying complemented data (bitline and bitline bar). Some layouts reverse
these lines at various places, resulting in another example of data topological
inversion.

Memory organization

Because memories are physically organized as rectangular sections of storage

cells, the address of these cells is separated into two parts, the row and the
column. Most DRAMs input the row address first and the column address second,
though SRAMs and non-volatile memories apply row and column addresses at the
same time. Recently, some memories have been designed with several banks, which
have address lines to select them. There is no rule as to which dimension is
the row or which is the column. In addition, different people have different
standards for how rows and columns are oriented in pictures of their device
interiors. Rows can be displayed horizontally or vertically.

In DRAMs, row addresses are the word lines, which cause an entire row of cells
to be connected to their sense amps, and column addresses are bit lines, which
select which sense amplifiers are connected to the device outputs.

Some failure modes

There are a variety of ways that memories can fail and specific ways to test for
these failure modes.

Decoder failures:
There are static and dynamic decoder designs. Static decoders can have opens
which will pass patterns that sequentially increment or decrement. To detect
these fails, address sequences need to jump around. All decoders can have
faults that result in mis-addressing memories. Many patterns, including march
patterns, can detect this problem.

DRAM refresh failures:

Making sure DRAMs meet their data retention specification is important. Devices
with longer refresh periods use less power, since they can be refreshed less
frequently, so they sell at a higher price for portable applications. The
refresh time of DRAMs decreases exponentially with temperature, which means
refresh intervals must be tested at the maximum rated temperature for the
device. Room temperature testing for refresh is a waste of time. Because
electron mobility increases as temperature decreases, a different refresh
failure mechanism can appear at low temperatures. This is less commonly tested
for, since low temperature testing is difficult to do.

SRAM data retention:

The resistive pullup value in an SRAM flip-flop is 1Tohm, so the current through
it is 1pA. A little source to drain leakage can change voltages enough to flip
the stored logic state. If the transistor capacitance is 15fF, that multiplied
by 1Tohm is 15ms. That is the time it would take to change the memory cell to
full charge. If the device is operated faster than that, the stored voltage
will be reduced, causing possible loss of data. Other SRAM problems can result
from imbalances between the two transistors in the flip-flop. These problems
can be aggravated with low VDD and multiple read operations on the same address.

EPROM addressing:
There is a tendency to think of non-volatile memories as being permanent storage
that once they are written to, they can always be read, and to focus on what is
required to successfully write them. However, internal crosstalk and other
problems can affect flash and EPROM devices, so they must be tested with varying
address sequences in the same way as volatile memories.

Sense amplifier problems:

DRAMs use sense amplifiers, which detect the charge stored on the storage cell
and amplify it. One possible problem is multiple reads of one data value can
make it hard to detect the opposite data value. To see this, read lots of zeros
then read a one. Another sense amplifier problem is the transition voltage
between high and low logic levels is derived from the supply voltage. If a cell
is written with one value of VDD and read with another, there is a possibility
that the read will see a different logic level from what was written. So-called
VBUMP tests look for this problem.

Common patterns

Memory patterns are sometimes described by a formula of their execution time.

If N is the number of addresses, a pattern that writes and reads each address
will have an execution time formula of 2N. Patterns like a galpat, which read
each address alternately with all others, have a formula of N-squared. The
execution time of such patterns becomes unmanageably long as the size of the
memory increases.

Here are the names of some common memory test patterns:

March (which has many variations)

Galloping Pattern (galpat)
Sliding Diagonal
Butterfly
Moving Inversion

Pattern names are not standardized. When someone asks for a specific pattern,
it is wise to have them describe how they believe this pattern operates.
Bitmaps

A bitmap is a picture of the passing and failing addresses in the memory,

arranged to show the physical locations of each of these addresses. Because
memory arrays have a very regular layout pattern, understanding where memory
fails are located not only helps to understand the cause of these fails, but can
also serve as a process monitor for the rest of the logic circuitry on the
device. Before the memory market became so price competitive that many
manufacturers seemed to be selling devices at a loss, companies would
manufacture memories primarily to debug semiconductor fabrication processes for
their logic devices, with the sales proceeds of the memories being an additional
benefit. Today, there are companies that continue to make memories as process
debug vehicles, but they no longer bother selling the devices.

Redundancy analysis

At time of 64k dynamic RAMs, memory manufacturers began to feel that inherent
fabrication defects would affect enough devices that yields would not be
acceptable unless the memories were manufactured with extra addresses. During
test, bad rows and columns are identified, then a variety of techniques are used
to disconnect the bad rows and columns and to program to spare rows and columns
with those addresses.

Collecting the memory fail information, deciding on an appropriate analysis

algorithm, and using the results of that analysis to repair the bad memory array
is a big task which is separate from simply testing a memory.

ATE design for memory test

Many testers can be used for tasks that they are not ideally suited, given
enough programming and interface design effort. A well-designed tester has
hardware and software features to make the programming task easy. The first
characteristic of memory ATE is an algorithmic pattern generator. Some machines
test memory with a logic vector generator, which requires one vector for each
memory read or write operation. Because memory patterns often scale to the
power of the number of memory addresses, the number of vectors can far exceed
the vector size of most logic testers. With algorithmic pattern generation, the
number of vectors is not a limitation. The next limitation becomes the speed of
the pattern generation.

Hardware support for the address scrambling, data generation, and data
topological inversion are important useful tester features. An interrupt
capability for the pattern generator to satisfy DRAM refresh needs is important.

Because bitmaps are so important for failure analysis, a memory tester should be
able to store pass/fail information as a function of device address. Even
better is to retain whether each fail occurred as a result of reading a high, or
low, or both high and low. Once fail information is saved, it should be
recovered as a bitmap, which will probably display the addresses and IO
locations within the address differently from the order in which the memory was
tested.
References:

CMOS Memory Design seminar given by Zlan, Ltd., Richardson, TX

Memory Self-Test Tutorial given by R. Dean Adams, IBM at ITC 2000