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Cosc 211 Exam

The document is an examination paper for COSC 211: Digital Electronics at Chuka University, intended for second-year computer science students. It includes instructions for candidates, a compulsory section with questions on digital circuits, memory hierarchy, and data movement, as well as additional questions covering Boolean algebra, multiplexers, and shift registers. The exam is scheduled for December 3, 2018, and lasts for two hours.

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0% found this document useful (0 votes)
26 views3 pages

Cosc 211 Exam

The document is an examination paper for COSC 211: Digital Electronics at Chuka University, intended for second-year computer science students. It includes instructions for candidates, a compulsory section with questions on digital circuits, memory hierarchy, and data movement, as well as additional questions covering Boolean algebra, multiplexers, and shift registers. The exam is scheduled for December 3, 2018, and lasts for two hours.

Uploaded by

kimutaiallan16
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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COSC 211

CHUKA UNIVERSITY

UNIVERSITY EXAMINATIONS

SECOND YEAR FIRST SEMESTER EXAMINATION FOR THE AWARD OF


DEGREE OF BACHELOR OF SCIENCE IN COMPUTER SCIENCE

COSC 211: DIGITAL ELECTRONICS

STREAMS: BSC (COMPUTER SCIENCE) TIME: 2 HOURS

DAY/DATE: MONDAY 03/12/2018 8.30 A.M. – 10.30 A.M.

CANDIDATE INSTRUCTIONS

 Answer all questions in section A and any other two questions from section B.
 No Reference Material is allowed in the exam Room.
 All Mobile phones should be switched off in the exam room.

SECTION A (COMPULSORY)

QUESTION 1(COMPULSORY) [30 MARKS]

a) Using a circuit diagram, explain the operation of an SR flip flop (6 marks)

b) Below is a digital circuit. Use it to answer the question below: -

Draw the minimised product of sum of the above circuit (show the process of
conversion from SOP to POS) (6 marks)

c) Using a diagram explain the memory hierarchy of a digital computer (5 marks)

d) Convert 6 decimal to a Binary number, then write the Gray number equivalent of the
same. (4 marks)

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COSC 211
e) Explain the four basic movement of data through a shift register (4 marks)

f) A certain digital device could count number 1 up to 8 in binary numbers. Draw a


minimized circuit which will enable this device to give output of logic 1, only where
there are two consecutive ones. i.e. 011, 110 etc. (5 marks)

SECTION B (Answer two question from this section)


QUESTION 2 [20 MARKS]
a) Prove that (A + B)(A+C) = AC + AB using
i) Boolean Algebra laws (4 marks)
ii) Truth table (4 marks)

b) Below is a truth table of a combination circuit with 3-inputs w, x, y, and 2-outputs a,


b.

i) Draw the un-minimized SOP circuit of the above truth table (4 marks)
ii) Minimize the above SOP circuit (6 marks)
iii) Draw the minimized SOP circuit (2 marks)

QUESTION 3 [20 MARKS]


a) Below is a circuit of a 4 to 1 multiplexer. Use it to answer the questions below.

i) Draw the truth table of the circuit (4marks)


ii) Draw a waveform of the circuit above (4marks)

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COSC 211
b) Distinguish between sequential access and direct access methods of storage devices
(4 marks)
c) Using a Boolean logic example in each case, explain the following laws: -
i) Dominance (2 marks)
ii) Commutative (2 marks)
iii) Idempotent (2 marks)
iv) involution (2 marks)

QUESTION 4 [20 MARKS]


a) With regard to the following POS logic algebra.
Y = (A+B) (A+B+C) (B+C)

i) Minimize the logic using Karnaugh map POS (4 marks)


ii) Minimize the logic using Boolean algebra (leave your answer as POS) (3 marks)
iii) Draw the resultant minimised SOP circuit (show workings) (4 marks)

b) Explain five characteristics of a shift register (5 marks)


c) Outline FOUR differences between computer RAM and ROM (4 marks)

QUESTION 5 [20 MARKS]


a) Using the help of a truth table, explain how a half bit adder works (6 marks)

b) Explain three types of computer RAM (6 marks)

c) With the help of a circuit diagram, explain the working principles of a Serial-in to
Parallel-out shift register. (8 marks)
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