PROJECT

Report

On

ELECTRONIC VOTING MACHINE USING FPGA VERILOG

A Report Submitted to

Blackbuck Engineers Pvt.Ltd

Submitted

By

P.SRAVANI (22B95A0417)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SRKR ENGINEERING COLLEGE

(Autonomous)
ChinaAmiram (V), Bhimavaram (M), Bhimavaram – 534201.

DECLARATION

We hereby declare that the work described in this Internship report titled
“ELECTRONIC VOTING MACHINE USING FPGA VERILOG” which is being
submitted by us in partial fulfilment for the award of Bachelor of Technology in the
Department of Electronics and Communication Engineering, SRKR ENGINEERING
COLLEGE is the result of investigations carried out by us under the guidance of
MRS.DIVYA, Professor, Department of ECE, Srkr Engineering
College,Bhimavaram .
No part of the project report is copied from books/ journals/ internet and whenever
the portion is taken, the same has been duly referred. The report is based on the
project work done entirely by us and not copied from any other source. The work is
original and has not been submitted for any Degree/Diploma of this or any other
university.

Place: Bhimavaram
Date: 27-07-2024

P.SRAVANI(22B95A0417)

ACKNOWLEDGEMENT
We would like to express our sincere gratitude to Dr.S.P.V. Subba rao, Professor, Head of the
department, Electronics & Communication Engineering, Sreenidhi Institute of Science & Technology,
Hyderabad for his continued support and valuable guidance and encouragement extended to us
during our research work. We thank him for his painstaking efforts to guide us throughout our
research work.
We thank Dr.G.Ganesh professor, Dept of ECE, Sreenidhi Institute of Science & Technology,
Hyderabad for her valuable comments and suggestions that greatly helped in improving quality of
thesis.We thank to all my teachers and professors for their valuable comments after reviewing our
research papers.
We wish to extend my special thanks to all my colleagues and friends who helped directly or
indirectly to complete our research work.We extend our thanks to our parents and all our family
members for their unceasing encouragement and support who wished us a lot to complete this
work
 CONTENTS
Page No.

List of figures

Abstract

CHAPTER1 INTRODUCTION 1-2

1.1 State diagram 1-2

CHAPTER 2 EXPERIMENTAL WORK 2-3

2.1 Design Module 2

2.2 Test bench Module 2-3

2.3 Explanation of the Design Logic 3

CHAPTER 3 EXPERIMENTAL PROCEDURE 3-8

CHAPTER 4 RESULTS 8-11

4.1 RTL Schematic 8

4.2 Simulated Waveforms 9

4.3 XDC File 9

4.4 Implementation schematic 9

4.5 I/O Ports 10

4.6 Power Report 10

4.7 Utilization Report 11

CHAPTER 5 CONCLUSION 11

REFERENCES 11
 ABSTRACT

Electronic Voting machine is a simple electronic device used to record votes automatically
without the need of manual operation of ballot papers. Fundamental right to vote forms the
basis of any Democracy. In all earlier elections, voters casted their votes to their favourite
candidates by putting the stamp against his/her name. This is a long-time consuming process
and is prone to errors and can at times be an unfair process. To overcome all these difficulties
and make the electoral process a fair one, implementation of electronic voting machine in
digital domain is presented in this project. It is difficult to tamper votes in digital domain and
provides a secure and safe method for conducting elections. We all know that it is very difficult
to manipulate signals, so we have designed electronic voting machine in Verilog using XILINX
Vivado as a platform which can be implemented on FPGA (Field Programmable Gate Array)
hardware using Artix-7 family and csg324 package. Since FPGA’s have in built RAM and each
vote requires only one bit of memory, this implementation is quite memory and cost efficient.
Further, this implementation also contains password which itself is digital in nature and is very
difficult to be hacked. Conventional paper-based voting procedure was terribly long process
and extremely prone to errors. Polling by Electronic Voting Machine (EVM) is easy, safe and
secure methodology that takes minimum of our time. In order to perform this mechanism, there
were several phases in the design process such as designing a flow chart, algorithm and
simultaneously the code is developed to implement & stimulate the logic. The proposed digital
EVM was designed on Xilinx ISE using Verilog HDL and can also be implemented on FPGA
board for real time purpose. The proposed method consists of 3 stages, in the first stage we
decide the total no. of voters and the total number of contestants taking part in the election
process. we have assigned Voting enable which is active high input signal for the voter in order
to cast his vote by using voter switch input signal for making this election process more secure
and safe. In stage two, voting process begins when the voter casts his vote to a particular party
or contestants the polled vote is registered in the individual contestant registry. In stage three
after completion of voting process the votes are validated by comparing the votes polled to the
contestants in their registries after which the election process ends by declaring the winner. The
above proposed method can be implemented on FPGA board for real time applications ranging
from university level elections to Assembly and Lok Sabha elections, as it has the advantage
that it can be reprogrammed over and over for various tasks according to their requirement
which helps in reducing the expenditure.

Key words: - Electronic Voting, Elections, Vivado, XILINX, Voting, Ballot, Verilog, FPGA
 CERTIFICATE

Date: 27 July 2024

This is to certify that the project report entitled “ELECTRONIC VOTING MACHINE USING
FPGA VERILOG” is being submitted by P.Sravani (22B95A0417 in partial fulfilment of the
requirements for the award of Bachelor of Technology degree in Electronics and
Communication Engineering to Srinidhi Institute of Science and Technology affiliated to
Jawaharlal Nehru Technological University, Hyderabad (Telangana).
This record is a bona fide work carried out by them under our guidance and supervision. The
results embodied in the report have not been submitted to any other University or Institution
for the award of any degree or diploma.
.

HEAD OF DEPARTMENT
MRS.DIVYA Dr. N.VUDAY KUMAR
Professor, Professor and HoD, ECE Dept. SRKREC
ECE Department

1. Introduction
Casting a ballot is the sole criteria for picking their agents by individuals in any vote-based
system, along these lines, this whole procedure thought to be finished with most extreme
consideration so just a reasonable and meriting hopeful is chosen that is exclusively founded
on popular conclusion. In prior days, decisions were led utilizing poll paper framework
whereby individuals threw their votes to their most well-liked challenger, just, by setting stamp
against his/her name however this strategy regularly experienced different defects, for example,
taking of votes and unjustifiable outcomes [5]. To defeat every one of these disparities,
electronic casting a ballot machine was planned. Be that as it may, the plan of straightforward
electronic casting a ballot machine with removable memory card was scarce as access to
memory card for even an instant will alter all of the votes with some completely different
malignant code. So, we tend to need a frame work that might offer some better technique for
executing Electronic Voting Machine. Since we tend to understand that it is laborious to
manage control signals, hence we have structured electronic casting a ballot machine in Verilog
HDL utilizing Xilinx ISE 9.2i which can be actualized on FPGA (Field Programmable Gate
Array) equipment. Further, this execution likewise contains secret key which itself is
computerized in nature and is hard to be hacked. Polling by Electronic mechanical device
(EVM) may be a straight forward, safe and secure methodology that takes minimum of your
time. The proposed digital EVM was designed using Verilog HDL and implemented on Spartan
3 FPGA. The proposed method consists of 3 stages; in the first stage we decide the total no.
of voters and the total number of contestants taking part in the election process. We have
assigned Voting enable which is active high input signal for the voter in order to cast his vote
by using voter switch input signal for making this election process more secure and safe. In
stage two, voting process begins when the voter casts his vote to a particular party or
contestants the polled vote is registered in the individual contestant registry. In stage three after
completion of voting process the votes are validated by comparing the votes polled to the
contestants with their registries after which the election process ends. The above proposed
method can be implemented on FPGA as it has the advantage that it can be reprogrammed
over and over for different tasks, making them very cost efficient by avoiding recurring
expenses.

1.1 STATE DIAGRAM:

 Figure 1: state machine diagram

2. IMPLEMENTATION:
 in the first stage we decide the total no. of voters and the total number of contestants
taking part in the election process. we have assigned Voting enable which is active
high input signal for the voter in order to cast his vote by using voter switch input
signal for making this election process more secure and safe.
 In stage two, voting process begins when the voter casts his vote to a particular
party or contestants the polled vote is registered in the individual contestant
registry.
 In stage three after completion of voting process the votes are validated by
comparing the votes polled to the contestants in their registries after which the
election process ends by declaring the winner.
 Using Xilinx vivado we have implemented in software.
  We have observed the timing diagram, power , utilization report , how many input
and outputs are used and making the design is accurate , with cost efficient.

2.1 Design model

`timescale 1ns / 1ps

module evm(clk,voter_switch,PB,voting_en,opled,invalid,dout);

input voting_en,PB,clk;//voting process will start when vote_en is on

input [2:0]voter_switch;
output [6:0]dout;//Max no. of votes = 127
output reg [2:0]opled;//opled[0]=party1 led, opled[1]=party2 led, opled[2]=party3 led output
reg invalid;//invalid vote indicator led

//counters to count each party votes

reg [6:0]cnt_reg1=0;//party1 reg
[6:0]cnt_nxt1=0;//party1 reg
[6:0]cnt_reg2=0;//party2 reg
[6:0]cnt_nxt2=0;//party2 reg
[6:0]cnt_reg3=0;//party3 reg
[6:0]cnt_nxt3=0;//party3

reg PB_reg1; reg

PB_reg2; reg [15:0]
PB_cnt; reg PB_state;
always @(posedge clk)
PB_reg1 <= PB;
always @(posedge clk)
PB_reg2 <= PB_reg1;

wire PB_idle = (PB_state==PB_reg2);

wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's

always @(posedge clk)

if(PB_idle)
PB_cnt <= 0; // idle state i.e. PB_cnt will not increment
else begin
PB_cnt <= PB_cnt + 16'd1;
if(PB_cnt_max)
PB_state <= ~PB_state; // if the counter is maximum, PB changes end
assign PB_down = ~PB_idle & PB_cnt_max & ~PB_state;

//counter for party1 votes

always@(posedge PB_down)
if(voter_switch == 3'b001 && voting_en == 1'b1)
begin cnt_reg1 <= cnt_nxt1; end always@(*)
begin cnt_nxt1 = cnt_reg1 + 1; end
//Counter for party2 votes always@(posedge
PB_down)
if(voter_switch == 3'b010 && voting_en == 1'b1)
begin cnt_reg2 <= cnt_nxt2; end always@(*)
begin cnt_nxt2 = cnt_reg2 + 1; end

//Counter for party3 votes always@(posedge

PB_down)
if(voter_switch == 3'b100 && voting_en == 1'b1)
begin cnt_reg3 <= cnt_nxt3; end always@(*)
begin cnt_nxt3 = cnt_reg3 + 1; end

//Final count i.e. total number of votes assign dout =

cnt_reg1 + cnt_reg2 + cnt_reg3; //relation of
"voter_switch" with "opled" & "invalid"
always@(*)
if(voting_en)
case(voter_switch)
3'b100 : begin
opled = 3'b100;
invalid = 1'b0;
end 3'b010 :
begin opled =
3'b010; invalid
= 1'b0; end
3'b001 : begin
opled = 3'b001;
invalid = 1'b0;
end 3'b011 :
begin opled =
3'b000; invalid
= 1'b1; end
3'b110 : begin
opled = 3'b000;
invalid = 1'b1;
end 3'b101 :
begin opled =
3'b000; invalid
= 1'b1; end
3'b111 : begin
opled = 3'b000;
invalid = 1'b1;
end 3'b000 :
begin opled =
3'b000; invalid
= 1'b0; end
default : begin
opled = 3'b000;
invalid = 1'b0;
 end
endcase
endmodule

2.2 Testbench:

`timescale 1ns / 1ps module

evm_TB1( ); reg
voting_en; reg PB; reg clk; reg [2:0]
voter switch; wire [6:0] dout; wire
[2:0] opled; wire invalid; wire
[6:0]cnt_reg1=0; wire
[6:0]cnt_nxt1=0; wire
[6:0]cnt_reg2=0;
wire[6:0]cnt_nxt2=0; wire
[6:0]cnt_reg3=0; wire [6:0]
cnt_nxt3=0; wirePB_reg1; wire
PB_reg2; wire [15:0] PB_cnt; wire
PB_state;
evm1 dut (clk, voter_switch,PB,voting_en,opled,invalid,dout);
initial clk= 1’b0; always #5 clk = ~clk; always #5 PB=~PB;
begin
voting_en=0; voter_switch=3`b000; PB=3`b000; #10
voting_en=1; voter_switch=3`b001; PB=3`b001;
#10 voting_en=1; voter_switch=3`b001; PB=3`b001;
#10 voting_en=1; voter_switch=3`b011; PB=3`b011;
#10 voting_en=1; voter_switch=3`b001; PB=3`b001;
#10 voting_en=1; voter_switch=3`b011; PB=3`b011;
#10 voting_en=1; voter_switch=3`b001; PB=3`b001;

#10 voting_en=1; voter_switch=3`b100; PB=3`b100;

#10 voting_en=1; voter_switch=3`b011; PB=3`b011;
#10 voting_en=1; voter_switch=3`b001; PB=3`b001;
#10 voting_en=1; voter_switch=3`b011; PB=3`b011;
#10 voting_en=1; voter_switch=3`b010; PB=3`b010;
#10 voting_en=1; voter_switch=3`b010; PB=3`b010;
#10 voting_en=1; voter_switch=3`b010; PB=3`b010;
#10 voting_en=1; voter_switch=3`b010; PB=3`b010;
end end module.
2.3.DESIGN EXPLANATION:

Our voting machine works as same as electronic voting device. But there is a little bit change
we made on our voting machine. Our voting machine does not totally depend on electronic
system. We also include a punch system which performs quite similar operation like paper
ballot system does. Voting contains Tabia Hossain et al. 19 the instantiations of the other 5
modules, which are 5 separate source files of the 5 different operations. Inside Ballot module
and Control module, there are another two modules separately instantiated.We use five
different steps for our design. Firstly we have to prepare our design specification. From our
design specification we write RTL Description. Then we convert our RTL description to Gate
level design. From gate level design we go to physical layout of our design. Finally we
implement our design. These five steps work individually but finally full work depends on each
of the state. If we fail to fulfil one step, next step does not work. Though they are five different
steps and work individually, they fully depend on each other. Our Electronic Voting Machine
(EVM) works in two major units: Control Unit and Ballot Unit. The control unit counts the
individual party results as well as the total vote counts. The ballot unit makes a beep sound and
gives a green signal when a cast vote is accepted. It will also give out a punched paper for the
appropriate party. If any error occurs, the ballot unit will give a red signal indication an error
and hence, it will display an error message. Validity of a voter for a certain vote centre will be
checked at fist. Only a valid voter with a valid NID can access the machine to cast a vote. Error
can occur in three ways: firstly wrong ID encounter; secondly repetition of the same voter and
thirdly, if more than one party is pressed simultaneously. When a vote is successfully accepted,
along with the sound and the green signal, a punched paper will come out putting a seal on the
appropriate party’s logo. Individual party counts and the total counts will be monitored and
recorded successfully after each successive voting process is done. Our design of the EVM is
a Finite State Machine (FSM) approach. A finitestate machine (FSM) or finite-state automaton
is a mathematical model of computation used to sequential logic circuits and computer
programs. It is conceived as an abstract machine that can be in one of a finite number of states

3 .EXPERIMENT PROCEDURE:
Step-1: Open Vivado and Enter the “Project Name” at the desired location and Click “Next”
as shown below
 Figure 2: create new project

Step-2: Select RTL project and also click the check box “Do not specify sources at this time”
 Figure3: project type
Step-3: Select Family as “Artix-7”, Package as “csg324”, Speed as “-1” and then select the
board “xc7a100tcsg324-1” and then Click Next.

Figure4: specification selection

Click finish to create the project

Step-4: Click on “Add Sources” in Flow Navigator, then click on “Add or Create design
sources”

Figure5: add design sources

Then create a filename as per the naming the variables in verilog since it is used as the module
name then click “OK” and then click “Finish”.

Figure6: create file

name Step-5: Then click the “Port name” and the
“Direction” as per the design of the blackbox of the circuit
and then click “OK” to create the design file. But in our
project we directly clicked “OK” and gave the input-
output parameters directly in the code.

Figure 7: adding I/O ports and directions

Step-6: To create testbench module again click on “Add sources” and then click “Add or Create
simulation sources”.
 Figure8: add simulation sources

Then create a filename as per the naming the variables in verilog since it is used as the module
name then click “OK” and then click “Finish”.

4. RESULTS 4.1.
RTL SCHMANTIC:
 Figure 10: RTL schematic
4.2.TIMING DIAGRAM:

Figure 9: Timing diagram

4.3XDC FILE
4.4 IMPLEMENTATION:

Figure 11: implementation blocks

4.5 I/O PORTS
 Figure12: I/O ports specifications

4.6 .POWER REPORT:

 Figure 13: power report

4. 7.UTILIZATION REPORT:

Figure14: utilization report

5. CONCLUSION:

The Xilinx based electronic voting machine met the requirements of the election process such
as Enrolling the total no. of voters & contestants in the first stage, allowing the voter to cast his
vote to a particular party of his choice which in turn is confirmed by the opled in the second
stage. In the final stage it compares all the valid votes polled to different parties and confirm
the winner of the election. We hereby conclude that the simulated design can be readily
implemented on any FPGA board. Future Enhancement of this project involves the security
section of the EVM. The security section of the EVM is one of the main parts of the project
where each voter will hold an individual voting card and his or her finger print will be the
password. The computer will scan the identity of the voter and then the polling officer will
allow the voter to cast his, /her vote if found eligible. Our design can also be enhanced to the
PRSTV Election process which is generally used in President, Vice President and Vidhana
Parishad Elections in which the voter will cast more than one vote.

REFERENCES:

• https://www.fpga4student.com/2017/09/verilog-code-for-moore-fsm-sequencedetector.html
• .https://frontendlogic.wordpress.com/2013/12/31/verilog-code-for-mealy-and-moore1011-
sequence-detector/.
• https://www.xilinx.com
• http://studytronics.weebly.com/sequence-detectors.html
• Public Notice :PN/ECI/41/2009 INDIA, Election Commission of India(2009). Electronic Voting Machines-
regarding.
• D. Ashok Kumar and T. Ummal Sariba Begum “Electronic voting machine — A review” Pattern Recognition,
Informatics and
• Medical Engineering (PRIME), 2012,IEEE Conference 21-23 March 2012
• Hari K. Prasad , J. Alex Halderman , Rop Gonggrijp , “Security Analysis of India’s Electronic Voting
Machines” appeared in
• Proc. 17th ACM Conference on Computer and Communications Security , July 2010 Sahibzada
Muhammad Ali, Chaudhary Arshad Mehmood,Ahsan Khawja, “Micro-Controller Based Smart Electronic
Voting
• Machine System” IEEE Conference 21-22 March 2013
• Davide Balzarotti, Greg Banks, Marco Cova,”An Experience in Testing the Security of Real-World Electronic
Voting Systems”
• IEEE Transactions On Software Engineering, Vol. 36, No. 4, July/August 2010
• Handbook for presiding officers, 2008.
• http://eci.nic.in/eci_main/ElectoralLaws/HandBooks/Handbook_for_Presiding_Officers.pdf
• From Wikipedia, the free encyclopedia, the web page on Indian EVM
https://en.wikipedia.org/wiki/Electronic_voting_in_India