Release Notes

Active-HDL 7.3

Release Notes

www.aldec.com
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 TABLE OF CONTENTS

Table of Contents
What's New in Version 7.3?..........................................................................................................................4
Licensing.................................................................................................................................................4
Compiler and Simulator...........................................................................................................................4
Verilog LINT...........................................................................................................................................19
Libraries.................................................................................................................................................19
Project Management.............................................................................................................................20
Waveform Viewer..................................................................................................................................20
Signal Browser of the Accelerated Waveform Viewer.................................................................23
List Viewer.............................................................................................................................................23
Design Flow Manager............................................................................................................................24
Expression Coverage............................................................................................................................25
Toggle Coverage...................................................................................................................................26
Block Diagram Editor.............................................................................................................................26
Active-HDL Interfaces and Wizards.......................................................................................................26
Scripts....................................................................................................................................................27
Installation.............................................................................................................................................29
Problems Corrected in Version 7.3........................................................................................................29
Active-HDL™ 7.3 provides many new features and enhancements that simplify team-based design,
increase design productivity and the speed of behavioral, RTL, and timing simulation of VHDL, Verilog,
SystemC™, SystemVerilog and EDIF projects.
Active-HDL 7.3 is offered in an FPGA vendor-independent edition and supports all leading C/HDL
synthesis and implementation tools that can be started directly from the Active-HDL environment. The
installation program automatically installs all system libraries and allows selecting both target FPGA
technology and vendor-specific libraries required for running HDL simulation.
The release notes describe new options and updates available in Active-HDL 7.3. Not all features and
enhancement described are available in every product configuration or OEM edition. The product license
file provides configuration information for the features to which you have access. Please, refer to Active-
HDL Configurations for more information about available product configurations.

What's New in Version 7.3?

The following is a brief overview of new features and changes introduced to Active-HDL 7.3 (BUILD 1749,
11/20/2007)

Licensing
 Active-HDL 7.3 may require validation of your existing maintenance contract. The latest version of
License Maintenance is 2007.1000. For more information refer to the License Maintenance
section of the Licensing chapter.
 Active-HDL and VSimSA 7.3 require FLEXnet ver. 11.4.1.
 The Diagnose tool has been enhanced with a new feature that allows saving to a text file general
information about your license. In the last window of the License Diagnose wizard (Help |
Diagnose License), you can choose Save to dump the information such as your license type,
number, enabled product features, Active-HDL version, license expiration date, or the current
license status.

Compiler and Simulator

NOTE: Due to internal changes in the compiler and simulator as well as updates in third-party tool
libraries, all user-defined libraries should be re-compiled after the installation of Active-HDL 7.3. The
installation program of Active-HDL 7.3 delivers and installs only the updated system and vendor-specific
libraries that do not require re-compilation after Active-HDL 7.3 is installed.
All existing designs will not have any problems associated with re-compiling the libraries. If you update
Active-HDL to version 7.3 and do not re-compile your design libraries, the following error message will be
displayed in the Console window:

# ELBREAD: Warning: Files created by the old version of the compiler found.
# ELBREAD: Error: Library '<library_name>' has incompatible format. Recompile
all library units.

VHDL Compilation and Simulation

4 of 34 Active-HDL 7.3
  The compilation time of source files has been reduced by 40% on average in comparison to the
previous version of Active-HDL. If Active-HDL 7.3 is installed on machines with multicore CPUs,
the compilation process can be 3 times faster. Simultaneously, the performance of the timing
simulation has been increased by 10%.
 Active-HDL 7.3 introduces the support for selected VHDL 2006 (IEEE Std 1076™-2006)
extensions to the VHDL 2002 (IEEE 1076™-2002) syntax. The extensions to the standard can be
enabled by selecting the VHDL 1076-2006 option in the Standard version list box or specifying
the -2006 argument in the syntax of the acom command. Refer to Scripts for additional
information.
 The default mode of operation of the compiler has been changed from VHDL 93 to VHDL 2002.
To run compilation in the VHDL 93 mode in the command line, invoke the compiler (acom) with
the -93 argument. Refer to Scripts for additional information about the available modes of
operation of the VHDL compiler that can be specified in the command line.
In order to change the VHDL standard in the GUI, make proper selection in the Preferences,
Design Settings, or File Properties dialog box. If you need to set the VHDL standard in
command line, you can issue the vhdlstandard command in the Console window.
 The VHDL compiler can compile source files containing protected envelopes (encrypted sections
of a source code), as described in clause 22 of the draft of a new revision of IEEE-1076 (Draft
IEEE P1076/D3.4, released April 26, 2007). An encrypted source code can be safely delivered as
IP. While encrypted files are illegible to humans, it is still possible to compile and simulate them in
Active-HDL. Neither special user actions nor additional arguments in the command line are
required. The compiler automatically detects whether a source file is encrypted and decrypts
source files in the background.
For IP vendors delivering IP in the form of encrypted source files is usually more convenient than
delivering pre-compiled libraries. When pre-compiled libraries are used, a library vendor is
responsible for providing and maintaining those libraries for each version of the simulator released
on the market. As the format of libraries may change from version to version, libraries compiled
with an older version of Active-HDL cannot be used with the newer one unless they are properly
recompiled or refreshed. When encrypted source files are used, users can compile the libraries
with any version of the simulator that supports the mechanism of encryption. For more
information, refer to the Encrypted Source Files topic in the VHDL Compilation chapter in the on-
line documentation.
 Protected types are supported. Protected types were introduced in the 2002 revision of the VHDL
standard (IEEE Std 1076™-2002). The protected type combines data and routines that operate on
that data. The protected type consists of a protected type declaration and the corresponding
protected type body. An example of the protected type is shown below. The type declarations
provides four procedures (CountUp, CountDown, Reset, and Load) that control the counter and a
function (value) to read back the counter value:
type Counter is protected
procedure CountUp;
procedure CountDown;
procedure Reset;
procedure Load (N: integer);
impure function value return Integer;
end protected Counter;
The actual implementation of the subprograms is provided in the body of the protected type:
type Counter is protected body
variable cnt: Integer := 0;

procedure CountUp is
begin

Active-HDL 7.3 5 of 34
 cnt := cnt + 1;
end procedure CoutUp;

procedure CountDown is
begin
cnt := cnt - 1;
end procedure CoutDown;

procedure Reset is
begin
cnt := 0;
end procedure CoutDown;

procedure Load (N: integer) is

begin
cnt := N;
end procedure CoutDown;

impure function value return Integer is

begin
return cnt;

end function value;

end protected body Counter;
If a subprogram body in the protected type body has no corresponding declaration in the protected
type declaration, such a subprogram is visible only inside the protected type body. Similarly,
variables declared only in the protected type body are not visible outside that body.
Because all subprogram bodies appearing in the body of the Counter type are conformant with
subprogram declarations in the declaration of the Counter type, they are accessible from outside
the protected type body. Variable cnt has no corresponding declaration outside the protected type
body and is visible only inside that body. It can, however, be manipulated from the outside through
subprograms included in the Counter type.
Protected types can be used to declare shared variables only (not signals, regular variables, or
constants).
 According to IEEE Std 1076™-2002 shared variables must be declared by using protected types.
For backward compatibility, the compiler allows shared variables of scalar, composite, and access
types as well. The following warning is printed whenever such variable is declared:
Shared variable is not of a protected type.
No such warning is printed when the compiler is invoked with the -93 argument. -93 forces the
compiler to conform to IEEE Std 1076-1993. (Protected types are not supported in VHDL 93 and
shared variables must be declared as scalar, composite, or access type.)
 File types and aliases inside VHDL 2002 protected types are now supported.
 Active-HDL 7.3 allows monitoring memory leaks in VHDL dynamic allocation (i.e. memory
reserved by the VHDL new allocator). A memory leak in VHDL happens when a dynamic object is
created with the allocator and then all designators of that object are destroyed (or overwritten)
before the object is deallocated with the deallocate VHDL procedure. The object stays in memory,
however, it can no longer be accessed by the VHDL code because no designator (i.e. no variable
of the access type) designates that object. A simple example is shown below.
p1: process is
type dta_t is array (0 to 127) of integer;
type dta_ta is access dta_t;
variable v : dta_ta;

6 of 34 Active-HDL 7.3
 begin
for i in 1 to 100 loop
v := new dta_t;
-- deallocate (v);
end loop;
wait;
end process;
The for loop in the p1 process executes 100 times and allocates a new object of the dta_t type in
each iteration. The objects are never deallocated and each iteration of the loop overwrites the
reference to the object created in the previous loop iteration. When the loop completes, 100 objects
have been created but a reference exists only for the object created in the last loop iteration. Failing
to deallocate objects during simulation runtime may result in an unnecessary increase of memory
allocation and impaired simulation performance. Starting from Active-HDL 7.3, the simulator
generates a message at the end of simulation (or after the simulation restart) when the memory
occupied by undesignated dynamic objects exceeds 10MB. The value of the 10MB threshold can
be changed by setting the $ACCESS_LEAK_REPORT_THRESHOLD variable to the desired value.
It is also possible to configure the simulator to report not only the number of objects and the amount
of memory they occupy but also the locations in the source code where such objects have been
created. This can be done by specifying the -access_leak_report argument for the asim command.
Note that allocated memory in VHDL will be eventually freed by the simulator when the simulation
terminates. However, repeated leaks gradually increase memory usage. This may degrade
simulation performance or even cause a simulation runtime error when memory requested by the
new allocator cannot be obtained. Similarly, a large leak in one simulation also may be destructive
if the system runs out of memory resources.
While checking whether a designator to a dynamic object exists, the simulator does not take into
account access variables declared in subprograms. This may result in false alerts when the
simulation terminates before a subprogram using access variables and dynamic objects has
finished execution. For additional information, refer to the asim command and the Checking for
Memory Leaks in VHDL Allocation topic of the Simulation chapter in the on-line documentation.
(SPT16451)
 Active-HDL 7.3 introduces several important changes related to binding mechanisms and visibility
rules used by the compiler in the VHDL 93 mode. (Note that VHDL 93 is no longer the default
mode of operation.)
• In the previous version, the library clause made all units from the designated library visible
to the compiler, as if the clause use <library>.all; were present. Consequently, the code
below compiled cleanly provided that the en entity had been compiled to the res library.
(Note that the use clause had been commented out.)
library res;
--use res.en;
entity test is
end entity test;
architecture test of test is
begin
U1 : entity en;
end architecture test;
In Active-HDL 7.3, the compiler reports an error unless the use clause is provided.
1. Previously, all units from the work library were always visible to the compiler. The compiler
implicitly assumed that the library work; clause was specified. Because the work library is
always visible, all units from that library were visible as well. Consequently, the following code
compiled cleanly provided that the en entity existed in the work library:
entity test is

Active-HDL 7.3 7 of 34
 end entity test;
architecture test of test is
begin
U1 : entity en;
end architecture test;
Now, the compiler running in the VHDL 93 mode requires the explicit use clause, i.e.:
use work.en;
or
use work.all;
Alternatively, you can specify the library name in the instantiation statement:
U1 : entity work.en;
The compiler behavior related to visibility of units in the work library can be restored in the
VHDL 93 mode with the -relax argument. Units from the work library are also visible when
compilation is run in the VHDL 2002 mode that is now the default mode of operation. (Using
the -2002 argument of the acom command is allowed but no longer necessary.)
1. Due to the implicit library work; and use work.all; clauses, units from work, if they existed,
"overlapped" units from other libraries. In the example below, the compiler in the VHDL 93
mode would use the en unit from the work library (if it existed) despite the library and use
clauses indicating the en unit from the res library.
library res;
use res.en;
entity test is
end entity test;
architecture test of test is
begin
U1 : entity en;
end architecture test;
Starting from version 7.3, the compiler in the VHDL 93 mode will use the en unit from the res
library unless the -relax argument is used. In the VHDL 2002 mode, the unit from the work
library is used (if it exists). In other words, the visibility rules in the VHDL 2002 mode are the
same as in the "relaxed" VHDL 93 mode.
Changes to the visibility rules affect not only direct entity instantiation statements but also binding
information in configurations, package references, etc. The example below shows the test package
where the t type defined in the typedef package is used.
library res;
-- use res.typedef;
package test is
signal s : typedef.t;
end package;
In the previous version of Active-HDL, the code above compiled cleanly. Starting from version 7.3,
the compiler will error out unless you uncomment the use clause.
 The package ENV, also referred to as the standard environment package, is now available in the
STD library. The contents of the package are defined in the new draft of IEEE 1076. The package
provides a VHDL interface to the simulation environment. It contains two procedures: STOP and
FINISH and one function: RESOLUTION_LIMIT.

8 of 34 Active-HDL 7.3
 The STOP procedure pauses simulation. Simulation can be then resumed. Calling the STOP
procedure is equivalent to calling vhpi_control function in a VHPI application and passing the
vhpiStop argument to that function.
The FINISH procedure stops simulation. Simulation cannot be resumed. A call to the VHDL
FINISH procedure is equivalent to a call to vhpi_control function with the vhpiStop argument. Both
the STOP and FINISH procedures are implemented as VHPI foreign procedures.
The RESOLUTION_LIMIT function returns the simulation resolution. The returned value is of type
DELAY_LENGTH. (Type DELAY_LENGTH is defined as time range 0 fs to
time'high;.). The RESOLUTION_LIMIT function is implemented as a VHPI foreign function.
 The instance_name attribute defined in 14.1 of IEEE Std 1076™-2002 is supported. The prefix of
the attribute can be any named entity other than the local ports and generics of a component
declaration, for example: a signal name, a variable name, a process label, an instantiation label,
etc. The result of evaluating this attribute is a string starting at the root of the design hierarchy and
descending to the named entity, including the names of instantiated design entities. For example,
attribute instance_name prefixed with the p1 process label:
p1: process(I) begin
report p1'instance_name;
end process;
could be evaluated to
:testbench(testbench_arch):uut@ctl(ctl_arch):i5@inv(inv_arch):p1:
 Expressions that are not locally static can now be used in VHDL case statements and selected
signal assignment statements. To allow compilation of such expressions, use the -relax argument
of the VHDL compiler (acom) or check the Relax LRM requirements option in the Active-HDL
GUI. This setting relaxes strict LRM requirements related to static expressions and changes the
compiler error to a warning.
 Library IEEE_PROPOSED is available in the default installation. The library contains packages
that have been proposed as an extension to the IEEE library.
 The CONV_INTEGER function of the IEEE.STD_LOGIC_UNSIGNED package now prints at most
one warning regardless of the number of unknown bits contained in an STD_LOGIC_VECTOR
value passed as an argument (i.e. bits equal 'U', 'X', 'W', 'Z', or, '-'). The warning has the following
form:
CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been
converted to 0.
In previous versions of Active-HDL, a separate warning was printed for each bit.
 The Allow action and simulation callbacks option (equivalent to the -callbacks argument of the
asim command) is now obsolete and no longer required to enable VHPI action callbacks and
simulation phase callbacks.
 When compilation is run with the -incr argument, unchanged entities and package declarations are
not recompiled even if their location in a source file changes. Unchanged architectures,
configurations, and package bodies are recompiled as long as their location changes. Previously,
changing a location in a source file (e.g. by inserting new lines with comments) resulted in
recompilation of all units.

Verilog Compilation and Simulation

 The performance of both RTL and timing simulation has been increased by 10% in comparison to
version 7.2 of Active-HDL.
 Simulation of large Verilog memories was accelerated. Differences in simulation speed become

Active-HDL 7.3 9 of 34
 noticeable when the Verilog memory model requires more than 100MB of system memory to
simulate. (Memory layout is defined in IEEE Std 1364-2001; a 64MB memory modeled with an
array of 223 8-bit registers requires 128MB of system memory for simulation.) Performance gains
increase with the size of the models. A simulation of a large model controlled by a testbench
writing to memory cells in a loop may run up to 10 times faster.
 The performance of the $random system function was improved. Designs using this task
extensively may simulate up to two times faster.
 Compilation of encrypted Verilog source files has been accelerated appreciably. Compilation
times of encrypted files are now only marginally longer than compilation times of plain files.
 The behavior of the Verilog power operator (**) has been modified and now depends on the
version Verilog/SystemVerilog standard the compiler conforms to. If the compiler conforms to
IEEE Std 1364-2001 (alog -v2k), the result of the power operator is real if either an operand is real
or signed. If both operands are unsigned, the result is also unsigned. If the compiler conforms to
IEEE Std 1364-2005™ (-v2k5) or any of the SystemVerilog revisions, then the result of the power
operator is real only if either of the operands is real. The example below illustrates a possible
difference in simulation results, depending on whether the file is compiled in Verilog 2001 or
Verilog 2005 mode.
integer signed i, j;
initial begin
i = 2;
j = -2;
if (i**j)
$display ("Verilog 2001");
else
$display ("Verilog 2005");
end
In Verilog 2001, expression i**j returns a non-zero real value (0.25). In Verilog 2005, the result is an
integer and it is equal 0. Consequently, different branches of the if statement are executed
depending on how the file is compiled. Previously, the power operator behaved according to the
rules defined in Verilog 2001. Note that the power operator is not available in Verilog 95.
 The $feof system function is available. The function requires one argument (a file descriptor). It
returns 1 if the end of a file was detected during the previous read. (In other words, $feof will
return 1 only after an attempted read has failed.) Otherwise, 0 is returned. A sample while loop
using $feof as a condition is shown below:
FH = $fopen ("input.txt", "r");
while (! $feof (FH)) begin
character = $fgetc (FH);
// ...
end
The loop will execute n+1 times, where n is the input file size in bytes. The last value read by the
$fgetc will be -1 (i.e. all bits will be set to one). $feof is available in Verilog 2005 (-v2k5) and in all
SystemVerilog versions. It is not available in Verilog 95 (-v95) and Verilog 2001 (-v2k).
 The simulator can be configured to automatically suggest using the /*sparse*/ pragma for Verilog
memories that are equal or larger in size than the threshold set by the user. When simulation is
initialized, the simulator will list all memories that are larger than the threshold and declared
without the /*sparse*/ pragma. The format of the message is as follows:
Size of Verilog memory <memory_name> defined in '<file_name>:<line_number>' is larger
than <threshold - 1>. Consider using /*sparse*/ pragma.

10 of 34 Active-HDL 7.3
 The threshold is specified by using either the SparseMemorySizeSuggestion variable (it can be
defined by using the set command; the variable is not set by default) or the
SparseMemorySizeSuggestion entry in the [simulator] section in the \Bin\vsimsa.cfg configuration
file. The value is specified in the number of bytes of the system memory that the simulator needs to
allocate for the Verilog memory model. By default, the threshold is set to 0, which disables
message generation. For more information about sparse memories and when to use them, refer to
the Sparse Memories topic of the Verilog Compilation chapter in the on-line documentation.
(MAD1521)
 Delays and timing checks from specify blocks can be omitted at compile time by using the
+nospecify argument for the Verilog compiler (alog). This option may be useful when you do not
need to check the timing of the design but its functional correctness. The +nospecify argument
does not affect delays outside specify blocks nor delayed signals for negative timing checks.
 The %l and %L format specifiers are supported. Both specifiers are used to display the library
binding information.
 Unit binding performed by the Verilog compiler at the compilation stage can now be overridden at
simulation initialization with the new -PL <library_name> argument for the asim command. If a
given unit was visible to the compiler during compilation and another unit with the same name is
also available in a library specified with the -PL argument, then the unit defined by -PL
<library_name> is used for simulation. Note that this behavior is different from the behavior of the
-L argument. (The simulator resorts to libraries specified with -L only to search for units that were
neither bound by the compiler during compilation nor can be found in the library where the
simulation top-level unit is located.) The -PL argument has no influence on simulation top-level
unit(s).
 The DelayOverride$ specparam is now used only in the unit (alog +delay_mode_unit) and zero
(alog +delay_mode_zero) delay modes and ignored when the path delay mode is used (alog
+delay_mode_path). In the previous versions of Active-HDL, DelayOverride$ was used in all three
aforementioned delay modes.
 The Verilog/SystemVerilog standard can be changed not only in the GUI (i.e. in the Preferences,
Design Settings, or File Properties dialog box). If you need to set the Verilog or SystemVerilog
standard in the command line, you can issue the verilogstandard command in the Console
window.

SLP-Accelerated Verilog Compilation and Simulation

 The performance of timing simulation has been increased by 20% while simulation of a Verilog
RTL code has been accelerated by 40% on average in comparison to Active-HDL 7.2.
Performance gains are visible in designs that use constructs that were not accelerated in the
previous version of Active-HDL. In selected designs, simulation time has been reduced by a factor
of 10. Note that all Verilog '95 constructs are now accelerated by SLP.
 SLP-accelerated simulations with the write access enabled with the +access +w argument of the
asim command can now run considerably faster. (The write access is required to force values in
the simulated Verilog model using the force macro command or the Stimulators dialog box.)
Internal benchmarks have shown that the simulation time has been reduced by half on the
average with some designs simulating five times as fast as in the previous version of Active-HDL.
 The time needed to initialize simulation of designs containing a substantial number of behavioral
constructs has been reduced up to 60%.
 Design containing large Verilog memories and simulated with the read access enabled with the
+access +r argument of the asim command now run noticeably faster compared to the previous
version of Active-HDL. Previously, the use of +access +r significantly impaired simulation
performance for designs containing large memories. Note that some performance penalty when

Active-HDL 7.3 11 of 34
 using +access +r is inevitable.
 Several Verilog and SystemVerilog constructs that previously were not SLP-accelerated can now
be accelerated if SLP is enabled. They include: reading from arrays of regs and blocking
assignments to arrays of regs, non-blocking assignments to part-selections that address ranges
that could not be determined during compilation, SystemVerilog $error, $warning, and $info
functions.
 More Verilog constructs are accelerated by the SLP acceleration technology. Constructs
accelerated in this version include:
 fork/join construct
 Continuous assignments with non-constant delays
 Procedural continuous assignments
 Calls to tasks and functions located outside the current module (i.e. using hierarchical
references)
 Verilog 2001 generate statement
 Verilog 2001 implicit event expression lists ( @(*) )
 Constant selections in multidimensional arrays of nets
 Event control in intra-assignments and repeat statements
 SDF NETDELAY construct
 $countdrivers task
If you simulated your design with SLP enabled (asim -O5) and your design or the vendor libraries
you used made an extensive use of any of the above constructs, you may observe appreciable
decrease in simulation run times. Please note that performance benefits usually vary considerably
depending on the design.
 The generation of SLP models (dynamic-link libraries generated at simulation initialization) has
been refined to facilitate sharing the same model between different simulations. The
improvements affect both single and multi-user environments with all copies of Active-HDL
running on the same machine as well as setups where libraries containing SLP models are shared
across the network.
Multiple copies of Active-HDL using the same library are safeguarded against overwriting the SLP
model. If a model is already being generated by one copy of Active-HDL then all other copies that
try to generate the model in the same library will error out with the following message:
SLP: Error: Other simulation model is being generated to library <library_name>
 A previously generated SLP model can be reused even if some arguments for the asim command
change. For example, specifying a new list of PLI applications with the -pli argument no longer
forces model regeneration. If the model already exists in the library, it will be reused. Model reuse
substantially reduces the time needed to initialize simulation.
A number of arguments for the asim command does force model regeneration. The list of such
arguments is available in the Repeated Simulations in SLP chapter in the on-line documentation.
The overwhelming majority of those arguments is related to timing, parameter assignment, and
read and write access to the design. Note that in the previous releases of Active-HDL, any change
in the asim command line forced model regeneration.
 It is possible to block the initialization of simulation if the existing SLP model cannot be reused or
does not exist. This is useful if you do not want to run the model generation process when the
simulation is started but wish to use the existing model instead. If the model cannot be reused for
some reason, the simulator will error out allowing you to examine the source of the problem. The
model generation process (possibly expensive) will not be started.

12 of 34 Active-HDL 7.3
 To prevent model regeneration (and consequently, the initialization of simulation) in the situation
when the model cannot be reused, use the -reuse_model argument for the asim command. Note
that the simulator reuses the model automatically whenever -O5 is used. The -reuse_model
argument is only needed to prevent model regeneration on condition there is no model to reuse.

SystemVerilog Compilation and Simulation

 SystemVerilog classes are supported:
 Class methods, both automatic and static, are now supported.
 Static data members are now supported. Static data members can be used for event control.
 Class scope resolution operator (::) is supported.
 Functions can return an object (i.e. a class instance). Such a function can create an object,
set its properties, and then return the object, for example:
class C;
int i;
endclass
module m;
function C f;
C c;
c = new;
c.i = 1;
return c;
endfunction
endmodule
(JKT551)
See the Classes topic in the SystemVerilog chapter for the detailed list of supported class features
and known limitations.
 SystemVerilog string data type is supported. A string is an ordered collection of characters. The
length of a string may vary during simulation. If a string literal is assigned to a string variable
during simulation, the size of the variable is adjusted so that neither the literal is truncated nor the
variable is padded with zeros. A string variable is declared using the following syntax:
string str;
An initial value can be assigned to the string variable in the declaration:
string str = "initial value";
Several sample assignments to a string variable are shown below:
str = "another value";
str = {"concatenation", " of", " strings"};
str = {5{"replication "}};
The size of the variable will be adjusted automatically.
A string variable can be used in the $display statement, for example:
$display ("str = %s", str);
Additionally:
 The following string methods are supported: toupper, tolower, putc, len, getc, and icompare.
See the String Type topic in the SystemVerilog chapter for the detailed description and usage
examples.

Active-HDL 7.3 13 of 34
  The [ ] operator is supported. It allows you to read a byte from a string at a given position, for
example:
string str;
initial begin
str = "..A..";
$display ("%c(%0d)", str[2], str[2]);
end
When the initial statement shown above is executed, the simulator will print out:
A(65)
The [ ] operator can also be used on the left side of the assignment. This allows to assign a
value to any byte inside the string, for example:
str[2] = 66;
 String comparison operators ==, !=, <, >, <=, and >= are supported. The operators return 1 if
the tested condition is true or 0 otherwise. The example presenting the use of > and < is
shown below:
string str1, str2;
integer i;
initial begin
str1 = "ABC";
str2 = "abc";
i = (str1 > str2);
$display ("%0d", i);
i = (str1 < str2);
$display ("%0d", i);
end
The simulator will print out:
0
1
 String literals can be used in array assignments, for example:
byte a = "Hello";
bit [0:17][0:7]b = "Hello";
byte c[0:10] = "Hello";
byte e[0:1] = "Hello";
byte f[1:0] = "Hello";
Note that the complete string may not fit into the variable and will be truncated depending on
the variable size. (SPT14366)
 SystemVerilog packed and unpacked structures are supported.
 The packed structures are defined with the struct keyword followed by the packed keyword,
for example:
struct packed
{
reg [0:3] preamble;
reg [0:7] addr;
reg [0:63] data;
reg [0:7] crc;

14 of 34 Active-HDL 7.3
 } packet;
The above example defines a variable packed. The variable is a packed structure consisting of
four fields: preamble, addr, data, and crc. Instead of defining a variable directly, you can first
define a type using the typedef keyword and then use that type to define required variable, for
example:
typedef struct packed
{
reg [0:3] preamble;
reg [0:7] addr;
reg [0:63] data;
reg [0:7] crc;
} packet_t;

packet_t srcpacket;
packet_t dstpacket;

All fields of a packed structure are packed in memory without gaps, similarly to a vector of bit
fields. Slices of that vector can be conveniently accessed as members, for example:
chk = srcpacket.crc;
You can also access a packed structure as a vector or a vector slice.
 Unpacked structures are supported. An unpacked structure, unlike a packed structure, can
contain non-integer data fields (for example fields of type real) or unpacked arrays. The
example below defines an unpacked structure us:
struct {
real a;
reg [7:0] b;
reg [7:0] c [3:0];
} us;
This structure cannot be declared as packed because it contains two unpacked members: a
real number and an array with an unpacked dimension. (The unpacked dimensions are
specified by the indexes following the array identifier.) (MAD1626)
 Fields of structures that have no unpacked members can be initialized at declaration, for
example:
struct {
int r = 100;
int g = 50;
int b = 100;
} colors;
Active-HDL also allows field initialization in structures explicitly defined as packed. This is an
extension to IEEE 1800™-2005. (IEEE 1800™-2005 does not allow initialization of members of
packed structures.)
 A port can be declared as a packed structure, for example:
typedef struct {
int addr;
int data;
int ctrl;
} str_t;
module m (output o);

Active-HDL 7.3 15 of 34
 str_t o;
endmodule
 SystemVerilog packed unions are supported.
 A port can be declared as a packed union.
 Macro commands such as change, drivers, dumpstack, examine, and trace support objects of
the union type.
 The wait_order statement is supported. The statement suspends the execution of the process until
the specified sequence of named events occurs. If any of the events is triggered out of order, a
runtime error is reported and the process execution resumes. A simple example is shown below:
initial begin
#10; ->e1;
#10; ->e2;
#10; ->e3;
end
initial begin
wait_order (e1, e2, e3);
$display ("time = %t", $time);
end
The $display statement in the second initial block will be executed at time 30. (SPT14369)
 The expect statement is supported. It is followed by a property and an action block. The calling
process will suspend execution until the property succeeds or fails.
expect (p) $display ("Success at %0t", $time); else $display ("Failure at %0t", $time);
When property p succeeds or fails, a message is printed to the Console.
 Continuous assignments to regs are now allowed when source files are compiled in the
SystemVerilog mode, for example:
reg r;
wire w;
assign r = w;
To disable this functionality, invoke the compiler with the -v95, -v2k, -v2005, or -v2k5 argument.
The compiler will then flag such assignments as errors as required by all revisions of the Verilog
LRM (IEEE 1364-1995, IEEE 1364-2001, and IEEE 1364™-2005).
 The name method can be used with variables of the enumerated type. The name() method returns
the string representation of the given enumeration value:
enum {RED, GREEN, BLUE} color;
initial begin
color = GREEN;
$display ("== %s ==", color.name);
end
The above example will display the string GREEN.
 Array querying functions ($dimensions, $left, $right, $low, $high, $increment, and $length) have
been enhanced. The second, optional, argument specifying the number of a dimension can now
be any integer expression. Previously, the dimension could be specified only with a compile time
constant.
 Event triggered property is supported. The triggered property evaluates to true if the event has
been triggered in the current simulation time. Otherwise it is false. The property can be used in
wait statements:

16 of 34 Active-HDL 7.3
 wait (<eventname>.triggered)
The <eventname>.triggered property remains true throughout the time step. This allows to avoid
race conditions such as the race shown in the listing below.
fork
@(e);
->e;
join
The fork-join statement may or may not complete depending on the order of execution of ->e and
@(e) statements. (The simulator is allowed to execute those statements in an arbitrary order.) The
example re-written using the e.triggered property is shown in the listing below:
fork
wait(e.triggered);
->e;
join
The wait(e.triggered) statement (contrary to the @(e) statement) will never block because the
e.triggered property remains true throughout the time step, regardless of the order of execution of
the statements in the fork-join block.
 The SystemVerilog unique and priority keywords are supported in the if and case selection
statements.
The unique keyword in the if statement indicates that the conditions in the statement are mutually
exclusive and can be safely evaluated in parallel. If more than one condition evaluates to true, the
simulator reports an error. The simulation continues even though an error has been reported.
The unique keyword in the case statement indicates that no more than one choice in the
statement matches. If it does, the simulator reports an error without interrupting the simulation. If
overlapping choices in the statement can be detected at the compilation stage, the appropriate
warning is also generated by the compiler when the file is compiled.
The priority keyword can be a hit for synthesis tools. It indicates that a series of if else conditions
or case choices should be evaluated in the order listed. If more than one condition is true or more
than one choice matches, priority logic may be required.
When either the unique or priority keyword is used, the simulator issues a warning if no condition
is true or no choice matches the expression. (LRM 10.4)
 Non-blocking event triggers are supported. The non-blocking event triggers are created with
operator ->>, for example:
->> ev;
The above statement executes without blocking and creates an assign update event. The non-
blocking event trigger can include a delay statement, for example:
->> #10 ev;
It can also be controlled by another event, for example:
->> @(clk) ev;
 Syntax for passing arguments to functions and tasks has been extended. The arguments can now
be bound not only by position but also by name or with a mixed by name and by position binding
(LRM 12.4.4). Additionally, arguments can be bound with .*, similar to module ports. Function f_or
that accepts two arguments a and b, could be invoked as follows:
initial
begin
c = f_or (.a(1), .b(1));
d = f_or (1, .b(1));

Active-HDL 7.3 17 of 34
 e = f_or (.a(a), .b(b));
f = f_or (.*);
end
 The input keyword is optional in tasks and functions. If no direction is specified for an argument,
that argument is assumed to be an input. (LRM 12.2)
 Some SystemVerilog types (bit, logic, int, shortint, longint, byte, enum, and shortreal) can
now be recorded to VCD files. SystemVerilog types are mapped to Verilog types. The file format
itself has not been extended. The type mapping between SystemVerilog types and Verilog types
is provided in section 24.2 of IEEE Std 1800™-2005.
 SystemVerilog 2-state types can now be accessed by PLI applications.

SystemC/SCV Compilation and Simulation

 The SystemC distribution delivered with version 7.3 has been updated from SystemC 2.1 to
SystemC 2.2. Active-HDL 7.3 is no longer compatible and cannot be used with SystemC 2.1.
SystemC designs that used deprecated SystemC 2.1 features may require an update before they
can be simulated in Active-HDL 7.3 and the SystemC 2.2 library. SystemC libraries and header
files are located in the \Systemc subdirectory of the Active-HDL installation directory.
 A SystemC signal can be written by only one process. If two or more processes write to the same
signal, a runtime error is reported. The check of multiple writes to the same signal by multiple
processes can be disabled by setting the value of the $SC_SIGNAL_WRITE_CHECK variable to
disable. This can be done either in the Active-HDL command line or in the OS environment. If
either of the variables is set, the check is disabled. To disable the check in the Active-HDL
environment, issue the following command:
set SC_SIGNAL_WRITE_CHECK disable
The variable can also be set to 0 or false. (All three values are equivalent; the size of characters
does not matter.) To re-enable the check, set the value of the $SC_SIGNAL_WRITE_CHECK
variable to any value other than disable, 0, or false. The variable must be set before simulation is
initialized. Any changes at simulation run time do not take effect until simulation is restarted.
If the variable is set in the OS environment when Active-HDL starts (and its value equals disable,
0, or false), the write check will be disabled regardless of the value of the
$SC_SIGNAL_WRITE_CHECK variable set in Active-HDL.
 Several SystemC functions are now considered deprecated. When a deprecated function, for
example sc_simulation_time() is used, the simulator may output the following message during
simulation:
SYSTEMC: Info: (I804) /IEEE_Std_1666/deprecated: sc_simulation_time() is deprecated use
sc_time_stamp()
 The wait_until() and delayed() functions are no longer included in the SystemC library. A code
using these functions must be re-written. For example, the following statement referring to the
dta_req signal declared as sc_signal <bool>
wait_until( dta_req.delayed() == true );
can be replaced by:
do wait(); while( !dta_req );
Both functions were removed from the SystemC 2.2 library and code using either wait_until() and
delayed() will not compile. Note that neither of the two functions is included in IEEE 1666™-2005. If
you want to leave your legacy SystemC 2.1 code intact, you can use the #if and #else if
preprocessor commands and defines from the sc_ver.h file to differentiate between SystemC 2.1
and SystemC 2.2 code.

18 of 34 Active-HDL 7.3
  The algorithm for synchronizing SystemC modules and HDL modules in mixed SystemC-HDL
simulations has changed. In the previous version of Active-HDL, a SystemC module could
execute multiple SystemC delta cycles before synchronizing with HDL modules. Starting from
version 7.3, the synchronization is truly event based.
The new algorithm may cause differences in delta cycle counts compared to the previous versions
of Active-HDL. For some designs, simulation results also may be affected.
 The command line options for SystemC models can be passed with the -sc_arg argument of the
asim command. The argument can be used multiple times, once for each SystemC option.
Command-line options can be accessed from SystemC with sc_argc() and sc_argv() functions.
 The following port types are now supported at the HDL/SystemC boundary: sc_fixed_fast,
sc_ufixed_fast, and signed char.
 SystemC objects of type real, sc_fixed, sc_ufixed, sc_fixed_fast, and sc_ufixed_fast can now be
recorded to a simulation database (*.asdb).
 The size of design libraries containing SystemC modules has been reduced.

Verilog LINT
The severity level of messages generated by the Verilog LINT engine can be changed and LINT
messages can be filtered. To change the severity level for a given warning, use the -err argument
for the Verilog compiler. The argument should be followed by the LINT message ID and the
required severity level, for example:
alog -err LINT_2003 W9 -lintcs gates.v
The command above changes the severity level of the LINT_2003 warning (i.e. Module name is
different from file name) to the lowest possible level (W9). By default, the messages with a level of
W6 through W9 are not printed on the compiler output. (This behavior can be modified with the
-msg argument.)
To raise the severity of the LINT_2003 warning to an error, use the following command:
alog -err LINT_2003 E -lintcs gates.v
The compiler will now error out and exit when reporting LINT_2003. Note that the mechanism for
altering the severity level of LINT warnings is the same as the mechanism used for compiler
warnings (i.e. warnings with identifiers starting with the VCP string).

Libraries
 VHDL units compiled with the -multiplatform argument of acom (or the Generate multiplatform
library option checked) on either x86 or x86_64 architecture are now portable between x86 and
x86_64 architectures.
 Verilog units compiled with the -multiplatform argument of alog are now portable between x86,
x86_64, and SPARC architectures. Previously, multiplatform Verilog units were portable only
between x86 and SPARC architectures.
 The library refresh feature now works smoothly with multiplatform library units. A library with
multiplatform units refreshed on a supported architecture (x86, x86_64, SPARC) retains its
multiplatform functionality. In the previous release of Active-HDL, library units were no longer
multiplatform after library refresh was performed.
 The Library Manager provides now more details about functions declared in packages. Starting
from version 7.3, if a package contains a function declaration, the Library Manager also displays

Active-HDL 7.3 19 of 34
 the arguments of the function and a type
Additionally, the following changes have been introduced to the system and vendor-specific libraries
delivered with the installation program of Active-HDL 7.3:
 Updated Libraries

HDL Synthesis
1. Synplicity FPGA Synthesis 8.9

Implementation
1. Actel Designer 8.0 SP3
2. Altera Quartus II 7.2
3. Lattice ispLEVER 7.0 SP1
4. QuickLogic QuickWorks 9.9
5. Xilinx ISE 9.2i SP3, IP Update 2
 Removed Libraries
Implementation
1. Cypress WARP 6.3 SP1 (CYPRESS, PRIMITIVE, OVI_CYPRESS, CYPRESS_VERILOG)
2. Xilinx Triscend FastChip 3.0 (TRISCEND, OVI_TRISCEND)
NOTE: For the complete list of all the pre-compiled vendor libraries delivered with Active-HDL 7.3, refer to
the Vendor-Specific Libraries chapter.

Project Management
 Active-HDL 7.3 introduces a change in management of files attached as links to the active design.
Now, the original location of a linked file can be referenced in your design (*.adf) by using either
absolute or relative paths. By default, Active-HDL 7.3 uses relative paths for links. The use of the
relative paths fully enables design portability, i.e. it allows using and opening third-party
documents, compiling, and simulating your design on another computer or design directory. The
manner of managing the links can be globally modified by the Use relative paths for files added
as links option available in the Design Browser category of the Preferences dialog box. Note
however that the absolute paths are always used when design resources are stored on another
drive (local or network) while files attached to the design and located within $DSN always use the
relative paths. For additional information on how to continue working with designs created in the
previous version(s) of Active-HDL, refer to the description of the Design Browser category in the
Preferences Dialog Box topic.
 Specifying compilation options for multiple HDL files selected on the design tree displayed in the
Design Browser window has been enabled. Now, except for selecting a destination library for a
group of source files, you can also define common compiler settings for both Verilog and VHDL
sources. The common compilation options for the selected files can be set in the Compile tab of
the File Properties dialog box. For more information, refer to the description of the File
Properties dialog box and the Specifying Destination Library and Compiler Settings section of the
Design Browser - Files Tab chapter in the on-line documentation.

Waveform Viewer
 Active-HDL continuously enhances functionality and significantly increases performance of built-in
waveform viewers. In version 7.3, except for the Standard Waveform Viewer/Editor, the full

20 of 34 Active-HDL 7.3
 integration with the new and high-performance Accelerated Waveform Viewer is offered. The
Accelerated Waveform Viewer, formerly known as the separate and stand-alone application
started from the Tools menu (still available), is now an integral part of the Active-HDL framework
and it can be used to present simulation data stored in the binary simulation database (*.asdb)
similarly to the lower performance feature-rich Standard Waveform Viewer/Editor displaying
simulation results saved in the *.awf text file.
By default, the Accelerated Waveform Viewer is enabled and the *.asdb simulation database is
created on initialization of simulation. The type of the waveform viewer can be changed globally
for the entire Active-HDL environment in the Default waveform viewer/editor list box in the
Waveform Editor/Editor category of the Preferences dialog box or by using the waveformmode
command. The change of the waveform viewer is possible prior to initializing your simulation
session. When simulation is running, the Default waveform viewer/editor list box is disabled and
issuing the waveformmode command returns an error in the Console window.
The waveform viewers have separate preferences available in the Standard Waveform
Viewer/Editor and Accelerated Waveform Viewer subcategories. Both the viewers are
integrated with the common Active-HDL framework and they can interact with other Active-HDL
built-in tools. Waveform objects presented in both the viewers can be added in the same way, i.e.
by dragging objects to the waveform window, by using the Add to Waveform option of the pop-up
menu, or the wave macro command. Both the waveform viewers share the Waveform menu.
However, the content of the menu depends on the currently enabled waveform viewer. For more
information refer to the Waveform Viewer | Accelerated Waveform Viewer chapter.
Apart from the direct integration with the Active-HDL GUI, in the comparison to the functionality
available in the previous version of the stand-alone viewer, the Accelerated Waveform Viewer of
Active-HDL 7.3 provides the following new features and enhancements:
 The viewer can be now configured to open an empty waveform window without displaying any
signal while loading the simulation database. After that, you may run a macro containing a series
of add wave commands inserting signals from the *.asdb file to the waveform window. Instead,
you can also configure the Accelerated Waveform Viewer to open the Signal Browser.
(SPT14711)
 Signals can be arranged together to form a virtual group. A virtual group can be manipulated as a
single object in the viewer. You can expand or collapse a group, add more signals to an existing
group, remove signals from it, delete a group, or ungroup selected signals. A virtual group can be
created by selecting required signals in the waveform window and choosing the Create Virtual
Group command from the pop-up menu. Virtual groups can also be created with the add wave
command used with the new -vgroup argument. For more information on virtual groups, refer to
the Grouping Signals chapter in the on-line documentation and the add wave command.
 The Value column in the Signal Grid pane shows not only values but also value changes. Values
of signals that changed at the time where the timing cursor is placed are shown in red using the
<old_value> to <new_value> notation, for example 0 to 1. To restore the old way for displaying
values, clear the Show events in the value column check box in the Waveform Preferences
dialog. Once the check box is cleared, the Value column will show only one value. (If there is an
event at the time where the cursor is located, only the new value be shown.)
Because the new notation occupies more space, the Value column alignment was changed from
left to right. At any time, you can change the alignment manually by selecting an appropriate
setting in the Columns tab of the Waveform Preferences dialog box.
 The Signal name column can now display the hierarchy path. To change the default behavior (by
default, this column displays only an object name and a hierarchical path is shown in the
Hierarchy column), check the Show hierarchy in the Signal Name column option in the
Waveform Preferences dialog box. The Hierarchy column can be turned on or off irrespective of
this setting.
 A new preference is available for setting the color of text in a named row during renaming. The
color can be specified globally on the Colors tab in the in the Waveform Preferences dialog box

Active-HDL 7.3 21 of 34
 by setting the Signal editing text color preference. In the previous version, no such preference
was available and the named row name could be invisible during renaming, depending on how
other color preferences were set. (SPT15230)
 Multiple analog waveforms can be displayed within the same signal area overlaying one another.
To make the waveforms overlap, select desired signals in the viewer, right-click, and select the
Create Analog Overlay Bus command from the pop-up menu. After an analog overlay bus is
created you can show its members by clicking the plus icon in front of the bus name and set their
display properties in the Signal Properties dialog box. Changes in the display properties (bold
and color) will be reflected in the overlay bus. For more information refer to the Analog Overlay
Buses topic in the Waveform Viewer | Accelerated Waveform Viewer chapter. (SPT15386)
 Parts of analog waveforms that have been clipped are now marked with the red color. An analog
waveform can be clipped if the values it displays do not fit in the specified range. (The range for
analog values can be set in the Signal Properties dialog box, individually for each signal.) If top
values are clipped, the red line appears on top of the waveform. If bottom values are clipped, the
red line is displayed at the bottom.
 The range of values displayed for signals in an analog shape can be specified with real numbers.
In the previous version, the range of values could be specified with integer numbers only. This
was inconvenient when observing signal values within a range less than 1. For example, to
display values from within (-0.1, 0.1) range you had to set the value range to (-1, 1). In the current
version, you can specify the value range by using fractional parts and set the low limit to -0.1 and
the high limit to 0.1. (SPT14832)
 The optimal range of values for a signal displayed by using an analog shape can be calculated
automatically. To calculate the range, right-click on the signal, select Properties from the pop-up
menu, and click on the Auto-calculate Range button in the Display tab. (SPT14833)
 When the list of signals displayed in the waveform viewer is saved to a macro with the Waveform
| Save to Macro command, the -analog argument for the wave command is now added
automatically for each signal with the display mode set to Analog. (Previously, this argument was
omitted. Therefore, when the macro was run, buses were always shown using the default Literal
display mode.) Additionally, macros can now pass more information about signal properties, e.g.
the preferred range of analog waveforms or bit order in vector signals. (SPT14975)
 Radix (e.g. the binary or hexadecimal radix) can be set for VHDL signals of type integer. In the
previous version, such signals were always shown using the decimal radix. (SPT15277, MIP3662)
 The search for values specified with the value#radix notation in the Find dialog box works for both
vector and scalar values. Previously, only vector values were located and scalar values (e.g.
VHDL integers) were omitted.
 You can now use X and Z values when searching for hexadecimal values. For example, entering
16#FZ in the Find edit box allows you to locate value 1111ZZZZ on an eight-bit vector signal.
Note that the Z in 16#FZ matches only if all the four neighboring bits are set to Z. When searching
for values of the STD_LOGIC_VECTOR type (or any other related types), you can also specify
other values of the STD_LOGIC type, i.e. U, W, L, H, and -.
 The radices of the values displayed by the Accelerated Waveform Viewer are synchronized
between any two compared signals. The viewer displays compared signals in pairs, one over the
other. Changing the display radix in the Signal Properties dialog box affects both signals. In the
previous version of Active-HDL, the radix was changed only for the signal from the original
simulation database and changing the radix had no effect on the signal coming from the second
simulation database.
 Applying the bold property now changes not only an object in the Waveform pane but also a name
of an object. (The signal waveform is drawn using a thick line; the signal name is shown in the
boldface.)

22 of 34 Active-HDL 7.3
  The Accelerated Waveform Viewer preserves the zoom factor after simulation is restarted.
(SPT15122)
 The height of named rows can now be changed. (SPT15229)
 Two new keyboard shortcuts have been added to the Accelerated Waveform Viewer. Ctrl+J
creates an analog overlay bus. Ctrl+* (Ctrl and the asterisk on the numeric keyboard) adjusts the
zoom factor so that the complete simulation range is shown. (SPT16512)
For more information on using the waveform viewers, their functionality, available features, and
command line support refer to the Standard Waveform Viewer/Editor and Accelerated Waveform
Viewer chapters, respectively.

Signal Browser of the Accelerated Waveform Viewer

 The Signal Browser built-in to the Accelerated Waveform Viewer is a new dedicated tool that
complements the viewer and allows browsing signals recorded to a simulation database (*.asdb).
The Signal Browser can be started either while opening the simulation database or later on to
display signals recorded in the database but initially invisible in the Accelerated Waveform Viewer:
 You can configure the Accelerated Waveform Viewer to start the Signal Browser whenever
the database is loaded. Instead of presenting all signals found in the *.asdb file, the waveform
viewer will open the Signal Browser and let you select which waveform objects should be
displayed. This is especially useful when working with large simulation databases.
 You can invoke the Signal Browser after loading the simulation database and add any signal
stored in the *.asdb file but not displayed in the active view of the waveform viewer. A signal
may not be displayed in the viewer if either it was not selected in the Signal Browser when the
.asdb file was first loaded or it was loaded from the .asdb file but deleted afterwards. Deleting
a signal in the Accelerated Waveform Viewer does not affect the .asdb simulation database.
Even though a signal is deleted from the Waveform View pane, it is still available in the .asdb
file and can be shown again.
The Signal Browser consists of two panes. The left pane shows design regions while the right one
lists objects defined in the region selected in the left pane. The hierarchy regions and signals
displayed in the Signal Browser can be filtered by names. The Scope and Object Name filters
allows specifying regular expressions. Additionally, signals can be filtered by their mode, which
allows reducing the signal list only to internal signals, input, output ports, etc.

List Viewer
 Active-HDL 7.3 introduces the Accelerated List Viewer - the new and high-performance tool that
can be used to present simulation data stored in the binary simulation database (*.asdb) in a
tabular format. The new list viewer (similarly to the Accelerated Waveform Viewer) is now an
integral part of the Active-HDL environment and can be used alternatively to the Standard List
Viewer displaying simulation results saved in the *.lst text file.
By default, the Accelerated List Viewer is enabled and the *.asdb simulation database is created
on initialization of simulation. The type of the list viewer can be changed globally for the entire
Active-HDL environment (along with the type of the waveform viewer) in the Default waveform
viewer/editor list box in the Waveform Editor/Editor category of the Preferences dialog box or
by using the waveformmode command. The change of the list viewer is possible prior to initializing
your simulation session. When simulation is running, the Default waveform viewer/editor list box
is disabled and issuing the waveformmode command returns an error in the Console window.
The list viewers have separate preferences available in the Appearance (Standard List Viewer)
and Accelerated Waveform Viewer (Accelerated List Viewer) subcategories in the Preferences

Active-HDL 7.3 23 of 34
 dialog box. Both the viewers are integrated with the common Active-HDL framework and they can
interact with other Active-HDL built-in tools. The list viewer objects presented in both types of the
list viewer can be added in the same way, i.e. by dragging objects to the list window, by using the
Add to List option of the pop-up menu, or the list macro command.

Design Flow Manager

 New Flowcharts

HDL Synthesis
1. Synplicity Synplify/Synplify Pro/Synplify Premier/Synplify Premier with Design Planner 8.9
2. Synplicity Synplify 8.8 for Actel (incl. Synplicity Synplify 8.8A1)
3. Synplicity Synplify 8.9 for Lattice
4. Xilinx XST 9.2 VHDL/Verilog (incl. Service Pack 3)

Physical Synthesis
1. Xilinx PlanAhead 9.2.3

Implementation
1. Actel Designer 8.0 SP3
2. Altera Quartus II 7.2
3. QuickLogic QuickWorks 9.9
4. Xilinx ISE/WebPack 9.2 (incl. Service Pack 3)
 Updated Flowcharts

HDL Synthesis
1. Mentor Graphics Precision RTL 2006a/2007a

Implementation
1. Altera Quartus II 7.1 (incl. Service Pack 1)
2. Lattice ispLEVER 7.0 SP1
 Flowchart Improvements and Changes

General improvements
1. The new PCB Interface feature has been added to the Design Flow Manager. The interface
allows conversion and then exchanging constraints (pin assignments) between a third-party
synthesis or implementation tool (e.g. used in a design and selected in the Design Flow Manager)
and a third-party PCB tool. If the interface is used along with other tools started from the Design
Flow window, the settings of the used technology and device family is automatically inherited. The
PCB Interface option is also available in the Tools menu. Alternatively, you can also export or
import constraints by using the activehdl2pcb and pcb2activehdl commands. Refer to Scripts for
additional information.

Cypress flowchart
1. The Cypress Warp flowchart has been removed.

Xilinx flowchart
1. The Xilinx Triscend FastChip flowchart has been removed. Contact Aldec technical support
directly for more information on how to enable and use this flowchart in version 7.3.

24 of 34 Active-HDL 7.3
Expression Coverage
Expression Coverage is now available for VHDL. (In version 7.2 of Active-HDL, it was available
only for Verilog.) The engine of Expression Coverage analyzes expressions found in the source
code, factorizes them into logical terms, and recognizes which terms contribute to the expression
value. Each term is then monitored during simulation for value changes. When simulation
terminates (or the excoverage write command is used), the simulator creates a report. The report
contains a breakdown of each expression accompanied by simulation statistics. The example
below discusses a simple expression:
clk'event and clk = '1'
This expression will be factorized into two terms: clk'event (marked by <1> in the listing below) and
clk = '1' (marked by <2>):
<1> - clk'event
<2> - clk = '1'
As the two terms are connected with the and operator, the result of the expression is determined as
follows:
• When the first term (clk'event) is false then the whole expression is false regardless of the
value of the second term (clk = '1').
• When the first term is true then the value of the expression is determined by the second
term. If the second term is false, the value of the expression is false.
• If both the first and the second term are true, the expression evaluates to true.
This is shown in the report using the following notation:
cnt | <1> <2>
and ---------------------
0| 0 -
10 | 1 0
10 | 1 1
Please note that the first term (i.e. clk'event) is marked by <1> and the second term (clk = '1') is
marked by <2>. and in front of the horizontal line is the name of the operator and the cnt column
shows counts for each of the three combinations. The expression clk = '1' used in (clk'event and clk
= '1') is further analyzed as:
<1> - clk
<2> - '1'

cnt | <1> <2>

= ---------------------
10 | lhs = rhs
10 | lhs /= rhs
To enable Expression Coverage, compile VHDL source files by using the -exc argument of the
VHDL compiler (acom) or check the Enable Expression Coverage option in the Compilation |
VHDL | Advanced category of the Design Settings dialog box. When you initialize simulation,
pass the -exc control | vector argument (simultaneously specifying the operating mode for
Expression Coverage) to the asim command. The database with coverage statistics is
automatically saved to a binary file when simulation terminates or you can generate a coverage
report manually.

Active-HDL 7.3 25 of 34
Toggle Coverage
 Toggle Coverage results collected in multiple simulation sessions can now be merged into a
single report in the command line. Merging coverage data is indispensable when it needs to be
assessed for a number of simulations. Instead of analyzing multiple Toggle Coverage reports, you
can merge all results and generate one collective report based on data from all simulations. Refer
to the Scripts section for additional information.

Block Diagram Editor

 The Block Diagram Editor and the Symbol Editor allow now controlling which VHDL generics
defined in library symbols will be passed to synthesis. Active-HDL 7.3 allows manual selection of
individual generics for which synthesis pragmas (by default, -- synopsys translate_on and --
synopsys translate_off) will be inserted into a generated source code. The pragmas can be
automatically inserted into the declarative part of a component and/or within generic map.
VHDL generics can be defined and then included or excluded from synthesis in the Symbol Editor
or on a block diagram in the component properties (in the Generics tab of the Symbol Properties
dialog box). The synthesis pragmas can be automatically inserted into the source code only for
generics of the components coming from the pre-installed vendor schematic libraries. Additionally,
some Xilinx libraries (VIRTEX 4/5, SPARTAN 3/3A/3ADSP/3E, and UNISIM) are delivered with
synthesis-specific generics already included to synthesis. In the previous versions of Active-HDL,
all synthesis-specific generics were excluded from synthesis by default. (JYI473, SPT16424,
SPT15711, SPT15117, SPT14344)
 The Check Diagram Settings dialog box provides the new Symbols tab. The tab allows you to
set whether any detected differences between generics of a compiled unit and a corresponding
library symbol will be detected and then reported as a warning or error.

Active-HDL Interfaces and Wizards

The following changes and improvements have been made to the built-in Active-HDL DSP interfaces:
 Interface to Simulink®
1. The HDL Black-Box for Synplify DSP block has been implemented. Introducing this block
allows integration and running co-simulation in designs containing models coming from Synplify
DSP ver. 3.2 and higher.
2. The VHDL ports of the real and integer types are now supported.
3. The VHDL generics of physical types are now supported.
4. The new ald_ver and ald_root functions have been added. The functions return the detailed
information about the installed blockset.
5. The ald_UpdateModel function has been improved. Now, the function allows specifying the
model name (opening model is no longer required) and it creates a backup copy of the model.
Additionally, it detects blocks that are not supported and provides information on how to manually
update them.
6. The value of the binary point of a HDL Black-Box port driven by a Simulink signal of the fixed-
point type can now be inherited from the settings of the driving signal. If the width of the vector in
Simulink differs from the width of the HDL port, you can choose to preserve either the dynamic
range or the accuracy.
7. The active edge of the clock signal can now be selected. It allows co-simulation of sequential
designs sensitive to either the rising or falling edge of the synchronization signals.

26 of 34 Active-HDL 7.3
  Interface to MATLAB®
1. The new ml_setup function allows setting the default value of the point, cast, and class
parameters used in all function calls related to passing values between MATLAB and Active-HDL.
As previously, the default values can be overridden by the explicit value specification in the
function call. Additionally, the ml_setup function allows choosing whether MATLAB Desktop or
MATLAB Command Window is used for co-simulation.
2. The new put_simtime function allows passing the current simulation time to the MATLAB
workspace.
The following changes and improvements have been made to the built-in third-party interfaces:
 Denali Interface
1. Denali memory models can now be used in VHDL. Using Verilog wrappers is no longer
necessary. (GRA2105, SPT16052)
2. The library for interfacing to Denali memory models no longer needs to be built by the user. A
ready-to-use dynamic-link library is delivered with Active-HDL. This library can be used both in
VHDL and for Verilog.
3. The denali.error file is created in the current directory when Denali exits abruptly and the Active-
HDL GUI closes. (Denali can exit when it detects a fatal error, for example the file with model
configuration is missing.)
 VPI Interface
Designs with VPI applications making an extensive use of the vpi_put_value() function can
simulate 5 times faster. For selected corner cases, the acceleration exceeded a factor of 10.
 PCB Interface
The new interface that allows transferring design constraints between HDL
synthesis/implementation tools and PCB tools has been added. Refer to the Flowchart
Improvements and Changes section of Design Flow Manager for more information.

Scripts
 The following arguments of the acom command are now available to specify the version of the
VHDL standard the compiler conforms to: -93 (IEEE Std 1076-1993), -2002 (IEEE Std
1076™-2002), -2006 (IEEE Std 1076™-2002 with some 2006 extensions). Additionally, the
-disable87 argument disables VHDL 87 syntax for file opening. By default, this syntax is allowed in
all modes (-93, -2002, and -2006). The equivalent options in the Active-HDL GUI are available in
the Preferences, Design Settings, and File Properties dialog boxes.
 The -strict93 argument of the acom command is now obsolete. This argument was previously
used to disable VHDL 87 file opening syntax.
 The behavior of the VSimSA alog command has changed with respect to the default working
library. If the working library has neither been set in VSimSA with the
set worklib <library> command nor specified in the command line with the -work <library>
argument, alog will try to compile source files to the work library, provided that this library is visible
from the current directory. In the previous versions, VSimSA reported an error (even if library was
visible).
 The -callbacks argument of the asim command (Active-HDL and VSimSA) is now obsolete and no
longer required to enable VHPI action callbacks and simulation phase callbacks or VPI
cbStartOfSimulation and cbEndOfSimulation callbacks.
 The -access_leak_report argument has been added to the asim command. When specified,
Active-HDL 7.3 allows monitoring and reporting all potential memory leaks (the default 10MB
threshold is no longer in effect) in VHDL dynamic allocation (i.e. memory reserved by the VHDL

Active-HDL 7.3 27 of 34
 new allocator) when simulation is terminated. Then the simulator reports not only the number of
objects and the amount of memory they occupy but also the locations in the source code where
such objects have been created.
 The waveformmode macro command has been added. The macro allows changing the type of the
waveform viewer in the command line and it is an alternative to the Default waveform
viewer/editor option in the Waveform Editor/Editor category of the Preferences dialog box.
 The wave and list macro commands support now both the Standard and Accelerated
Waveform/List Viewer. The syntax of the commands is common for both the viewers.
 The wave macro command has been supplemented with new arguments dedicated specifically to
the Accelerated Waveform Viewer. Now, the command allows adding virtual groups, analog
overlay buses, splitting waveform view panes, displaying objects in bold, presenting values of
vectors with reversed order of the vector bits, printing a detailed list of items added to the
Accelerated Waveform Viewer window, etc. Refer to the Active-HDL on-line documentation for
details.
 The -splitter argument has been added to the list macro command. The argument allows inserting
a new List View panes into the Accelerated List Viewer window.
 The new splitter command has been introduces. The command can be used to insert a new pane
into the Accelerated Waveform/List Viewer window, close the active pane, or change the focus
from one pane to another.
 The new arguments dedicated to the Accelerated Waveform Viewer have been added to the
syntax of the write macro command. Now, the command allows creating DO macros that can be
then used to restore the current view (or the format) of the Accelerated Waveform/List Viewer
window. It also allows you to save waveform view configurations (*.awc). Optionally, it is also
possible to save a copy of a simulation database the view configuration file is associated with.
 The activehdl2pcb and pcb2activehdl commands have been introduced. The commands allow
exchanging constraints (pin assignments) between a third-party synthesis or implementation tool
(e.g. used in a design and selected in the Design Flow Manager) and a third-party PCB tool.
Alternatively, you can control the export or import of design constraints by using the PCB
Interface option available from the Tools menu and the Design Flow window.
 The toggle -merge command has been implemented. The command allows merging Toggle
Coverage reports saved in the XML format. (Text reports cannot be merged.) The output of the
command with merged statistics is stored in an XML report.
 The addfile command has been supplemented with two new arguments that allow specifying the
simulation database file (*.asdb) and Accelerated Waveform View Configuration file (*.awc) while
adding new sources to the Active-HDL design.
 The force command allows now forcing a value onto a vector slice. Previously, it was only
possible to force a value of a complete vector or a single vector bit. A vector slice is specified with
two digits separated with a colon and enclosed in parenthesis, for example:
force -freeze a(2:0) 111
The above command forces the value 111 on three bits of the a signal. This notation can also be
used to refer to slices within complex signals, for example, to refer to a vector slice in a VHDL
record field or a slice of an element of an array of arrays, for example:
force -freeze record_sig.field_1(3:1) (100.0,200.0,300.0)
force -freeze arrarr_sig(0)(1)(1:0) "11"
The first example forces elements 3 through 1 in the field_1 field of the record_sig signal. The
field_1 field is an array of the real values. Note that the values are enclosed in the parenthesis and
separated with commas.

28 of 34 Active-HDL 7.3
 The second example forces a slice of a vector in an array of arrays. The type of the arrarr_sig
signal could be defined as follows:
type arr is array(1 to 10) of std_logic_vector(0 to 7);
type arrarr is array(1 to 10) of arr;
 The vhdlstandard and verilogstandard commands have been implemented. The commands allow
setting the VHDL/Verilog/SystemVerilog standard in the active design, Active-HDL global
preferences, or they return the current standard the compiler conforms to. (Alternatively, the
standard of the compiler can be selected in the VHDL/Verilog Compilation categories of the
Design Settings dialog box and VHDL/Verilog Compiler categories of the Preferences dialog
box. The standard for individual sources can also be set in the Compile tab of the File Properties
dialog box.)

Installation
 The value of the $PATH environment variable is now copied to the installation log
(AHDL<version>Setup.log). If you need to restore the paths defined by the variable prior to
installing Active-HDL, open the log file and go to the following entry:

AHDLSetup : Environment PATH=

The log file is always created in the root directory of the drive where the operating system is
installed. (SPT15499)

Problems Corrected in Version 7.3

VHDL Compilation and Simulation
 The vcom.exe program started in the operating system shell with the -lint argument did not
produce any LINT messages. The messages were only produced if the compiler was invoked from
the Active-HDL environment. The issue has been corrected and the messages are generated
regardless of how the compiler is started. (SPT16030)
 Initialization of simulation failed if a component used in an architecture was defined in a package
and it had a port of a user-defined type also defined in that package. The error appeared only if no
signal in the architecture was declared to be of the same type as the offending port. (SPT15788)
 Incorrect drivers were created for signals assigned to in processes created by the for...generate
statement if the assignments were made to signal elements selected with the iterator of the
generate loop. This resulted in incorrect simulation results. (SPT15807, SPT16034)
 Simulation initialization failed in some cases if the design used very convoluted VHDL
configuration introducing multiple levels of hierarchy that included generate statements.
(SPT15903)
 The range attribute could sometimes return incorrect values if its prefix was a type declared in a
package. (SPT15604)
 An internal application error occurred during simulation if a function returning the string type
returned a variable of the line type followed by a slice name. (SPT16099)
 A problem with compiling complex configurations that used architectures from libraries other than
the current working library has been fixed. (SPT16454)

Active-HDL 7.3 29 of 34
  An issue with annotating generics for negative timing checks was fixed. This issue could result in
assigning incorrect values to generics used in the setuphold timing check. (SPT16486)
 Failure to allocate memory by using the VHDL new allocator is now reported to the Console
window with the following message:
KERNEL: Error: Unable to allocate VHDL dynamic memory (<mem_size> MB).
VSIM: Error: Fatal error occurred during simulation.
where <mem_size> is the memory size. In the previous version of Active-HDL, an internal
application error was reported. Now, this issue is revised. (SPT16590)
 Simulation restarts after VHDL code changes and recompilation have been improved. (SPT15728)
 An issue with incorrect range calculation in expressions has been fixed. (SPT15658)
 Several issues with simulation elaboration, performance, and producing incorrect simulation
results were solved. (SPT15087, SPT16071, SPT16480, SPT16733)
 An internal application error has been eliminated when a variable of the line type was used.
(SPT16403)
 The issue with improper reporting the syntax error when the to_unsigned function was used
incorrectly in a VHDL code has been revised. (SPT14193)
 Previously, range checks in simulation could work incorrectly depending on the selected compiler
optimization mode (a difference between –dbg and -O3 mode). Now, this issue is revised.
(SPT16578)
 An issue with memory de-allocation after simulation restart was solved. (SPT16760)
Verilog Compilation and Simulation
 Verilog source files encrypted with the Synplicity protectip script were not compiled correctly if the
user key contained bytes equal 00 or 0A. (SPT15836)
 Several issues related to attributes have been resolved. Attributes could not be used inside
generate blocks or attached to register declarations inside named blocks. Bogus compiler errors
were reported if multiple attributes were placed in front of a module or a specific sequence of
attribute specifications, both with and without values, was used inside one set of parenthesis (* *).
(SPT14164, SPT16061, SPT16106, SPT16159, SPT16238)
 Making an assignment to a variable declared inside a named block inside a function could result in
an error during initialization of simulation. (SPT16283)
 Hierarchical references to parameters in the instantiation statement were not allowed. For
example, when the following statement was used:
I1 #(.param (uut.i2.param) ) m();
the compiler would incorrectly report that external references could not be used in the parameter
initial value. This issue surface when using Actel libraries. (SPT15970)
 A random compiler crash has been fixed. (SPT16253)
 A problem was solved with compilation of Verilog files to Active-HDL local library. (SPT14275)
 A problem in the compiler resulting in a simulation error was resolved. (SPT16719)
 An issue with incorrect case warnings was fixed. (SPT16750)
 The compiler did not generate a meaningful message when braces ( { } ) were used incorrectly in
the expressions specifying the address range of an array. (SPT16416)
 An internal compiler error was fixed. The error occurred when compiling Verilog generate
construct with a table of instances. (SPT16969)

30 of 34 Active-HDL 7.3
  A problem with simulation of hierarchical references was resolved. (SPT15577)
 The error message suggesting the use of the -v95/-v2k argument for the compiler has been
clarified. (SPT15544)
SystemVerilog Simulation
 Previously, the functions with the inout arguments could not be compiled. In this version of Active-
HDL, this issue is fixed. (MAL392)
SystemC Simulation
 Issues with wrong simulation results have been solved, Now, the synchronization between HDL
and SystemC kernels is now done on an event-by-event bases. This (SPT13452)
Mixed Simulation
 Under specific circumstances, using a bit selection of a Verilog port in the port map of a statement
instantiating a Verilog module in VHDL could result in an error at simulation initialization.
(SPT15978)
 The force command invoked with the -freeze argument did sometimes not work correctly for
signals at the VHDL/Verilog boundary. While the new value was applied correctly, it was then
overridden by the next event on the forced signal. (SPT16147)
EDIF Simulation
 The mappings in the edfmap.ini file were improved for better support Virtex BRAM models.
(SPT16281)
Code Coverage
 An internal error happened after restart when the -cc_exclude option was used in the asim
command. This defect is now repaired. (SPT16031)
 A problem with the support for national characters used in the VHDL coverage generation and
reports was fixed. (SPT15253)
Expression Coverage
 Occasional runtime errors that occurred while collecting Expression Coverage data for designs
using the VHDL SIGNED and UNSIGNED types have been eliminated.
Toggle Coverage
 A problem with counting signals initialized with the ‘0’ value at simulation initialization was
corrected. (SPT13607)
Design Flow Manager
 The problem with backslashes used in paths when an encryption bit file was used has been
corrected. (SPT16347)
 The issue with the macro search path in ISE-XST project generated by Active-HDL has been
corrected. (SPT15818)
 The import of pin assignment from the Altera QSF file has been corrected. (SPT15864)
 Previously, if the case used to specify the name of the top-level unit in the Top-level unit combo
box was different than the case in the source code, top-level was not detected when the Xilinx
Synthesis and Implementation flowchart was used. Now, this issue is resolved. (SPT16036)
 The issue with enabling the Timing process during implementation by using the Timing icon and
the corresponding Do not run simulation option in the Simulation tab of the Xilinx ISE
Implementation Options dialog box has been corrected. (SPT16402)

Active-HDL 7.3 31 of 34
Framework
 A GUI option is available to turn off Active-HDL messages with a module prefix. (SPT16390)
 An issue with disappearing menu after opening a file for the second time but in a separate split
window was solved. (SPT14715)
 The problem with the status of *.bde and *.asf files in the Design Browser after code changes,
after copying and pasting them to the Design Browser. (SPT15908)
 The HDL Editor was not opened automatically after a code breakpoint was hit. This problem
appeared only in the Beta release of Active-HDL 7.3. (SPT16717)
 A .dll library name conflict with Cadence Allegro was resolved. (SPT16025)
Active-HDL Interfaces and Wizards
 Scanning VHDL ports of type STD_LOGIC_VECTOR for drivers via the VHPI Interface by using
the vhpi_scan() function could hang VHPI applications. This issue occurred only in specific
circumstances, when multiple drivers were attached to port slices. (SPT14936, KRK844)
 The option to import ISE projects was improved. Problems with the detection of the xtclsh.exe file
were eliminated. (SPT16828)
 The import of EDK scripts was improved with regard to handling long paths to files inside scripts.
(SPT16552)
 The quality of the Archive option was improved; the location of .aws, and *.adf files was changed
in the *.zip file. (SPT15864)
 The quality of the MSIM project import was improved. File compilation status is now unavailable
after import. (SPT16647)
Accelerated Waveform Viewer
 The zoom range in the waveform viewer was sometimes reset if some source files were
recompiled and then the simulation was restarted. Additionally, the Zoom Previous option
became unavailable. (SPT15735, SPT16207)
 The range of analog signals was sometimes reset if some source files were recompiled and then
the simulation was restarted. (SPT16206)
 The waveform viewer sometimes displayed buses that contained bits with X values without
applying the color preference for the X value. The problem occurred if the X value was trimmed
inside the value displayed on the signal waveform. The color selected in the Preferences dialog
box was applied only when the waveform was zoomed in close enough (and the values inside the
waveform became visible). (SPT15917)
 Simplified display of Z,X,U,W values (which helps to see values) depends now on the zoom factor.
(SPT13298)
Standard Waveform Viewer/Editor
 An issue with large resource requirements when viewing a waveform with a large number of
expressions was solved. (SPT14808)
Block Diagram Editor
 The original case is now preserved for names of VHDL symbols created and available inside a
block diagram. (SPT15650)
 An application crash occurring after the fub input terminal was removed has been solved.
(SPT15912)

32 of 34 Active-HDL 7.3
  The quality of DRC was improved for some non-default VHDL specific sets. (SPT16369)
 A problem in the support of compound buses after the import Active-CAD was fixed. (SPT16598)
 A problem with disconnecting wires after moving symbols on a block diagram has been revised.
The problem occurred only in the Beta release of Active-HDL 7.3. (SPT16888)
State Diagram Editor
 The quality of code generation when actions contained assignments with line breaks has been
improved. (SPT16090)
 An issue with testbench generation when the FSM table is defined in a state machine has been
solved. (SPT16561)
Code2Graphics
 In version 7.3, the include directories are taken into account in a Verilog code. (SPT16382)
 The order of declarations in the VHDL declarative part does not change after Code2Graphics.
(SPT16464)
 The support for FSM templates in Code2FSM has been improved. (SPT16360)
Licensing
 An issue with the license check on the Microsoft Vista platform was fixed. (SPT16540)

Active-HDL 7.3 33 of 34
NOTES

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