CPU SIMULATION

Srushti Gole Aniruddha Sutawane Tanvi Walthare

Dept. Electronics and telecommunication Dept. Electronics and Dept. Electronics and telecommunication
engineering telecommunication engineering engineering
Vishwakarma Institute of Technology Pune, Vishwakarma Institute of Technology Vishwakarma Institute of Technology
India. Pune, India. Pune, India.

I. INTRODUCTION management in conjunction with CPU instructions can

In modern computing systems, efficient management of significantly slow down simulators, making it a challenge to
input and output (I/O) operations is crucial for simulate complex modern operating systems [7]. CPU
maintaining system performance and responsiveness. Two simulators paired with basic operating systems are essential
important concepts that help achieve this are I/O spooling in academic environments for teaching CPU architecture,
and buffering. Spooling (Simultaneous Peripheral operating system principles, and low-level programming.
Operation On-Line) refers to the process of placing jobs or Tools like Pintos and Topsy provide hands-on experience
tasks in a queue, allowing multiple tasks to be submitted with real-world systems on simulated hardware [8].
simultaneously while the system processes them Researchers use simulators to design and test new CPU
sequentially. Buffering, on the other hand, temporarily architectures, optimize performance, and study hardware-
stores data in memory (a buffer) before it is sent to a software interactions without the cost of building physical
device or application. prototypes [9]. Simulators also play a crucial role in
This project demonstrates the concepts of spooling and performance benchmarking, where the interaction between
buffering by implementing a print queue management CPU, memory, and operating systems is analyzed under
system. The print queue allows multiple print jobs to be different workloads [10]. Cycle-accurate simulations
submitted concurrently and manages them efficiently provide detailed insights but are extremely slow, making
using spooling techniques. The project aims to showcase them impractical for large workloads. Balancing between
how spooling optimizes resource utilization, reduces idle accuracy and speed is an ongoing challenge [11].
time, and enhances the overall performance of the printing Simulating multicore architectures and parallel execution
system. efficiently remains difficult. As modern processors increase
core counts, simulators must evolve to handle the
II. Literature Review complexity of concurrent execution [12]. Simulating both
Simulating CPU behavior offers invaluable insights into hardware and software, including OS behavior and
system performance, behavior under stress, and the peripheral devices, in a full-system simulation requires
functioning of hardware-software interactions. CPU substantial computational resources and precise modeling
simulators allow researchers and educators to test and [13].
teach without the need for physical hardware. Basic
operating systems are often used in these simulations to
provide a functional environment for processes, memory
management, and device interaction. III. METHODOLOGY/EXPERIMENTAL
A variety of techniques have been developed for
A. Block Diagram:
simulating CPUs. These include full-system simulators,
which simulate both the hardware and operating system,
and process-level simulators, which only emulate CPU
instructions. Simulators such as SimpleScalar [1] provide
detailed instruction-level simulations for different
architectures. These simulators enable the testing of CPU
instructions and their interactions with memory, caches,
and branch predictors. Tools like Gem5 [2] allow for
cycle-level simulation, where each clock cycle of the CPU
is simulated to understand performance bottlenecks, such
as cache misses or pipeline stalls. QEMU [3] is widely
used for functional simulation where the aim is to simulate
the execution of software without necessarily capturing
the precise timing behavior of the hardware. Hybrid
simulators combine instruction-level and cycle-level
methods to achieve a balance between accuracy and speed
[4].
Bochs [5] is a well-known emulator for x86 CPUs that can
run entire operating systems. It emulates both hardware
and software, making it a useful tool for OS development
and testing. Some simulators are designed with
minimalistic operating systems in mind. For example,
Pintos [6] is a minimal OS used to teach operating system
concepts. It runs on a simulated x86 machine and provides
an interface for developing OS-level projects. Accurate
simulation of system calls, interrupts, and process
 Stanford University, 2004. [Online].
IV. RESULTS AND DISCUSSIONS [7] M. Rosenblum and T. Garfinkel, "Virtual machine monitors:
current technology and future trends," Computer, vol. 38, no. 5, pp.
39–47, 2005.
[8] A. S. Tanenbaum, "Modern Operating Systems," 4th ed., Pearson,
2014.
[9] J. Emer, P. Ahuja, and M. Hill, "A future for computer
architecture research," ACM SIGARCH Computer Architecture News,
vol. 35, no. 2, pp. 2–17, 2007.
[10] C. Bienia, "Benchmarking Modern Multiprocessors," PhD
Thesis, Princeton University, 2011.
[11] A. Patel, F. Afram, S. Chen, and K. Ghose, "MARSS: A full
system simulator for multicore x86 CPUs," in Proceedings of the
48th Design Automation Conference, 2011, pp. 105-110.

The simulator successfully reads input instructions from a file [12] M. M. K. Martin et al., "Multifacet's general execution-driven
(input.txt), loads them into memory, and executes them as per multiprocessor simulator (GEMS) toolset," ACM SIGARCH
Computer Architecture News, vol. 33, no. 4, pp. 92–99, 2005.
the instruction set. As shown in the output file (output.txt), the
program processed multiple sets of instructions and generated [13] P. Magnusson et al., "Simics: A Full System Simulation
corresponding output, such as writing data to memory and Platform," Computer, vol. 35, no. 2, pp. 50–58, 2002.
comparing values.


The image shows an input file for an OS simulator project,

containing program jobs with instructions like `GD` (read
data), `PD` (write data), `LR` (load to register), `SR` (store
from register), and control commands like `CR` (compare)
and `BT` (branch). It includes delimiters (`$AMJ`, `$DTA`,
`$END`) marking job sections and contains sample data (like
"Hello World!" and "VIIT"). The file is used to simulate
reading, processing, and outputting data in memory during
execution.
REFERENCES
[1] D. Burger and T. M. Austin, "The SimpleScalar tool set, version
2.0," ACM SIGARCH Computer Architecture News, vol. 25, no. 3,
pp. 13–25, Jun. 1997.
[2] N. Binkert et al., "The Gem5 simulator," ACM SIGARCH
Computer Architecture News, vol. 39, no. 2, pp. 1–7, 2011.
[3] F. Bellard, "QEMU, a Fast and Portable Dynamic Translator,"
in Proceedings of the USENIX Annual Technical Conference, 2005,
pp. 41-46.
[4] R. Desikan, D. Burger, S. W. Keckler, and T. M. Austin, "Sim-
alpha: a validated, execution-driven Alpha 21264 simulator," ACM
Transactions on Modeling and Computer Simulation (TOMACS),
vol. 12, no. 4, pp. 283–311, 2002.
[5] K. Lawton, "Bochs: A portable x86 PC emulator," Linux
Journal, vol. 1996, no. 29, p. 7, 1996.
[6] B. Engler, "Pintos: A simple instructional operating system,"