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This document is an examination paper for the 4th Semester B. Tech students at P P Savani University, focusing on Computer Organization. It includes various questions on addressing modes, binary operations, flowchart design, and instruction evaluation. The exam is scheduled for April 6, 2022, and consists of multiple-choice and descriptive questions worth a total of 30 marks.

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9 views2 pages

Co 2

This document is an examination paper for the 4th Semester B. Tech students at P P Savani University, focusing on Computer Organization. It includes various questions on addressing modes, binary operations, flowchart design, and instruction evaluation. The exam is scheduled for April 6, 2022, and consists of multiple-choice and descriptive questions worth a total of 30 marks.

Uploaded by

nasitdrashti10
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Enrolment Number: _________________

P P SAVANI UNIVERSITY
P P SAVANI SCHOOL OF ENGINEERING
4th Semester of B. Tech Examination (2nd Internal Exam)
Subject: Computer Organization (SECE2040)
Branch: CE/IT

[Date: 06/04/2022, Wednesday] [Time: 12:30 P.M. to 01:30 P.M.] [Total Marks: 30]
Instructions:
 Figures to the right indicate full marks.
 Use of scientific calculator is allowed.
 Draw neat and clean drawings & Assume suitable data if necessary.

Q-1 Answer the following: (Any Five) (05)


1. In relative addressing mode, effective address = _______________ + __________________
2. Perform Arithmetic Shift Right on following binary number (100110011)2
3. ______________ Unit of CPU co-ordinates various operations using timing signals.
4. Define : Control word
5. RISC stands for _____________________________.
6. In the process of multiplication of unsigned numbers, the sign of result is decided by
a. Qs ⊕ Bs c. As ⊕ Qs
b. Bs ⊕ As d. None of Above
7. The most efficient method for translating arithmetic expressions into machine
language instructions is using
a. Prefix notation c. Postfix Notation
b. Infix Notation d. None of Above

Q-2 (a) Design a Flowchart for addition and subtraction of two binary numbers A and B. (05)
Assume that the numbers are stored in signed-magnitude representation.
Q-2 (b) Show the contents of register E, A, Q and SC during the process of multiplication of two (05)
binary numbers, 11111(multiplicand) and 10101(multiplier).The signs are not
included.
OR
Q-2 (a) Show the contents of register E, A, Q and SC during the process of division of 10010011
by 1011. (Use a dividend of eight bits).
Q-2 (b) Show the step-by-step multiplication process using Booth algorithm when the following
numbers are multiplied, +14(multiplicand) and -10(multiplier). Assume 5-bit registers
that hold signed numbers.
Q-3 (a) An instruction is stored at location 300 with its address field at location 301.The (05)
address field has the value 400.A processor register R1 contains the number
200.Evaluate the effective address if the addressing mode of the instruction is a) Direct
b) Immediate c) Relative d) Register indirect e) Index with R1 as the index register.
Q-3 (b) Explain the Three-Address and Two-Address instructions with expression (05)
(A+B)*(C+D).
OR

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Q-3 (a) Draw and explain the general register organization of CPU having seven registers, two (05)
multiplexers (MUX), an ALU and a destination decoder. Using that specify the control
word for micro-operation R1 R3 OR R4. (OPR selection for OR = 01010).
Q-3 (b) Convert the following numerical arithmetic expression into reverse polish notation (05)
(Postfix) and show the stack operations for evaluating the numeric result.
(300 + 23) * (43-21) / (84 + 7)
Q-4 What is parallel processing? How Parallel Computers are classified based on Flynn’s (05)
classification.

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