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DEPARTMENT OF ELECTRONICS &

COMMUNICATION
LAB MANUAL (EC 303)
“DIGITAL SYSTEM DESIGN”

Oriental Group of Institutes 1

 BACHELOR OF ENGINEERING (B.E.) COURSE

SEMESTER – III
(2024-25)
Corporate Office: Oriental Campus, Raisen Road, Bhopal - 462 022 (M.P.) India
Website: www.oriental.ac.in

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ORIENTAL INSTITUTE OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS
AND COMMUNICATION

LAB MANOGRAPH
DIGITAL SYSTEM DESIGN (EC-303)

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 INDEX
I. General Instructions

II. Experiments as per RGPV syllabus.

1. TO STUDY AND TEST OF OPERATION OF ALL LOGIC GATES FOR VARIOUS

IC’S (IC#7400,IC#7403,IC# 7408,IC#74332,IC#7486).

2. VERIFICATION OF DEMORGAN’S THEOREM.

3. TO CONSTRUCT OF HALF ADDER AND FULL ADDER.

4. TO CONSTRUCT OF HALF SUBTRACTOR AND FULL SUBTRACTOR CIRCUITS.

5. VERIFICATION OF VERSATILITY OF NAND GATE.

6. VERIFICATION OF VERSATILITY OF NOR GATE.

7. STUDY AND VERIFY RS FLIP FLOP.

8. STUDY AND VERIFY JK FLIP FLOP.

9. DESIGN A MULTIPLEXER.

10. DESIGN A DEMULTIPLEXER.

11. DESIGN A BCD TO EXCESS-3 CODE CONVERTER.

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Experiment No-1
Aim: - To study and test of operation of all logic gates for various IC’s (IC#7400, IC#7403, IC#7408,
IC#74332, IC#7486

Apparatus Required:- Logic gate Trainer Kit

Theory:-

Logic gates:-

Logic circuits that perform the logical operation of AND, OR & NOT are called gates. These gates
produce a Logic 1 & Logic 0 o/p signal and thus know as a Logic gates. These gates are AND,
OR, NOT, NAND, NOR, EXOR and EXNOR gates.

(1). AND gate:-The AND gate is an electronic circuit that gives a high output (1) only if all its
inputs are high. A dot ( . ) is used to show the AND operation i.e. A.B
(2).OR gate:-The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A plus
(+) is used to show the OR operation.

(3).NOT gate:- The NOT gate is an electronic circuit that produces an inverted version of the

input at its output.It is also known as an inverter. If the input variable is A, the inverted

output is known as NOT A

(4)NAND gate: -The NAND gate operates as an AND gate followed by a NOT gate.

It acts in the manner of the logical operation "and" followed by negation. The output is "false"

if both inputs are "true." Otherwise, the output is "true."

(5).NOR gate :-This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs
of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the
output. The small circle represents inversion.

(6).EXOR gate:-The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of
its two inputs are high. An encircled plus sign (+) is used to show the EXOR operation.

(7).EXNOR gate:-The 'Exclusive-NOR' gate circuit does the opposite to the EXOR gate. It will give a low
output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on
the output. The small circle represents inversion.

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Table 1: Logic gate symbols

(1) AND gate (2) OR gate

(3) Inverter or NOT gate (4) NAND gate

(5)NOR gate (6) XOR gate

(7) XNOR gate

Table 2: Logic gates representation using the Truth table

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1.AND GATE-(IC-7411) This operation is represented by a dot. The logic operation AND is interrupted by
means that z=1 if and only if x and y =1 ; otherwise z = 0

X Y F=X.Y

0 0 0

0 0 0

0
1 0
1

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 0

1 1 1

Truth table for AND Gate

2. OR GATE-(IC-7412)

This operation is represented by ‘+’ sign . It means that output is high in case any one of the I/Ps is high

X Y F=X+Y

0 0 0

0 0 1 Truth table for

OR Gate
0

1 1 1
X F=X’
0
0
1 1
1 0
1 1
0
1
0 1

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 0 3. NOT GATE- (IC-7404)This operation is represented by a
prime(some time a bar) .X′ =Z (X=Z) is read “X is not equal to Z”
0 , means if x=0 ,z=1 and vice versa

Truth table for NOT Gate

4. EXCLUSIVE OR GATE: The EX-OR operation gives high output if one of the inputs is high. The Boolean
for XOR operation can be written Y = X +Y = X’Y + XY’ ,This operation can be implemented using basic
AND, OR and invert gates. The symbol and truth table for XOR gate is given in Fig.(a) and (b) . The pin
diagram of popular XOR gate IC is shown in fig.

X Y F=x’y+xy’

0 0 0

0 1 1

1 0 1

1 1 0

Truth table for XOR Gate

5. EXCLUSIVE NOR GATE:

The EX-NOR operation give high output for both inputs low and both inputs high. The Ex-NOR is written
as

F=X’Y’+XY This operation is implemented using basic AND, OR, and invert gates .The basic logic circuit
and symbol for the EX-NOR are shown in fig.

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 X Y F=x’y’+xy

0 0 1

0 1 0

1 0 0

1 1 1

Truth table for XNOR Gate

PROCEDURE :

1. Connect the gates as shown in Figure

2. Set the input switches according to the truth tables as shown in the first row.
3. Monitor the output for the proper indication. If the light is off. Place a 0 under column Z and
write”off” in the LED column. If the light is ON, place a 1 under column Z and write “on” in the
LED column.
4. Repeat steps 2 and 3 for the remaining rows of the truth tables.
5. Repeat the above steps for verifying the truth tables in the case of a 3-input AND gate by selecting
3input switches and 073 monitoring the output on the Lamp out.

RESULT: The Truth table for all the logic gates is verified

CONCLUSION:
1.AND GATE- Output is high when all the inputs are high

2.OR GATE- Output is high when any input is high.

3.EX-OR GATE –Output is high when number of input 1’s are odd.

4.EX-NOR - Output is high when number of input 1’s are even.

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Experiment No-2

Aim: - To study and verify Demorgan’s theorem

Apparatus Required: - Logic gate Trainer Kit

Theory:-

De Morgan’s Theorem was created by Augustus De Morgan, a 19th-century mathematician who

developed many of the concepts that make Boolean logic work with electronics.

DeMorgan'Theorems:
a. (A + B) = A* B
b. A*B = A + B
Note: * = AND operation

Theorem 1:The compliment of the product of two variables is equal to the sum of the compliment of
each variable.Thus according to De-Morgan’s laws or De-Morgan’s theorem if A and B are the two
variables or Boolean numbers. Then accordingly

(A.B)’ = A’ + B’

Theorem 2:The compliment of the sum of two variables is equal to the product of the compliment of
each variable.

Thus according to De Morgan’s theorem if A and B are the two variables then.

(A + B)’ = A’.B’

RESULT: Demorgans law has been verified

PRECAUTIONS:
1. The connections should be made properly
2. The trainer kit should be handled properly

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Proof by Tabular method

A B A.B (A.B)’ A B A’ B’ (A’+B’)

0 0 0 1 0 0 1 1 1

0 1 0 1 0 1 1 0 1

1 0 0 1 1 0 0 1 1

1 1 1 0 1 1 0 0 0

A B A+B (A+B)’ A B A’ B’ A’.B’

0 0 0 1 0 0 1 1 1

0 1 1 0 0 1 1 0 0

1 0 1 0 1 0 0 1 0

1 1 1 0 1 1 0 0 0

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Experiment No-3

Aim: - To construct half adder and full adder

Apparatus Required: - Logic gate Trainer Kit

Theory:-

Half Adder:-It is a combinational circuit that performs addition of two bits. This circuit has two
inputs and two outputs. . Two of the inputs variables denoted by A & B represent the two
significant bits to be added. The two outputs are designated as the symbols”S” for sum &”C” for
carry. The binary variable S gives the value of least significant bit of the sum. The binary
variable C gives the output carry.

Output

Carry Sum
Input

A B C S

0 0 0 0

0 1 0 1

1 0 0 1
Truth table for half adder
1 1 1 0

Full Adder:-A full adder is a combinational circuit that forms arithmetic sum of three
input bits. It consists of three inputs & two outputs. Two of the inputs variables denoted
by X&Y represent the two significant bits to be added. The third input Z represents the
carry from the previous lower significant position. The need for the two outputs arises
because the arithmetic sum of three binary digits ranges in the value from 0-3 and
binary 2&3 need two digits. The two outputs are designated as the symbols”S” for sum
&”C” for carry. The binary variable S gives the value of least significant bit of the sum.
The binary variable C gives the output carry.the truth table logical expression for S &
C outputs are:S = A  B/S=A’B+AB’/C=AB

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 X Y Z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0 Truth table for full adder

1 0 0 0 1

1 0 1 1 0 From the truth table logical expression for S & C

outputs are:
1 1 0 1 0

1 1 1 1 1

S=XY’Z’+X’YZ’ +X

C=XY+XZ+YZ

PROCEDURE:

1. Connect the gates as shown in Figure

2. Set the input switches according to the truth tables as shown in the first row.
3. Monitor the output for the proper indication. If the light is off. Place a 0 under column Z
and write”off” in the LED column. If the light is ON, place a 1 under column Z and write
“on” in the LED column.
4. Repeat steps 2 and 3 for the remaining rows of the truth tables.
5. Repeat the above steps for verifying the truth tables

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 RESULT : The Truth table for Full Adder and Half Adder is verified

PRECAUTIONS:

1. The connections should be made properly

2. The trainer kit should be handled properly

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Experiment No-4
Aim: - To construct of half subtractor and full subtractor circuits

Apparatus Required:- Logic gate Trainer Kit

Theory:- HALF SUBTRACTOR:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.

𝐃𝐢𝐟𝐟𝐞𝐫𝐞𝐧𝐜𝐞 = 𝐀 ⊕ 𝐁

Borrow=A’.B

FULL SUBTRACTOR: A combinational circuit which performs the subtraction of three input bits is called full
subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can
be implemented with two half subtractors and one OR gate.

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Difference, DIFF= A’B’C + A’BC’ + AB’C’ + ABC

Borrow, BORR = A’BC + AB’C + ABC’ +ABC

HALF SUBTRACTOR

TRUTH TABLE:

INPUT OUTPUT
S.No
A B DIFF BORR

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

FULL SUBTRACTOR

TRUTH TABLE:

INPUT OUTPUT
S.No
A B C DIFF BORR

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

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 7. 1 1 0 0 0

8. 1 1 1 1 1

RESULT : The Truth table for Full subtractor and Half subtractor is verified

PRECAUTIONS:

1. The connections should be made properly

2. The trainer kit should be handled properly

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Experiment No-5
Aim: - Verification of versatility of NAND gate

Apparatus Required: - Logic gate Trainer Kit

Theory:-NAND GATE-(IC-7450):-NAND function is complement of AND and is an abbreviation for “AND”. Its graphic
symbol which consists of an AND graphic symbol following by a small circle. The NAND & NOR gates are extensively used
as standard logic gates and are in fact far more popular than AND or OR gates, NAND and NOR gates are easily
constructed with transistor circuits and because Boolean function can be easily implemented with them, that is why are
popularly know as universal gates.

F=X.
X Y F’=(X.Y)’
Y

0 0 0 1

1 0

0 0 1

0
Truth table NAND Gate
0 0
PROCEDURE:
1 1 1
1. Connect the gates as shown in Figure

2. Set the input switches according to the truth tables as shown in the 0
first row.
1 1 0
3. Monitor the output for the proper indication. If the light is off. Place
a 0 under 1 1
Column Z and write “off” in the LED column. If the light is ON, place a
1 under 1

Column Z and write “on” in the LED column.

4. Repeat steps 2 and 3 for the remaining rows of the truth tables.

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5. Repeat the above steps for verifying the truth tables in the case of a 3-input AND

gate by selecting 3input switches and 073 monitoring the output on the Lamp out.

RESULT: The Truth tables for NAND GATE gates are verified

PRECAUTIONS 1. The connections should be made properly

2. The trainer kit should be handled properly

Experiment No-6
Aim: - Verification of versatility of NOR gate.

Apparatus Required: - Logic gate Trainer Kit

X Y F=X+Y F’=(X.Y)’

0 0

0 0 0

1 1

0 0 0

0 1

1 1 0

1 1 1
1
1

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Theory:-NOR GATE( IC-7427):- The NOR function is the
complement of the OR function and its name an OR graphic 1
symbol followed by a small circle.The NAND & NOR gates are
extensively used as standard logic gates and are in fact far more popular than AND or OR gates , This is
become NAND and NOR gates are easily constructed with transistor circuits and because Boolean
function can be easily implemented with them, that is why are popularly know as universal gates.

Truth table for NOR Gate

PROCEDURE:

1. Connect the gates as shown in Figure

2. Set the input switches according to the truth tables as shown in the first row.

3. Monitor the output for the proper indication. If the light is off. Place a 0 under

Column Z and write “off” in the LED column. If the light is ON, place a 1 under

Column Z and write “on” in the LED column.

4. Repeat steps 2 and 3 for the remaining rows of the truth tables.

5. Repeat the above steps for verifying the truth tables in the case of a 3-input AND

gate by selecting 3input switches and 073 monitoring the output on the Lamp out.

RESULT: The Truth tables for NAND GATE gates are verified

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PRECAUTIONS:

1. The connections should be made properly

2. The trainer kit should be handled properly

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Experiment-No-7
Aim: - Study & Verify RS Flip Flop.

Apparatus Required: - Logic gate Trainer Kit

Theory:-

1) Basic flip flop : - A flip flop can be constructed from two NAND gates or two NOR gates .the cross
coupled connections from the o/p of one gate be i/p of another constitute the feedback path ,each flip
flop has two o/p Q & Q' and two i/p set and reset ,the type of flip flop is sometimes called direct coupled
RS flip flop or SR latch.In basic flip flop circuit with NOR gate we must remember that o/p is 1 only when
all i/p are 0. as starting point is assume that set i/p is 1 and reset i/p is 0, since gate 2 has an i/p of 1, it’s
o/p must be 0,its o/p Q' must be 0, which puts both input of gates to the o/p Q is 1, when the set i/p is
returned to 0,the o/p remains the same at one i/p at gate 2 at 1.That causes o/p Q to stay at 0 which
leaves both i/p of gates no. 1 at 0.So Q is at 1. A f-f has two useful states when Q =1 and Q'=0 ,it is in the
set state . When Q =0&Q'=1 it is clear state .Under normal conditions both i/p remains at 0 unless the
state of the flip flop has to be changed. The application of momentary 1 to the set i/p causes the flip flop
to go to set state .The set state i/p must go back to 0 before 1 is supplied to reset i/p .The NAND basic flip
flop circuit . Operates with both i/p normally at 1 under the state of f-f has to be changed. The application
at momentary 0 to set i/p has o/p Q to go to 1 and Q' to 0. The flip flop in the set state .After the set i/p
causes a transition to the clear state when both i/p go to 1, a condition avoided in the f-f operation .

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 Logic diagram Transition table

2) Clocked RS Flip Flop : By adding Gates to the i/p of the basic circuit. of the flip flop can be made to
respond to the i/p level during the occurrence clock pulse. This f-f consist of basic NOR and two NAND
gates the o/p of the two AND gates remains at 0 as long as the clock pulse is 0 regardless of S & R. i/p
values when clock pulse goes to 1 information from S & R i/p is allowed to reach the basic f-f , the set state
is 1 with set R=0 & CP = 1.To change to clear state the i/p must be S=0, R=1 & CP =1, with both S = 1, R =1,
the occurrence of clock pulse causes both i/p to go 0.

Q(t+1)=S+R'Q

It is an algebraic exp. for binary information of characteristics tables

Logic diagram Transition table

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PROCEDURE:

1.Connect the input terminal of flip flop to high and low terminal of the logic circuit .

2.Connect the out put terminal to LED.

3.Switch on the kit .

4.Vary the input (high/low) in the input terminals of various Flip flops.

5.Make the verification of truth table.

OBSERVATIONS :
The truth table obtained matches with function of logic gates and hence verified.The truth table
that has been prepared as per the requirements and connection made. All the functions of the
multiple matches and verified as per the truth table.

RESULT:
Truth table for RS & JK flip-flop is verified and the result was checked through LED’S.

PRECAUTIONS:
1.The connections should be made properly
2.The trainer kit should be handled properly

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Experiment-No-8
Aim: - Study & Verify JK Flip Flop.

Apparatus Required: - Logic gate Trainer Kit

Theory:-J K Flip Flop : J K Flip Flop is a refinement of RS Flip Flop in that the indeterminate state of RS type is defined in
JK type. Input J & K Behaves like input S & R. to set and clear Flip Flop when inputs are applied to both J & K
Simultaneously Flip Flop switches to its complementary State. In this type of Flip Flop output Q is AND with Clock pulse,
inputs so that the i/p are available to the Flip Flop only when Q and CP both are 1.

Logic diagram Transition table

PROCEDURE:

1.Connect the input terminal of flip flop to high and low terminal of the logic circuit .

2.Connect the out put terminal to LED.

3.Switch on the kit .

4.Vary the input (high/low) in the input terminals of various Flip flops.

5.Make the verification of truth table.

OBSERVATIONS :

The truth table obtained matches with function of logic gates and hence verified.The truth table
that has been prepared as per the requirements and connection made. All the functions of the
multiple matches and verified as per the truth table.

RESULT:Truth table for RS & JK flip-flop is verified and the result was checked through LED’S.

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PRECAUTIONS:
1.The connections should be made properly
2.The trainer kit should be handled properly

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 Experiment No-9/10
Aim: -Study and design a Multiplexer/ Demultiplexer

Apparatus Required: - Logic gate Trainer Kit

Theory:-Multiplexer means transmitting a large no. of information unit over a small no. of channels or
lines. A digital multiplexer is a combinational circuit.That receives binary information from one of 2n input
data lines & directs it to a Single output lines. the selection of a particular input data line for output is
Determine by a set of selection input. A 2n x 1 multiplexer has 2n input data lines & n input selection lines
whose bit combinations determine which input data are selected for the output. Each of the four data
inputs I0 through I3 is applied to one input of an and gate. The two selection inputs s1 & s0 are decoded to
select a particular AND gate . The outputs of the AND gates are applied to single OR gate to provide the
single output. The multiplexer has six inputs and one output. A multiplexer is also called data selectors,
since it selects one of the many inputs and steers the binary information to the output line.

Circuit Diagram

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Demultiplexer is a digital device that directs information from a single input to one of several
output which means one is to many. This enable to transmit the information on one of the 2n
possible output lines .the decoder can function as Demultiplexer if e line is taken as data input line
and line a and b are taken as selection lines. This is shown in figure of Demultiplexer. a decoder
with an enable input is referred to as decoder/Demultiplexer. It is enable to input that makes a
circuit a Demultiplexer. Decoder/Demultiplexer circuits can be connected together to form a larger
decoder circuits. fig. shows two 3*8 decoders which enable inputs connected to form 4*16
decoders.

PROCEDURE :
1. Switch on the trainer and check the power supply .
2. Note that the supply voltage is +5v.
3. Study pin configuration of the 74150 circuit 7493 is provided mechanical switches which has been
in the trainer to choose correct input (1 Hz) to pin 14 of 7493 and corresponding patch the output
of 7493 ABCD TO THE INPUT OF 74150 .
4. The LED,s are connected to the 7493 counts from 0 to 15 the single output channel of the
multiplexer is energized alternately the 16 inputs to 74150 IC can be given through logic switches
also thus the trainer highlights how a 16 bit information is otherwise indicated as 16*1
multiplexing..
5. Study the pin configuration of 74154-ckt. The device consists of 16 counter which is
provided in a trainer to give input to the Demultiplexer.
6. The clock input (1 Hz.) to pin 14 of 7493 and corresponding path the output of 7493 ABCD
to the input of 74154 G1 and G2.the slope points of 74154 are to grounded
7. The LED’s are connected to output of demultiplexer.As the 7493 count from 0-15 the
output channel 1-16 of Demultiplexer are alternatively ABCD input can be given through
logic switch also.
8. The trainer highlights has a 4 bit information is being transmitted through 16 channels
which is indicated 4-16 Demultiplexer

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 CIRCUIT DIAGRAM

OBSERVATIONS:
The truth table obtained matches with function of logic gates and hence verified.
The truth table that has been prepared as per the requirements and connection made. All
the functions of the multiple matches are verified as per the truth table.

RESULT:
Truth table for the MUX & DEMUX has been verified.

PRECAUTIONS:
1. The connections should be made properly
2. The trainer kit should be handled properly.

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EXPERIMENT NO. 11
Aim: To Design and verify the truth table of code conversion from BCD to Excess-3

using basic Logic Gates.

Objective:
 Design of different combinational circuits and their applications using basic
logic gates.
 Creation and observation of the excess 3 code representation sequence
 Exercising the design of code conversion logic circuits,
 Creating the truth table of conversion functions from BCD to EXCESS 3 code
 Developing skills in simplification of specified logical functions
Apparatus Required:
 Prototyping board (breadboard)
 DC Power Supply 5V Batery
 Light Emitting Diode (LED)
 Digital ICs: 7404 :Hex Inverter
7408 :Quad 2 input AND
7432 :Quad 2 input OR
 Connecting Wires
Theory:

Code Converters: A code converter is a combinational circuit that must be inserted between the
two systems, to make them compatible even though each uses different code for same
information. It means that a code converter is a code translator from one code to the other. The
code converter is used since to systems using two different codes but they need to use the same
information. So the code converter is the solution.

BCD Codes: Numeric codes represent numeric information i.e. only numbers as a series of 0’s
and 1’s. Numeric codes used to represent decimal digits are called Binary Coded Decimal (BCD)
codes. A BCD code is one, in which the digits of a decimal number are encoded-one at a time into
group of four binary digits. There are a large number of BCD codes in order to represent decimal
digits0, 1, 2 …9, it is necessary to use a sequence of at least four binary digits. Such a sequence
of binary digits which represents a decimal digit is called code word.

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EXCESS 3 Codes: It is a non-weighted code. It is also a self-complementing BCD code used in
decimal arithmetic units. . The Excess-3 code for the decimal number is performed in the same
manner as BCD except that decimal number 3 is added to the each decimal unit before encoding
it to binary.

Circuit Diagram:

Fig: Circuit Diagram of BCD to EXCESS 3 code converter

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Truth Table for BCD to Excess -3 Code Conversion:

INPUTS(BCD) OUTPUTS(Excess-3)

A B C D W X Y Z

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 1 0 1 0 1

0 0 1 0 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

0 1 0 1 1 0 0 1

0 1 0 0 1 0 1 0

1 1 0 0 1 0 1 1

1 1 0 1 1 1 0 0

Eqautions:

Z=D

Y = CD+C’D’=CD(C+D)’

X = B’C+B’D+BC’D’= B’(C+D) +BC’D

W = B’(C+D) +B(C+D)’

Procedure :

1. Collect the components necessary to accomplish this experiment.

2. Plug the IC chip into the trainer kit.
3. Connect the supply voltage.

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 4. Connect the output of the gate to the output LEDs.
5. Set the inputs to the logic gates according to the all possible combinations.
6. Once all connections have been done, turn on the power switch of the
trainer kit.
7. Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if L1 is OFF Apply
the various combination of inputs according to the truth table and observe the condition of Output
LEDs.
Observation Table: Input Variable: A B C D
Output Variable: W X Y Z

INPUTS(LED) OUTPUTS(LED)
A B C D W X Y Z

Calculation:

Kmap Simplification:

For W:

For X:

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 For Y

For Z

Boolean Expression: W =

X =

Y=

Z=

Result and Discussions: Excess-3 code is a 4-bit unweighted code and can be obtained from the
corresponding value of BCD code by adding three to each coded number.Excess-3 code is self
complemnting in nature because 1’s complement of the coded number yields 9’s complement of
number itself.

Conclusion: BCD to Excess-3 code converter has been designed using basic logic gates and its
truth table verified.

Lab tutorial

1) Excess-3 code are:

a) cyclic codes
b) self complemantary codes
c) Weighted codes
a) None of above
2) BCD is:
a) Binary coded digit
b) Binary coded decima

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 c) binary cyclic decimal
d) none of the above
3) The Excess-3 code for 0111 is:
a) 1010
b) 1011
c) 1000
d) 1001
4) The Excess-3 code of 1000 is:
a) 0111
b) 1011
c) 10101
d) 1100
5) The BCD of Excess-3 code 0100 is:
a) 0010
b) 0001
c) 0011
d) 0100
6) The weights in the BCD codes are :
a) 1,2,4,8
b) 8,4,2,1
c) 8,6,4,2
d) 2,4,6,8
Short Answer types question:
Ques1: Why Excess-3 code is known as self complementary code?

Ques2: Design a combinational circuit which converts Excess-3 code into BCD?

Ques3: A combinational network has four inputs( A,B,C,D) and four outputs (W.X,Y,Z).W X Y Z
represents an excess-3 coded number whosevvalue equal te number of 1’s at the input.Write
down the minimum expresion for the outputs?

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Ques4: Design a combinational circuit whose input is 8421 BCD number and whose outputs is the
9’s complement of the input number.

Ques 5: Design a combinational circuit whose input is a three bit number and whose output is
the 1’s complement of the input number.

Oriental Group of Institutes 37