What Is The Fetch-Execute Cycle
What Is The Fetch-Execute Cycle
The fetch-execute cycle (also known as the fetch-decode-execute cycle) is the process the CPU
follows to retrieve an instruction from memory, understand it, and then execute it. It repeats
continuously while the computer is running.
Then, you move on to the next task and repeat the cycle.
1. Fetch Stage
The Program Counter (PC) holds the address of the next instruction to be fetched.
The Memory Address Register (MAR) takes this address from the PC.
The CPU fetches the instruction stored at that address in RAM and stores it in the Memory
Data Register (MDR).
2. Decode Stage
The Control Unit (CU) interprets the instruction stored in the MDR.
If it involves data, the CPU gets ready by identifying which registers are needed.
3. Execute Stage
This could involve arithmetic operations (using the Arithmetic Logic Unit (ALU)),
loading/storing data, or changing the flow of execution (e.g., a jump instruction).
Diagram Representation
1. Fetch:
PC → MAR → MDR → CIR
2. Decode:
CIR → CU
3. Execute:
ALU / Registers → Output
I recommend drawing this cycle on the board with arrows to show the flow of data.
ADD 5, 3
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1. "The CPU fetches the instruction and data at the same time."
Explain that fetching an instruction is separate from fetching data. The CPU fetches the
instruction first, then fetches the required data if needed.
Modern CPUs use pipelining, meaning they work on multiple instructions at different stages
simultaneously.
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Assign students different CPU components (PC, MAR, MDR, ALU, CU) and have them act out
the fetch-execute cycle.
One student (PC) holds a list of instructions, another (MAR) fetches from a "memory location,"
and so on.
2. CPU Simulation
Use an online simulator like Little Man Computer (LMC) to allow students to step through each
stage of the cycle.
The fetch-execute cycle is how the CPU retrieves, interprets, and carries out instructions.
It involves the PC, MAR, MDR, CIR, CU, ALU, and Registers.
Marking Scheme
2(a) The CPU fetches an instruction: LOAD 50 (5 marks)
The LOAD 50 instruction means the CPU should load the value stored at memory
address 50 into a register. The process follows these steps:
1. Fetch (2 marks)
The Program Counter (PC) holds the address of the next instruction (e.g., 200).
The Memory Address Register (MAR) takes this address and sends a request to RAM.
The instruction (LOAD 50) is retrieved from memory and stored in the Memory Data
Register (MDR).
The instruction is transferred to the Current Instruction Register (CIR) for decoding.
2. Decode (1 mark)
It identifies that the CPU must fetch data from memory location 50 and store it in a
register.
3. Execute (2 marks)
The CPU fetches the data from memory address 50 and stores it in a general-purpose
register (e.g., Accumulator).
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MAR = 200 → The CPU is currently fetching the instruction stored at address 200. (1
mark)