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Codes Exp 7

The document contains Verilog code for various digital logic components including half adders, half subtractors, and full adders. It also includes implementations for basic logic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR) and a seven-segment display decoder. The code is structured into modules with appropriate input and output specifications for each component.

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prakhar3202005
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3 views4 pages

Codes Exp 7

The document contains Verilog code for various digital logic components including half adders, half subtractors, and full adders. It also includes implementations for basic logic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR) and a seven-segment display decoder. The code is structured into modules with appropriate input and output specifications for each component.

Uploaded by

prakhar3202005
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Full adder

Full Subtractor

Half adder

module half_adder_d (
input a,b,
output sum, carry
);
assign sum = a ^ b;
assign carry = a & b;

Endmodule

Half Subtractor
module half_sub_d (
input a,b,
output sum, carry
);

assign sum = a ^ b;
assign carry = ~a & b;

Endmodule

Verilog code for all Logic Operation

`timescale 1ns/1ps

module and_gate(input a, b, output y);


assign y = a & b;
endmodule

module or_gate(input a, b, output y);


assign y = a | b;
endmodule

module not_gate(input a, output y);


assign y = ~a;
endmodule

module nand_gate(input a, b, output y);


assign y = ~(a & b);
endmodule

module nor_gate(input a, b, output y);


assign y = ~(a | b);
endmodule

module xor_gate(input a, b, output y);


assign y = a ^ b;
endmodule

module xnor_gate(input a, b, output y);


assign y = ~(a ^ b);
endmodule

module gate(
input wire a, b,
input wire [2:0] select,
output reg led,
input wire clk
);

wire and_out, or_out, not_out, nand_out, nor_out, xor_out, xnor_out;

// Unique instance names


and_gate u1 (.a(a), .b(b), .y(and_out));
or_gate u2 (.a(a), .b(b), .y(or_out));
not_gate u3 (.a(a), .y(not_out));
nand_gate u4 (.a(a), .b(b), .y(nand_out));
nor_gate u5 (.a(a), .b(b), .y(nor_out));
xor_gate u6 (.a(a), .b(b), .y(xor_out));
xnor_gate u7 (.a(a), .b(b), .y(xnor_out));

always @(posedge clk) begin


case (select)
3'b000: led = and_out;
3'b001: led = or_out;
3'b010: led = not_out;
3'b011: led = nand_out;
3'b100: led = nor_out;
3'b101: led = xor_out;
3'b110: led = xnor_out;
default: led = 1'b0;
endcase
end

endmodule

Seven Segment Display

`timescale 1ns/1ps

module seven_seg(
input [3:0] digit,
output reg [6:0] display,
output wire [7:0] an,
output wire dp
);

// Correcting the seven-segment display encoding


parameter zero = 7'b0000001;
parameter one = 7'b1001111;
parameter two = 7'b0010010;
parameter three = 7'b0000110;
parameter four = 7'b1001100;
parameter five = 7'b0100100;
parameter six = 7'b0100000;
parameter seven = 7'b0001111;
parameter eight = 7'b0000000;
parameter nine = 7'b0000100;
parameter A = 7'b0001000;
parameter B = 7'b0000011; // Fixed B
parameter C = 7'b0110001;
parameter D = 7'b0000110; // Fixed D
parameter E = 7'b0110000;
parameter F = 7'b0111000;

// Corrected bit-width for 'an'


assign an = 8'b11111110;
assign dp = 1'b1;

always @(digit) begin


case (digit)
4'd0: display = zero;
4'd1: display = one;
4'd2: display = two;
4'd3: display = three;
4'd4: display = four;
4'd5: display = five;
4'd6: display = six;
4'd7: display = seven;
4'd8: display = eight;
4'd9: display = nine;
4'd10: display = A;
4'd11: display = B;
4'd12: display = C;
4'd13: display = D;
4'd14: display = E;
4'd15: display = F;
default: display = 7'b1111111; // Turn off all segments for undefined values
endcase
end

endmodule

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