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Esa 2023

The document outlines the End Semester Assessment for the Computer Architecture course at PES University, detailing various questions and topics related to parallelism, cache performance, reliability, optimization techniques, memory access times, and vector architecture. It includes calculations for CPI, reliability improvements, and explanations of concepts such as branch prediction and memory consistency models. The assessment consists of multiple sections with specific marks allocated for each question.

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Rizwanpatel Malipatel
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18 views5 pages

Esa 2023

The document outlines the End Semester Assessment for the Computer Architecture course at PES University, detailing various questions and topics related to parallelism, cache performance, reliability, optimization techniques, memory access times, and vector architecture. It includes calculations for CPI, reliability improvements, and explanations of concepts such as branch prediction and memory consistency models. The assessment consists of multiple sections with specific marks allocated for each question.

Uploaded by

Rizwanpatel Malipatel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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PES University, Bengaluru

(Established under Karnataka Act 16 of 2013)

END SEMESTER ASSESSMENT (ESA) - JULY - 2023

UE20EC353 - Computer Architecture

Total Marks : 100.0

1.a.
Explain Michael Flynn Classes of Parallelism and Parallel Architectures
(6.0 Marks)

1.b. A system has base CPI of 1.0, assuming all references hit in the level 1 cache,
and a clock rate of 1 GHz. The system has on chip split level 1 cache. The miss rate
of an instruction cache is 2% and the miss rate of the data cache is 5%. System also
has off chip unified level2 cache with access time of 25ns and miss rate of 0.82%.
The main memory access time is 250ns. Calculate the total CPI of the system and
speed_up with level2 cache. Assume 40% of instructions are load store. (6.0 Marks)

1.c. The failure rate of a system is 60 per million. When a redundant component is
added in a system the failure rate becomes 54 per million. The redundant
component’s MTTF improved by 3500 times. Calculate the improvement in
reliability due to redundant component in the system. (4.0 Marks)
1.d.

(4.0 Marks)

2.a.

(5.0 Marks)

2.b. Explain the following optimization techniques


a) Way Prediction to Reduce Hit Time (3M)
b) Critical Word First and Early Restart to Reduce Miss Penalty (3M)
c) Compiler Optimizations to Reduce Miss Rate - Loop Interchange (4M)
(10.0 Marks)
2.c. Consider a single level paging scheme with a TLB. Assume no page fault occurs.
It takes 20 ns to search the TLB and 100 ns to access the physical memory. If TLB
hit ratio is 80%, the effective memory access time is _______ msec. (5.0 Marks)

3.a. Define True and Name dependences ? Identify the True and Name
dependences present in the given code sequence and give appropriate reasons.
(5.0 Marks)

3.b. Explain the 2-bit branch predictor with state diagram. (5.0 Marks)

3.c. In a dynamic Scheduling using Tomsula’s Approach, Show what the status
tables ( Instruction status and Reservation Station status)look like when the MUL.D
is ready to write its result
(10.0 Marks)
4.a. In Vector architecture what is strip mining? Why it is required? Explain strip
mining concept using the strip-mined version of the DAXPY loop in
C. (7.0 Marks)

4.b. Define the following with respect to Vector Execution Time


a) A convoy
b) Chime
Show how the following code sequence lays out in convoys, assuming a single copy
of each vector functional unit

How many chimes will this vector sequence take ? How many cycles per FLOP
(floating point operations) are needed, ignoring vector instruction issue overhead?
(6.0 Marks)

4.c. Explain the following


a) Private, Local, and GPU memory structure used in NVIDEA
GPU 4M
b) Write equivalent code using PTX for the following sequence of code
3M
If (i<n)
j=j+1 (7.0 Marks)

5.a. a) What are invalid, exclusive and shared states in snoopy protocol
2M
b) Write the Cache state transition for
i) Request coming from CPU and
ii) Request coming from bus for three State Write back Invalidate Snooping
Protocol. 8M (10.0 Marks)
5.b.
What is cache coherence problem? Refer below table and write contents for X in a
write update/write broadcast snoopy protocol.

(4.0 Marks)

5.c.
What are memory consistency models? Explain importance and features of
sequential consistency model with an example
(6.0 Marks)

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