Scribd
Upload
26 views4 pages

EC2092 - Foundation of Digital Design

This document is an examination paper for the B.Sc. Engineering (Hons) Degree at the Sri Lanka Institute of Information Technology, focusing on the Foundation of Digital Design. It consists of four questions covering topics such as digital circuits, Boolean algebra, and fault detection in CMOS circuits, with a total duration of 2 hours plus reading time. Candidates are instructed to answer all questions and adhere to specific examination rules, including the use of non-programmable calculators.

Uploaded by

diwyanvithana09
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
26 views4 pages

EC2092 - Foundation of Digital Design

This document is an examination paper for the B.Sc. Engineering (Hons) Degree at the Sri Lanka Institute of Information Technology, focusing on the Foundation of Digital Design. It consists of four questions covering topics such as digital circuits, Boolean algebra, and fault detection in CMOS circuits, with a total duration of 2 hours plus reading time. Candidates are instructed to answer all questions and adhere to specific examination rules, including the use of non-programmable calculators.

Uploaded by

diwyanvithana09
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

I

..........
••I.e••
••••••
SLIIT
••••••
~~~~-~

Sri Lanka Institute of Information Technology

B.Sc. Engineering (Hons) Degree


End of Semester Examination
Year 2- Semester I (2019)

EC2092- Foundation of Digital Design

Duration: 2 Hours + 10 minutes reading time

June 2019

Instructions to Candidates:

• This paper contains Four Questions.


• Answer ALL questions.
• Clearly state all the assumptions you make.
• Marks allocated for each question and sub parts are indicated.
• Faculty approved non-programmable calculators are allowed.
• This paper contains 4 pages including the cover page.
• This is a CLOSED BOOK examination.
• Strictly NO writing during the reading time.
• A formulae sheet is attached at the end of the paper.
'f/
i'
l --
//
t/
~/

./
I Question 1 (25 marks)
I

a) Sketch the single bit comparator and explain its operation. (06 marks)

b) Design a 4-to-1 multiplexer using logic gates. (06 marks)

c) Sketch the full-adder circuit and explain its operation. (06 marks)

d) Simplify the below Boolean expression using Boolean algebra and sketch the logic
circuit. (07 marks)

(A C B)( ( A + C) + ( B C)) = X

Question 2 (25 marks)

A sequential circuit is required to display the effect of a moving group oflights (LED's). These
lights move one position for each clock pulse creating the pattern shows in Figure 2.1. Design
the circuit using gates and logic of your choice to implement this requirement and describe
briefly how you would simulate your circuit for correct operation. Show all the steps followed
when designing the circuit. (25 marks)

Initial Output eee0 0 0 0 0


1st Clock 0 e e 0 0 0 0 0
2nct Clock 0 e e e 0 0 0 0
3rd Clock 0 0 e e 0 0 0 0
4th Clock 0 0 e e e 0 0 0
sth Clock 0 0 0 e e 0 0 0
6thclock 0 0 0 e e e 0 0
7th Clock 0 0 0 0 e e 0 0
(Repeats)
Figure 2.1

2
/
I
f
If Question 3 (25 marks)

a) Derive the Reed-Muller expansion ofthe following Boolean function. (11 marks)

f= A B CD + A B CD + ABC D + A B CD

b) Add-shift multipliers are widely used in arithmetic logic units (ALU's). Show the
behavior/process of the add-shift algorithm using a flowchart. Multiply 12 x 13 using
the add-shift method. Show all the steps followed when performing the calculation.
(14 marks)

Question 4 (25 marks)

a) Explain the meaning of stuck-at faults and why they can happen in CMOS
circuits. What is the result of a stuck-at '0' or a stuck-at '1' fault in a digital
circuit. (06 marks)

b) Derive the minimum number of tests required to detect all stuck-at faults for the
combinational circuit shown in Figure 4.1 using stuck-at fault model. In your
answer, clearly show which test vector test which fault. You are required to test
all the inputs and nodes for stuck-at faults. (19 marks)

A f 1
B

g
c ------~~-------4
h

D -------' k
E-----[>o----------1
Figure 4.1

End of Question Paper

3
Formulae Sheet

1) X·O=O lOA) X·Y=Y·X


2) X·l=X lOB) X+Y=Y+X
3) X·X=X llA) X(YZ)= (XY)Z
liB) X+(Y +Z)=(X +Y)+Z
4) X·X=O
12A) X(Y +Z)= XY +XZ
5) X+O=X
12B) (X+ YXW +Z)= XW +XZ +YW +YZ
6) X+l=l
13A) X+XY=X+Y
7) X+X=X
13B) X+XY=X+Y
8) X+X=l --
13C) X+XY=X+Y
9) X=X
I 3D) X+XY=X+Y
~

-
14A) XY=X+Y
14B) X+Y=X Y

You might also like