Chap.

3: Error Detection, Flow Control,

and Error Control – Part 2
2.2.2 Longitudinal Redundancy Check

An improvement can be achieved by using a second set of parity

bits.

A frame is viewed as a matrix of words. A parity bit is appended to

each word. Moreover, a parity bit is generated for each bit across
all words.

b11 b12 b1n p1

b21 b2n p2

bm1 bm2 bmn pm

w1 w2 wn wn+1

pi = bi1 Å bi2 … Å bin

wj = b1j Å b2j … Å bmj
(Even parity)

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Sender side:
The matrix is formed and transmitted one row at a time.

The receiver side:

It checks all the parity bits. If any one is wrong, it requests a
retransmission of the matrix.

An example:
Assume a Frame of 7 x 8: 7 rows and 8 columns
And assume an even parity bit.

Sender has this word to transmit:

101101001101111010010101010001010110110110. (42 bits)

What will be transmitted?

1 0 1 1 0 1 0 0
0 1 1 0 1 1 1 1
1 0 1 0 0 1 0 1
1 0 1 0 1 0 0 1
0 1 0 1 0 1 1 0
0 1 1 0 1 1 0 0
1 1 1 0 1 1 0 1

2
When does it detect errors? …

1 0 1 1 0 1 0 0
0 1 1 0 1 1 1 1
1 0 0 0 0 1 0 1
1 0 1 0 1 0 0 1
0 1 0 1 0 1 1 0
0 1 1 0 1 1 0 0
1 1 1 0 1 1 0 1

1 0 1 1 0 1 0 0
0 1 1 0 1 1 1 1
1 0 0 0 1 1 0 1
1 0 1 0 1 0 0 1
0 1 0 1 0 1 1 0
0 1 1 0 1 1 0 0
1 1 1 0 1 1 0 1

1 0 1 1 0 1 0 0
0 1 1 0 1 1 1 1
1 0 0 0 1 1 0 1
1 0 1 0 1 0 0 1
0 1 1 1 0 1 1 0
0 1 1 0 1 1 0 0
1 1 1 0 1 1 0 1

3
When it does not detect errors? …

1 0 1 1 0 1 0 0
0 1 1 0 1 1 1 1
1 0 0 0 1 1 0 1
1 0 1 0 1 0 0 1
0 1 1 1 1 1 1 0
0 1 1 0 1 1 0 0
1 1 1 0 1 1 0 1

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2.2.3 Cyclic Redundancy Check (CRC)

Sender side:
Given a k bits frame, the sender generates an n bits sequence,
known as Frame Check Sequence (FCS), so that the resulting
frame, consisting of (k + n) bits, is exactly divisible by some
predetermined bit pattern.

Receiver side:
The receiver divides the incoming frame by the same
predetermined bit pattern, and if there is no remainder, it assumes
that there was no error.

Let us define:

M = k bit message (Information to send)

T = (k + n) bit frame to be really transmitted, with n < k
M: will represent the first k bits of T

P = Pattern of (n + l) bits; (predetermined bit pattern aforementioned)

F = n bit: FCS, the last n - bits of T

T can be represented as 2nM + F.

(where note 2nM represents the shift of M by n 0’s to the left)

We would like to construct T such that T/P has no remainder.

So, how to construct T?

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Let us divide 2nM by P:

2nM = Q + R
P P

We will use this remainder (R) as our FCS.

And make T = 2nM + R

Does this T satisfy our condition?

T = 2nM + R
P P

T=Q+R+R
P P P

Any binary number added to itself modulo 2 yields zero à

T = Q + R+R = Q
P P

There is no remainder, and therefore T is exactly divisible by P.

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The procedure:

• At the Sender side, divide 2nM by P and use the remainder as

the FCS.

• At the Receiver side, divide T by P; if there is a remainder

then there is an error for sure, otherwise assume it is correct.

The pattern P is chosen to be one bit longer than the desired FCS,
and the exact bit pattern chosen depends on the type of errors
expected.

Both the high - and low - order bits of P must be 1.

Example:

1. Given Message M = 1010001101 (10 bits).

Pattern P = 1101011 (7 bits)
FCS R = to be calculated (6 bits)

2. The message is multiplied by 26 à 1010001101000000.

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This product is divided by P:

1010001101000000 ß 26M
1101011
01110101
1101011
001111001
1101011
001001000
1101011
01000110
1101011
01011010
1101011
01100010
1101011
00010010
010010 ß R

3. The remainder (R = 010010) is added to 2nM to make T =

1010001101010010.

4. If there are no errors, the receiver receives T intact. The

received frame is divided by P.

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But some errors cannot be detected … which ones?

Note: for existing protocols, standard bodies have

defined some patterns P.
This will be revisited later for specific protocols
(Layer 2 and Layer 4).

Note: See the hardware implementation in the

textbooks.