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DD Lab4

The document outlines a lab assignment for designing a combination lock using VHDL and synchronous design techniques. It details the user interface, button press detection, and state machine implementation, culminating in a combination lock that responds to a user-defined 4-digit code. The assignment emphasizes improving security by modifying the lock to handle feedback and increasing the passcode length to enhance security measures.

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11 views3 pages

DD Lab4

The document outlines a lab assignment for designing a combination lock using VHDL and synchronous design techniques. It details the user interface, button press detection, and state machine implementation, culminating in a combination lock that responds to a user-defined 4-digit code. The assignment emphasizes improving security by modifying the lock to handle feedback and increasing the passcode length to enhance security measures.

Uploaded by

ly3924266
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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MSc Digital Design

Lab 4
A simple combination lock
1 Introduction
The aim of the coursework assignment will be to design a combination lock using
VHDL and synchronous design techniques. The user interface will be simple and
based on use of the push buttons, slider switches, and LEDs on the FPGA board.

In this lab we will look at the basic techniques that will be needed, and produce a
simple prototype for part of the lock. In the assignment this prototype will be
extended and expanded to be more useful and to have more features.

2 The scenario for this lab


By the end of this lab, you will be able to receive a 4-digit combination from the user
and respond appropriately. The user interface will operate as follows:
 One of the push buttons will be used to indicate that the user wishes to enter a
code sequence.
 A digit will be entered as a binary number on the slider switches
 Once the digit has been a set up on the slider switches, a second button will be
used by the user to indicate that the first digit is ready to be read.
 The user then uses the slider switches and the second push button to enter the
remaining four digits.
 If the code sequence is correct, then some suitable visual indication will be given
(for example, you might choose to light up all the LEDs).

3 Detecting a button press


The first problem that we need to solve is how to detect a button press. Simply using
the state of the button (“pressed” or “not pressed”) is insufficient. Suppose the user’s
combination is 1, 2, 3, 4. The user will set up the number 1 on the slider switches and
then press the button. The button press will last for about a second, but the FPGA will
sample the button on each clock cycle, every 10 nanoseconds. So the FPGA will read
a sequence 1,1,1,1,1,… which is the wrong combination.

Instead, we need to detect the transition of the button from “not pressed” to “pressed”.
The obvious was to do this is with the VHDL rising_edge() function. However,
this is likely to create a problem for the synthesis tool. The normal purpose of the
rising_edge() function is to create clock signals for flip-flops, but our button is
not the FPGA clock, so synthesis would be likely to fail if we use this method.

So we need a more complicated solution. This is based on the ideas of lectures 25 and
26. It works like this:
 We create a new signal called “previous”, which is a copy of the button state but
lagging by one clock cycle. Creating a copy that lags by one clock cycle is easy:
we just put the signal assignment inside a process that is conditioned on the rising
edge of the clock.
 We check for the condition button=’1’ and previous=’0’. This means that the
button has just been pressed
 When the button has just been pressed, we set a signal called rise to ‘1’.
Here is the basic code:

process(clock)
begin
if rising_edge(clock) then
previous <= button;
if button=’1’ and previous=’0’ then
rise<=’1’;
else
rise<=’0’;
end if;
end if;
end process;

This waveform shows what happens when the button is pressed:

4 Our basic state machine


Now we can build a basic state machine that advances one state each time the button
is pressed. We will use 4 LEDs as our output display to show which state the machine
is in. Construct the state machine shown below and test that it works as expected. If
you need to revise how to create a finite state machine, you can find the details in
lecture 27.

5 Our combination lock


Now that we have solved the problem of sensing button presses, we can create our
combination lock. The code sequence that you will be required to implement is the
last four digits of your student ID number. So, for example, if your ID is 1099562,
then your code sequence will be the digits 9,5,6,2.

Modify your code so that when the button is pressed (rise=’1’) the system checks for
the appropriate number from the combination. If the number is correct we advanced to
the next state in the sequence. If the number entered is incorrect, we move back to the
state Init.
6 Improving the lock
So far we have a lock that, when it sees a wrong digit entered, will return to the initial
state and will let the user know that it is back in the initial state. This is nice for
debugging, but terrible for security as it makes it obvious when and where a wrong
number has been entered. Thieves would only need to try a very small set of numbers
before they can figure out what the correct combination should be.

Change the lock so that it will always consume four numbers, and only at the end of
the sequence of 4 numbers will give feedback on whether the combination was right
or wrong.

7 Improving the lock further


The number of different combinations that a thief has to try is determined by the
number of digits in our passcode. Increasing the number of digits in out passcode can
exponentially improve our security with a very modest increase in the complexity of
our design.

Increase the number of digits in your design to 6, with the last 6 digits of your ID
number as your passcode.

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