MSc Electronic and Computer Engineering

Digital Design

34 Finite State Machine Synthesis

In earlier lectures, we looked at the general principles of the finite state machine, and how to design an
FSM using VHDL. We looked at how to characterise the desired behaviours using a state diagram and
a state table. Then we left the implementation to the synthesis tool.

In this group of lectures, we want to look at the detail of what happens to implement a finite state
machine as logic gates and flip-flops.

34.1 Finite state machine organisation

A finite state machine produces a sequence of outputs, perhaps in response to an input sequence, or
perhaps without any inputs at all. Internally, the finite state machine has something called “state”. The
combination of current input and current state determines how the state machine will transition on the
next clock cycle.

There are two different architectures for a finite state machine: the Moore model and the Mealy model.
The Moore organisation looks like this:

The state is encoded into flip-flop bits. Transitions from one state to the next are determined by the
next state logic, a block of combinational logic which takes as its inputs the current input and the
current state. The output of the transition logic determines the state that the machine will transition to
on the next clock cycle. The current output is some Boolean function of the current state; this function
is implemented as a block of combinational logic.

The Mealy machine looks like this:

The main principles are the same as for the Moore machine. The difference is that the current output is
some Boolean function of both the current state and the current input. The Moore and Mealy machines
are similar in their expressive power, but do lead to different state sequences and differences of detail
in the designs that result. In our treatment we will look at the Moore machine.

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34.2 Finite state machine terminology
In this lecture we will look a design recipe for the blocks of logic and the flip flops that are needed to
implement a particular requirement for a finite state machine.

The terminology that we will use is as follows:

 The state variables are a group of Boolean variables stored in the memory bits of flip flops, and
serve to represent the current state of the machine
 The transition function is a combinational logic block whose outputs will determine the next state
that the machine should transition to on the next clock cycle.
 The inputs to the transition function are the current values of primary inputs (the overall inputs to
the machine) and the current values of the secondary inputs (which are the state variables fed back
to the input of the transition function).

34.3 Finite state machine design recipe

The key steps in the design of a finite state machine are:
 Characterise the required behaviour as a series of states
 Produce a state diagram to show what transitions should occur between states in response to input
values
 Translate the state diagram into a tabular form, the state table
 Choose an encoding of the state as a set of Boolean variables
 Produce a transition table that takes as its inputs the primary input and the state variables, and
delivers as its outputs the values needed to cause the required transitions in the state variables.
 Produce a Karnaugh map for each of the outputs of transition table
 Extract from these Karnaugh maps the required transition logic
 Design the output logic to produce the required output value from the values of the state variables
We’ll illustrate these steps using the example that we saw in lecture 27.

34.4 The 101 sequence detector example

In lecture 27, we saw the example of a simple FSM called seq_detect.

x
seq_detect z
clock

Its behaviour is that on each rising clock edge, new value is read at input x. The output z goes high
when input sequence ends in 101. This is illustrated with an example input and output sequence:

x=0011011001010100
z=0000010000010100

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34.4.1 The state diagram and state table
The state diagram shows how new values for x cause transitions between states (the full detail of this
is explained in lecture 17):

0 1
S0 1 S1
0 0
Input = x
1 0 0 Output = z

S3 1 S2
1 0 0

With state diagrams, it is easy to overlook a transition, so we translate the state diagram into a tabular
form in order to check for any missing entries. The state table conveys the same information as the
state diagram, but in tabular form. For each state that the device could be in, it lists what the next state
will be for any possible value of the input.

Present state Next state

x=0 x=1
S0 S0 S1
S1 S2 S1
S2 S0 S3
S3 S2 S1

34.4.2 The state encoding

We need to represent the states S0, S1, S2, S3 in a way suitable for implementing as Boolean variables
in flip-flops. Four distinct states can be represented as two bits.

There are many different choices that we could make, but we’ll make an arbitrary choice to represent
our states as
 S0 is Q1=0, Q0=0
 S1 is Q1=0, Q0=1
 S2 is Q1=1, Q0=0
 S3 is Q1=1, Q0=1

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34.4.3 The transition table
We now design the transition logic. We take the state table and re-write it using the encoding of the
states. So, for example, if we are currently in state S1 then Q1=0 and Q2=1. If we then receive an input
x=0, the next state to which we will transition is state S2 (which is Q1=1, Q0=0). On the other hand, if
we receive an input x=1, the next state to which we will transition is state S1 (which is Q1=0, Q0=1)

Inputs Outputs
Q1 Q0 x D1 D0
0 0 0 0 0
0 0 1 0 1
0 1 0 1 0
0 1 1 0 1
1 0 0 0 0
1 0 1 1 1
1 1 0 1 0
1 1 1 0 1

The inputs to the transition table are the current values of input x and state variables Q1 and Q0

The outputs of the transition logic are the inputs to the D flip flops that store the state variables. These
D inputs will be ignored until the rising edge of the clock, and when that edge happens the value at the
D inputs will be read into the Q memory bits. So the outputs in the table above are showing what state
we must transition to in the next clock cycle.

34.4.3 Extraction of the transition logic

Now that we know required outputs of the transition function, we must design the logic that will
accomplish this function. We need two Karnaugh maps: one for D1 and one for D0.

Q1Q0 Q1Q0
x 00 01 11 10 x 00 01 11 10
0 1 1 0

1 1 1 1 1 1 1
D1 D0

This gives us our transition logic:

𝐷 = 𝑄 . 𝑥̅ + 𝑄 . 𝑄 . 𝑥
𝐷 =𝑥

34.4.4 Output function

We also need to design the logic for the output function. When we are in state S3 (so Q1=1, Q0=1) the
output z must be 1. In all other states it must be 0. This is trivially accomplished by an AND gate:

𝑧 = 𝑄 .𝑄

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34.4.5 The completed design
We now have our completed design, expressed as logic gates and D flip flops:

34.5 Analysis of the design

As a check on the correctness of our design, we’ll check how it responds to the input sequence 0101 …
The process of taking a design, giving it some inputs and computing the resulting outputs is called
analysis.

The initial condition will be Q1=0, Q0=0. The input in the first clock cycle will be x=0. The transition
logic will compute new values for D1 and D0:

𝐷 = 𝑄 . 𝑥̅ + 𝑄 . 𝑄 . 𝑥 = 0.1.0 + 0.1 = 0
𝐷 =𝑥=0

At the next clock cycle, these values at D1 and D0 will be loaded into Q1 and Q0. That means in the
next cycle we will move to state S0.

Using this process, we can now draw up a table for what will happen in subsequent clock cycles:

Values in this clock cycle Next cycle

Cycle x Q1 Q0 D1 D0 Q1+ Q0+
1 0 0 0 0 0 0 0
2 1 0 0 0 1 0 1
3 0 0 1 1 0 1 0
4 1 1 0 1 1 1 1

So the state sequence followed in response to the input 0101 is S0, S0, S1, S2, S3. The output z will be
zero for S0, S1, S2 and 1 when the machine moves into state 3.

This confirms the required behaviour, so it gives us confidence that the design is correct.

You should now know...

 The difference between a Moore machine and a Mealy machine
 The key stages in the implementation of a Moore model finite state machine using D flip-flops
 How to analyse a finite state machine design by giving it inputs and predicting what the outputs
would do

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35 Finite State Machine Synthesis using T Flip Flops
The state of a finite state machine must be stored as Boolean variables inside flip-flops. In the last
lecture we looked at an example that used D flip flops. In this lecture, we will design the same system
using T flip-flops.

35.1 The example system

We will carry out our example design using the same example as the last lecture, the 101 sequence
detector. The output z goes high each time the input sequence 101 on successive clock cycles is
detected.

x Example sequence:
seq_detect z x=0011011001010100
clock z=0000010000010100

The state diagram for this system has been derived previously as:

Present state Next state

x=0 x=1
S0 S0 S1
S1 S2 S1
S2 S0 S3
S3 S2 S1

We will choose to encode our states in the same way as previously:

 S0 is Q1=0, Q0=0,
 S1 is Q1=0, Q0=1,
 S2 is Q1=1, Q0=0,
 S3 is Q1=1, Q0=1,

35.2 The overall architecture using T flip flops

We now need to map our design to this architecture:

The T flip-flop regards the T input as a toggle instruction: T=1 means that Q should toggle its value;
T=0 means that Q should hold its value.

The transition function will take as its inputs the current value of input x and the current value of the
state variables Q1 and Q0. It will produce at its output the values of T1 and T0 that are required to cause
Q1 and Q0 to make the required transition at the next clock cycle.
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35.3 The behaviour of the T flip flop
The transition table for the T flip-flop tells us how the value of Q will behave in response to an input
value of T:

T at the clock edge Q at the clock edge Q after the clock edge
0 0 0
0 1 1
1 0 1
1 1 0

The alternative (or reverse) form of the transition table for the T flip-flop tell us what value of T we
need to apply to a T flip flop to guide its value of Q to the desired value after the clock edge:

Q at the clock edge Desired Q after the Required T at the clock

clock edge edge
0 0 0
1 1 0
0 1 1
1 0 1

35.4 The transition table

We now design the transition logic. We take the state table and re-write it using the encoding of the
states. So, for example, if we are currently in state S1 then Q1=0 and Q2=1, and we receive an input
x=0, the next state to which we will transition is state S2 (which is Q1=1, Q0=0). That means that we
will need Q1 to toggle in the next clock cycle, so we need the transition logic to produce T1=1. Also we
will need Q0 to toggle in the next clock cycle, so we will need the transition logic to produce T0=1.

Inputs What we want to The value of T

happen next required
Q1 Q0 x Q1 Q0 T1 T0
0 0 0 0 0 0 0
0 0 1 0 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 0 0
1 0 0 0 0 1 0
1 0 1 1 1 0 1
1 1 0 1 0 0 1
1 1 1 0 1 1 0

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35.5 Extraction of the transition logic
Now that we know required outputs of the transition function, we must design the logic that will
accomplish this function. We need two Karnaugh maps: one for T1 and one for T0.

Q1Q0 Q1Q0
x 00 01 11 10 00 01 11 10
x
0 1 0 1 1
1 1 1 1 1 1
T1 T0

𝑇 = 𝑄 . 𝑄 . 𝑥̅ + 𝑄 . 𝑥
𝑇 = 𝑄 . 𝑥̅ + 𝑄 . 𝑥

35.6 Output function

When we are in state S3 (so Q1=1, Q0=1) the output z must be 1. In all other states it must be 0. This is
trivially accomplished by an AND gate:

𝑧 = 𝑄 .𝑄

35.7 The completed design

We now have our completed design, expressed as logic gates and T flip flops:

You should now know...

 How to use the T inputs to flip flops to control the transition that they make on the next clock
cycle
 The key stages in the implementation of a Moore model finite state machine using T flip-flops

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36 Finite State Machine Optimisation
In the last two lectures we saw the basic principles of finite state machine implementation. However,
the example that we looked at had “nice” properties because the number of states required was an
exact power of 2. In this lecture we will look at another example of finite state machine synthesis. This
time the number of states will not be an exact power of two, which will lead us to the idea of unused
states. The manner in which we treat these unused states an influence the robustness and the efficiency
of the resulting implementation. In this lecture we will look at how to produce a robust and efficient
design.

36.1 The example system

For this example, we are given the following specification:
 Design a synchronous finite state machine with one input (UD) and three outputs (Qc,Qb,Qa).

Qc
Finite
UD State Qb
Machine
Qa

Clock

 When UD=1 the machine transits cyclically through the sequence {000,001,011,100,101,111,000}.
 When UD=0 the machine transits cyclically through the sequence {000,100,101,111,011,001,000}.
 The machine is to use D-type flip-flops.
 The design must minimise the complexity of the logic gates used.

36.2 The state diagram

We’ll build up our state diagram in stages. First, we consider when UD=1, the machine transits
cyclically through the sequence {000,001,011,100,101,111,000, etc.}.
1 1
Sa Sb Sd

000 001 011

UD
1
1
Sh Sf Se

111 101 100

1 1
Output
Qc,Qb,Qa

Then we consider when UD=0, the machine transits cyclically through the sequence
{000,100,101,111,011,001,000, etc.}.
UD

0 0

Sa Sb Sd

000 001 011

0

0
Sh Sf Se

111 101 100

0 0 Output
Qc,Qb,Qa

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Now we combine the two to get our overall state diagram:
UD

0 0

1 1
Sa Sb Sd

000 001 011

0
1 1
0
Sh Sf Se

111 101 100

1 1
0 0 Output
Qc,Qb,Qa

36.3 The state table

We now create the state table for the above diagram

Present state Next state

UD=0 UD=1
Sa Se Sb
Sb Sa Sd
Sd Sb Se
Se Sf Sf
Sf Sh Sh
Sh Sd Sa

It’s easy to make a mistake on a state diagram and omit some transitions. These would become clear
as gaps in the table. But we don’t see any gaps: that means our state diagram is correct., so we
continue with our design.

36.4 The state encoding

So far, the process has been the same as we’ve seen before. But now we have something new. The
number of states is not an exact power of two. In order to represent 6 states, we need 3 Boolean state
variables. But 23 gives us 8 different possible codes to represent states. That means that our encoding
introduces two new states that we didn’t really want. We’ll call them Sc and Sg. Our state encoding
looks like this:

State Qc Qb Qa
Sa 0 0 0
Sb 0 0 1
Sc 0 1 0
Sd 0 1 1
Se 1 0 0
Sf 1 0 1
Sg 1 1 0
Sh 1 1 1

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Our revised state diagram now looks like this:

UD

0 0

1 1
Sa Sb Sc Sd

000 001 010 011

?
0
1
1
0 ?
Sh Sg Sf Se

111 110 101 100

1 1
0 0 Output
Qc,Qb,Qa

Now we need to figure out what to do about Sc and Sg. It is tempting to simply ignore them, and
continue our design by looking at only the six states that we wanted. However, that could create
problems. With some types of hardware, the state at turn-on is randomised. It would be possible
sometimes to turn the device on and the flip flop bits randomly initialise to 010, putting us into state
Sc. Things would get serious if it turned out that the logic we had designed for the 6 wanted states
accidentally caused Sc to transition into Sg and state Sg to transition into Sc. That would mean that
sometimes when the system powers on it locks into on erroneous state transitioning between Sc and Sg
continuously and never reaching the desired sequence.

So we will need to plan for the possibility of initialisation into Sc or Sg, and to cause them to transition
on the next clock cycle into one of our allocated states. There is a huge number of ways that we could
choose to do this, and some of these will lead to efficient logic and other swill be inefficient. We want
to choose a good solution. We have a total of 4 transitions out of Sc and Sg, and each of those could
route to one of 6 different states. So we have 64 = 1296 different ways to do this. Looking at all
possible solutions exhaustively isn’t feasible.

36.5 The transition table

The way that we will handle this is to give symbolic names to the next states for Sc and Sg, and
incorporate these symbolic names into our design process. The names we give are as follows:

When in Sc and the input is 0, the machine will transition to Qc=wc, Qb=wb, Qa=wa
When in Sc and the input is 1, the machine will transition to Qc=xc, Qb=xb, Qa=xa
When in Sg and the input is 0, the machine will transition to Qc=yc, Qb=yb, Qa=ya
When in Sg and the input is 1, the machine will transition to Qc=zc, Qb=zb, Qa=za

As we complete the process, we will figure out the best values to assign to these symbolic names.

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We now draw up our transition table:

Present State Next State Required value of D

State Qc Qb Qa UD State Qc Qb Qa Dc Db Da
Sa 0 0 0 0 Se 1 0 0 1 0 0
Sa 0 0 0 1 Sb 0 0 1 0 0 1
Sb 0 0 1 0 Sa 0 0 0 0 0 0
Sb 0 0 1 1 Sd 0 1 1 0 1 1
Sc 0 1 0 0 ? Wc Wb Wa Wc Wb Wa
Sc 0 1 0 1 ? Xc Xb Xa Xc Xb Xa
Sd 0 1 1 0 Sb 0 0 1 0 0 1
Sd 0 1 1 1 Se 1 0 0 1 0 0
Se 1 0 0 0 Sf 1 0 1 1 0 1
Se 1 0 0 1 Sf 1 0 1 1 0 1
Sf 1 0 1 0 Sh 1 1 1 1 1 1
Sf 1 0 1 1 Sh 1 1 1 1 1 1
Sg 1 1 0 0 ? Yc Yb Ya Yc Yb Ya
Sg 1 1 0 1 ? Zc Zb Za Zc Zb Za
Sh 1 1 1 0 Sd 0 1 1 0 1 1
Sh 1 1 1 1 Sa 0 0 0 0 0 0

We now create Karnaugh maps for Dc, Db and Da, and choose to treat each of the symbolic names as
1 or 0 according to which gives us the simplest transition logic.

Qa,UD Qa,UD Qa,UD

Qc,Qb 00 01 11 10 Qc,Qb 00 01 11 10 Qc,Qb 00 01 11 10

00 1 00 1 00 1 1

01 Wc Xc 1 01 Wb Xb 01 Wa Xa 1

11 Yc Zc 11 Yb Zb 1 11 Ya Za 1

10 1 1 1 1 10 1 1 10 1 1 1 1

Dc Db Da

From these Karnaugh maps, we read off the D-inputs of the unallocated state destinations:

W = 101, X = 100, Y = 101, Z = 000

These have been extracted on the basis of minimising the complexity of the required logic. However,
there is no guarantee that this is an acceptable solution. So we’ll need to re-draw the state diagram
including these transitions:

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 UD

0 0

1 1
Sa Sb Sc Sd

000 001 010 011

0
0 1 1
1
0
Sh 1 Sg 0 Sf Se

111 110 101 100

1 1
0 0 Output
Qc,Qb,Qa

We find that Sc and Sg do indeed transition on the next clock cycle to an allocated state, so this
solution is acceptable. If this were not the case, we would need to return to our Karnaugh maps and
iterate extracting other alternative solutions and constructing the state diagram until we found an
acceptable solution.

The Karnaugh maps give us our solution:

𝐷𝑎 = 𝑄𝑐. 𝑄𝑏 + 𝑄𝑏. 𝑈𝐷 + 𝑄𝑏. 𝑈𝐷

𝐷𝑏 = 𝑄𝑏. 𝑄𝑎. 𝑈𝐷 + 𝑄𝑐. 𝑄𝑎. 𝑈𝐷
𝐷𝑐 = 𝑄𝑐. 𝑄𝑏 + 𝑄𝑎. 𝑈𝐷 + 𝑄𝑐. 𝑄𝑏. 𝑈𝐷

36.6 The final implementation

Our final implementation looks like this:

Note that in this example, we have not needed any output logic as the state encodings were chosen to
be identical to the required outputs

You should now know...

 Why a number of states that is not a power of two leads to unallocated states
 Why these unallocated states must be forced to transition to an allocated state
 How to minimise the complexity of the resulting logic

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37 Designing a Finite State Machine with no output logic
The standard architecture of a Moore finite state machine is:

There can sometimes be advantages (and disadvantages) in designing a machine with no output logic.

This means that the required output values must be contained within some subset of the state variables.
In the last lecture we saw an example where this was easy to achieve because the obvious state
encoding was identical to the required outputs. In this lecture, we’ll look at an example where
circumstances are less convenient.

37.1 The example system

We will carry out our example design using the same example as the last lecture, the 101 sequence
detector. The output z goes high each time the input sequence 101 on successive clock cycles is
detected.

x Example sequence:
seq_detect z x=0011011001010100
clock z=0000010000010100

The state diagram for this system has been derived previously as:

Present state Next state

x=0 x=1
S0 S0 S1
S1 S2 S1
S2 S0 S3
S3 S2 S1

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37.2 The state encoding
Previously we chose our encoding as this:
 S0 is Q1=0, Q0=0,
 S1 is Q1=0, Q0=1,
 S2 is Q1=1, Q0=0,
 S3 is Q1=1, Q0=1,

In the absence of output logic, we would need to find some subset of the state variables that is 1 when
in S3 and 0 in all other states. No such subset exists for the encoding above, so we will need to change
the state encoding. We will have to include an extra bit Q2 in our state encoding to provide the output.
 S0 is Q2=0, Q1=0, Q0=0,
 S1 is Q2=0, Q1=0, Q0=1,
 S2 is Q2=0, Q1=1, Q0=0,
 S3 is Q2=1, Q1=1, Q0=1,

Now we can simply feed the value of Q2 through to our output z.

37.3 Dealing with unallocated states

Increasing the number of state variables to 3 means that there are now 23=8 state codes, and only 4 of
them have been allocated in our design. It is possible that at power-up, randomisation of the initial
state of flip flop bits could cause one of the unallocated states to intermittently occur, and we will need
to ensure that they transition to an allocated state in the next clock cycle. We will give names to the
unallocated states as follows:
 Sa is Q2=0, Q1=0, Q0=0,
 Sb is Q2=0, Q1=0, Q0=1,
 Sc is Q2=0, Q1=1, Q0=0,
 Sd is Q2=0, Q1=1, Q0=1,

For this example, we will cause them all to transition to S0 at the next clock cycle, regardless of the
value of the input x. This gives us the following transition table

Inputs to transition logic Outputs of transition logic

Q2 Q1 Q0 x D2 D1 D0
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 0 0 1 0
0 0 1 1 0 0 1
0 1 0 0 0 0 0
0 1 0 1 1 1 1
0 1 1 0 0 0 0
0 1 1 1 0 0 0
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 0 0
1 0 1 1 0 0 0
1 1 0 0 0 0 0
1 1 0 1 0 0 0
1 1 1 0 0 1 0
1 1 1 1 0 0 1

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37.4 Extraction of the transition logic
We now transfer the transition table to Karnaugh maps for D2, D1 and D0

This gives us our solution:

𝐷 = 𝑄 .𝑄 .𝑄 .𝑥
𝐷 = 𝑄 . 𝑄 . 𝑄 . 𝑥 + 𝑄 . 𝑄 . 𝑄 . 𝑥̅ + 𝑄 . 𝑄 . 𝑄 . 𝑥̅
𝐷 = 𝑄 . 𝑄 .𝑥 + 𝑄 .𝑄 .𝑥 + 𝑄 .𝑄 .𝑄 .𝑥

You should now know...

 How to avoid the need for output logic in a Moore machine by incorporating additional
information into the state variable encoding

16
 Index

34 Finite State Machine Synthesis 1

34.1 Finite state machine organisation 1
34.2 Finite state machine terminology 2
34.3 Finite state machine design recipe 2
34.4 The 101 sequence detector example 2
34.4.1 The state diagram and state table 3
34.4.2 The state encoding 3
34.4.3 The transition table 4
34.4.3 Extraction of the transition logic 4
34.4.4 Output function 4
34.4.5 The completed design 5
34.5 Analysis of the design 5
35 Finite State Machine Synthesis using T Flip Flops 6
35.1 The example system 6
35.2 The overall architecture using T flip flops 6
35.3 The behaviour of the T flip flop 7
35.4 The transition table 7
35.5 Extraction of the transition logic 8
35.6 Output function 8
35.7 The completed design 8
36 Finite State Machine Optimisation 9
36.1 The example system 9
36.2 The state diagram 9
36.3 The state table 10
36.4 The state encoding 10
36.5 The transition table 11
36.6 The final implementation 13
37 Designing a Finite State Machine with no output logic 14
37.1 The example system 14
37.2 The state encoding 14
37.3 Dealing with unallocated states 15
37.4 Extraction of the transition logic 16

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