Introduction

General-purpose microprocessor
• CPU for Computers
• No RAM, ROM, I/O on CPU chip itself
• Example：Intel’s x86, Motorola’s 680x0

Many chips on mother’s board

Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus

General-Purpose Microprocessor System

 Introduction
• The term PIC originally stands for “Programmable
Intelligent computer” but now more commonly
called as “Peripheral Interface Controller”. It is
the brain child of Microchip Technology, USA .
• The first microcontroller offered by Microchip in
1989 had small amounts of data RAM, a few
hundred bytes of on-chip ROM for the program,
one timer, and a few pins for I/O ports, all on a
single chip. The device was available with only 8
pins.
• PICs are popular with both industrial
developers and hobbyists alike due to their
low cost, wide availability, large user base,
extensive collection of application notes,
availability of low cost or free development
tools, and serial programming (and re-
programming with flash memory) capability.
 Difference between PIC 16F and
PIC18F microcontrollers
• There are many architectural as well as peripheral
differences between the two families.
• Both have flash memories but PIC 18F vary on
account of Larger instruction Set, some more
hardware features, usually more RAM/ROM, Higher
Clock Frequency, Stack (and the method of Indirect
addressing), Instruction size, Program Counter,
simpler banking. All of the SFRs on most 18F PICs are
in the same bank. So it provides easier SFR access
rather than switching banks to access I/O ports
 PIC 16F and PIC 18F comparison*
PIC 16F877A PIC18F4550
Pin Count: 40-pin PDIP Pin Count: 40-pin PDIP
I/O PIN : 33 I/O PIN : 35
Program Memory: 14KB or 8K 14-bit Flash Program Memory 32 KB Flash
Max Crystal Speed: 20MHz Max Crystal Speed: 48MHz or 12 MIPS
Internal Oscillator : No Internal Oscillator : 31kHz to 4Mhz
RAM Bytes: 368 EEPROM (bytes): 256
EEPROM (Bytes): 256 Timers: 1 x 8-bit, 3 x 16-bit
Timers: 2 x 8 bit, 1 x 16-bit Serial Communication Peripherals: 1-
Serial Communication: 1xUSART, 1 x EUSART, 1-MSSP(SPI/I2C)
MSSP(SPI/I2C) ADC: 13 ch, 10-bit
Capture/Compare/PWM: 2 x CCP Capture/Compare/PWM Peripherals: 1
ADC: 8ch, 10-bit CCP, 1 ECCP,
Comparators: 2 Comparators: 2

*source: https://robu.in/pic16f-vs-pic18fanalysis-pic-mid-range-8-
bit-family-advanced-8-bits-family/
 PIC 18F

Specifications of PIC18F Family Members*

*Source PIC Microcontroller and Embedded Systems Using Assembly and C for PIC18 MA Mazidi,
Rolin D Mckinlay, Danny Causey. Pearson International Edition.
 PIC18FXXX High End Microcontroller
• 16-bit instructions
• a deeper stack, and an interrupt system that can
handle internal interrupts as well as several
inputs for external interrupts.
• Some of these PICs have an open architecture.
This allows the increase of both program memory
• and data memory.
• The number of available devices for high-end
microcontrollers is also larger.
 PIC18Fxxx Features
• Microcontrollers that belong to the PIC18 family have flash memory and
an instruction set of 77 instructions of 16 bits each.
• Their program memory can have a size of up to 2 MB, and their data
memory can reach 4096 registers of 8 bits in each one.
• Some members of the PIC18 family allow external memory to store
program memory.
• Their stack is 31 levels deep;
PIC18Fxxx Architecture*
 PIC Architecture
• PIC 18F has Harvard Architecture and is a RISC
type of processor.
• It uses two separate address buses to access code
and data memory unlike von-Neumann
architecture where both code and data memories
are accessed through same buses.
• This increases speed of processing. Apart from
this the Reduced Instruction Set reduces the
number of transistors required to decode the
instructions.
 PIC Architecture
• Almost all the instructions in the PIC18 are 2-byte instructions
leaving few instructions which are 4 byte.
• PIC being a RISC processor has a large number of registers.
• RISC processors have a small instruction set. RISC processors
have only the basic instructions such as ADD, SUB, MUL,
LOAD, STORE, AND, OR, EXOR, CALL, JUMP, and so on.
• The program may get lengthy if written in
assembly language, but the most important
characteristic of the RISC processors is that
more than 95% of instructions are executed
with only one clock cycle
• The speed of execution further increases with
code scheduling and pipelining features.
• Program Counter (PC) keeps track of the program execution by
holding the address of the current instruction. It is automatically
incremented to the next instruction during the current instruction
execution.
• The stack is used to store the address of the next instruction
immediately below the CALL instruction.
• The CALL instruction is used to jump to a subroutine, which must be
terminated with the RETURN instruction. CALL has the address of
the first instruction in the subroutine as its operand.
• When the CALL instruction is executed, the destination address is
copied to the PC. The PC is PUSHed onto the stack when a CALL
instruction is executed, or an interrupt causes a branch. The stack is
POP’ed in the event of a RETURN, RETLW or a RETFIE instruction
execution.
 Main CPU Registers
The CPU registers are
• Working Register (Wreg)
• Status – Register; psw
• FSR – File Select Register
• INDF
• Program Counter
• Stack
 Working (Wreg) Register
• The working register in PIC has features similar
to Accumulator of Intel 8051 microcontroller.
• It is an eight bit register.
• The Wreg as destination register is not fixed in
arithmetic and logical instructions unlike
accumulator in 8051.
 Examples showing use of Wreg
• The MOVLW instruction format is
• MOVLW K; K is a literal 8 bit value to be
moved into working register W.
• The instruction stands for: Move the literal
value specified by K into register W.
• Ex MOVLW 20H will move 20 H into register
W.
• MOVLW 40H ; MOVE THE LITERAL VALUE IN
WORKING REGISTER
• MOVWF 30H ; WREG INTO FILE LOCATION
WHOSE ADDRESS IS 30H
 Arithmetic and logic unit (ALU)
The ALU executes the arithmetic and logic operations available in the instruction set.
There is one register associated with the ALU that temporarily stores at least one
operand involved in the operation, as well as the result of that operation.
The ALU also has bits to indicate specific characteristics of the resulting value, such as
if the result is zero, the sign of the resulting value, or the existence of carry over. These
bits are normally part of the STATUS register.
In most microprocessors and microcontrollers the register associated with the ALU is
called the accumulator (ACC). In PIC microcontrollers the register associated with the
ALU is called the W register. The W register carries out tasks similar to the ACC, it is
positioned in a different place. Therefore, the ACC and the W register do not operate
in the same way.
In traditional architectures, the ACC is placed at the output of the ALU, so it always
stores the result of an arithmetic or logic operation. In PIC microcontrollers, however,
the result of an operation can either be placed in the W register or in any register in
the data memory
ALU OPERATIONS
ADDLW 0AFH
 Instruction Execution and Machine cycle
There are three phases in the execution of a program
instruction: fetch, decode, and execution
 Pipe Lining

• The first step fetches the instruction that will be executed in

the second step.
• Each step lasts one machine cycle (MC). The pipeline has two
different instructions in the two steps.
• Each instruction stays in the pipeline for 2 MC, therefore there
is one instruction leaving the pipeline each MC.
 Oscillators
• The main oscillator in PIC microcontrollers can be a crystal
oscillator, an RC oscillator, or an external clock. Some
devices also have an internal RC oscillator at 4 MHz.
• configuration bits select specific modes of operation for
crystal or ceramic oscillators: LP, XT, and HS.
• The LP mode selects oscillator frequencies between 32 kHz
and 200 kHz, and is used in very low power-consumption
applications.
• The XT mode selects oscillator frequencies between 100
kHz and 4 MHz.
• The HS mode selects oscillator frequencies between 8 MHz
and 20 MHz.
External oscillator in a PIC
 Configuration Bits

The configuration bits allow the programmer to

specify certain aspects of the microcontroller to
better fit the intended application:
• Type of oscillator
• Watchdog timer on or off
• Program memory protection
• Protection of EEPROM data if available
• Specifications for reset and power supply
 Configuration Bits
CP1, CP0: FLASH program memory code LVP: Low voltage In-circuit serial
protection: programming:
11 - Code protection off 1 - enabled
10 - Only last 256 cells (F00h to FFFh)
0 - disabled
protected
01 - Only page 1 (800h to FFFh) protected BODEN: Brown-out reset:
00 - All memory protected (000h to FFFh) 1 - enabled
DEBUG: In-circuit Debugger mode 0 - disabled
1 - disabled (RB6 and RB7 are general purpose PWRTE#: Power-up timer:
I/O pins) 1 - disabled
0 - enabled (RB6 and RB7 are dedicated to the 0 - enabled
debugger) WDTE: Watchdog timer:
WRT: FLASH program memory write enable:
1 - enabled
1 - enabled
0 - disabled 0 - disabled
CPD: Data EEPROM memory code protection: FOSC1, FOS0: Oscillator selection bits:
1 - Code protection off 11 - RC
0 - Code protection on 10 - HS
01 - XT
00 - LP
 Reset Options
In PIC microcontrollers, reset sets the program
counter to zero.
Reset sources
• External reset
• Power-on reset
• Watchdog reset
• Brown-out reset
RESET SCHEMATIC
• The reset circuit has to guarantee that the
microcontroller will only leave the reset state
if the main oscillator is working and is stable.
• This is the task of the block labeled OST/PWRT.
MANUAL RESET
POWER ON RESET
BROWN OUT RESET (BOR)
 MEMORY ORGANIZATION
• Program Memory
• Data RAM
• Data EEPROM
Data and program memory use separate busses,
which allows for concurrent access of these
blocks
 Program Memory Organization
• A 21-bit program counter is capable of addressing the 2-
Mbyte program memory space
• Max. of 32 Kbytes of FLASH memory available
• can store up to 16K of single word instructions
• The RESET vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
PROGRAM MEMORY MAP AND STACK FOR PIC18F452/252
 Addressing Program Memory
PCL,PCH,PCU, PCLATH and PCLATU
The program counter (PC) specifies the address of the instruction to fetch for
execution. The PC is 21-bits wide.
The low byte is called the PCL register. This register is readable and writable.
The high byte is called the PCH register.
This register contains the PC<15:8> bits and is not directly readable or
writable. Updates to the PCH register may be performed through the PCLATH
register.
The upper byte is called PCU. This register contains the PC<20:16> bits and is
not directly readable or writable. Updates to the PCU register may be
performed through the PCLATU register.
The PC increments by 2 to address sequential instructions in the program
memory.
• The CALL, RCALL, GOTO and program branch instructions write to the
program counter directly.
 Instructions in Program Memory

The program memory is addressed in bytes. Instructions are stored as two bytes or four
bytes in program memory.
The Least Significant Byte of an instruction word is always stored in a program memory
location with an even address (LSB =’0’).
To maintain alignment with instruction boundaries, the PC increments in steps of 2.
The CALL and GOTO instructions have an absolute program memory address embedded
into the instruction.
The data contained in the instruction is a word address. The word address is written to
PC<20:1>, which accesses the desired byte address in program memory. Instruction #2
shows how the instruction “GOTO 000006h’ is encoded in the program memory. The
offset value stored in a branch instruction represents the number of single word
instructions that the PC will be offset by.
• The PIC18FXX2 devices have four two-word
instructions: MOVFF, CALL, GOTO and LFSR.
 Return Address Stack
• The return address stack allows any combination of up to 31 program calls and interrupts to
occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL
instruction is executed, or an interrupt is acknowledged. The PC value is pulled off the stack
on a RETURN, RETLW or a RETFIE instruction.
• PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.
• The stack operates as a 31-word by 21-bit RAM and a 5-bit stack pointer, with the stack
pointer initialized to 00000b after all RESETS.
• There is no RAM associated with stack pointer 00000b. This is only a RESET value.
• During a CALL type instruction, causing a push onto the stack, the stack pointer is first
incremented and the RAM location pointed to by the stack pointer is written with the contents
of the PC.
• During a RETURN type instruction, causing a pop from the stack, the contents of the RAM
location pointed to by the STKPTR are transferred to the PC and then the stack pointer is
decremented.
• The stack space is not part of either program or data space. The stack pointer is readable and
writable, and the address on the top of the stack is readable and writable through SFR
registers. Data can also be pushed to, or popped from, the stack using the top-of-stack SFRs.
 TOP-OF-STACK ACCESS
• The top of the stack is readable and writable.
• Three register locations TOSU, TOSH and TOSL hold the
contents of the stack location pointed to by the STKPTR
register.
• This allows users to implement a software stack if
necessary.
• After a CALL, RCALL or interrupt, the software can read the
pushed value by reading the TOSU, TOSH and TOSL
registers.
• These values can be placed on a user defined software
stack.
• At return time, the software can replace the TOSU, TOSH
and TOSL and do a return.
RETURN STACK POINTER (STKPTR)
RETURN STACK POINTER (STKPTR)
 RETURN STACK POINTER (STKPTR)
• The STKPTR register contains the stack pointer value, the STKFUL (stack full) status bit, and the
STKUNF
• (stack underflow) status bits.
• The value of the stack pointer can be 0 through 31. The stack pointer increments when values are pushed
onto the stack and decrements when values are popped off the stack.
• At RESET, the stack pointer value will be 0. The user may read and write the stack pointer value.
• After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit
is set. The STKFUL bit can only be cleared in software or by a POR.
• The action that takes place when the stack becomes full depends on the state of the STVREN (Stack
Overflow
• Reset Enable) configuration bit. If STVREN is set (default), the 31st push will push the (PC + 2) value onto
the stack, set the STKFUL bit, and reset the device. The STKFUL bit will remain set and the stack pointer
will be set to ‘0’.
• If STVREN is cleared, the STKFUL bit will be set on the 31st push and the stack pointer will increment to
31.
• Any additional pushes will not overwrite the 31st push, and STKPTR will remain at 31.
Data Memory Organization Map
 Data Memory Organization
• The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory.
• The data memory map is divided into as many as 16 banks that contain 256 bytes each.
• The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed.
• The upper 4 bits for the BSR are not implemented.
• The data memory contains Special Function Registers (SFR) and General Purpose Registers (GPR).
• The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data
• storage and scratch pad operations in the user’s application.
• The SFRs start at the last location of Bank 15 (0xFFF) and extend downwards.
• Any remaining space beyond the SFRs in the Bank may be implemented as GPRs. GPRs start at the first
location of Bank 0 and grow upwards.
• Any read of an unimplemented location will read as ’0’s.
• The entire data memory may be accessed directly or indirectly.
• Direct addressing may require the use of the BSR register.
• Indirect addressing requires the use of a File Select Register (FSRn) and a corresponding Indirect File Operand
(INDFn).
• Each FSR holds a 12-bit address value that can be used to access any location in the Data Memory map without
banking.
• The instruction set and architecture allow operations across all banks.
• This may be accomplished by indirect addressing or by the use of the MOVFF instruction. The MOVFF
instruction is a two-word/two-cycle instruction that moves a value from one register to another.
• To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, regardless of
the current BSR values, an Access Bank is implemented.
• A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM.
 GENERAL PURPOSE REGISTER FILE
• The register file can be accessed either directly or
indirectly.
• Indirect addressing operates using a File Select
Register and corresponding Indirect File Operand.
• Data RAM is available for use as GPR registers by
all instructions.
• The top half of Bank 15 (0xF80 to 0xFFF) contains
SFRs.
• All other banks of data memory contain GPR
registers, starting with Bank 0.
 SPECIAL FUNCTION REGISTERS
• The Special Function Registers (SFRs) are registers used
by the CPU and Peripheral Modules for controlling the
desired operation of the device.
• These registers are implemented as static RAM.
• The SFRs can be classified into two sets; those
associated with the core” function and those related to
the peripheral functions..
• The SFRs are typically distributed among the
peripherals whose functions they control.
• The unused SFR locations will be unimplemented and
read as '0's.
SPECIAL FUNCTION REGISTERS MAP
SPECIAL FUNCTION REGISTERS SUMMARY
SPECIAL FUNCTION REGISTERS SUMMARY
 Access Bank

• While the use of the BSR, with an embedded 8-bit address, allows users to address the entire
range of data memory, it also means that the user must always ensure that the correct bank
is selected. Otherwise, data may be read from or written to the wrong location.
• To streamline access for the most commonly used data memory locations, the data memory
is configured with an Access Bank, which allows users to access a mapped block of memory
without specifying a BSR.
• The Access Bank is comprised of the upper 128 bytes in Bank 15 (SFRs) and the lower 128
bytes in Bank 0.
• These two sections will be referred to as Access RAM High and Access RAM Low, respectively.
• A bit in the instruction word specifies if the operation is to occur in the bank specified by the
BSR register or in the Access Bank.
• This bit is denoted by the ’a’ bit (for access bit).
• When forced in the Access Bank (a = 0), the last address in Access RAM Low is followed by
the first address in Access RAM High.
• Access RAM High maps the Special Function registers, so that these registers can be
accessed without any software overhead. This is useful for testing status flags and modifying
control bits.
 Access Bank
The Access Bank is an architectural enhancement THAT ALLOWS data memory region can be used for:
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
• Faster evaluation/control of SFRs (no banking)
 Direct addressing (BSR role)
• The data memory is partitioned into sixteen
banks. When using direct addressing, the BSR
should be configured for the desired bank.
• BSR<3:0> holds the upper 4 bits of the 12-bit
RAM address. The BSR<7:4> bits will always
read ’0’s, and writes will have no effect.
• BSR (address 0xFE) refer page 48 of datasheet
• A MOVLB instruction has been provided in the
• instruction set to assist in selecting banks.
DIRECT ADDRESSING
Indirect Addressing, INDF and FSR Registers

• Indirect addressing is a mode of addressing

data memory, where the data memory
address in the instruction is not fixed.
• An FSR register is used as a pointer to the data
memory location that is to be read or written.
Since this pointer is in RAM, the contents can
be modified by the program.
• This can be useful for data tables in the data
memory and for software stacks.
• Indirect addressing is possible by using one of the INDF
registers.
• Any instruction using the INDF register actually accesses the
register pointed to by the File Select Register, FSR.
• The FSR register contains a 12-bit address as shown in Figure
• The INDFn register is not a physical register. Addressing INDFn
actually addresses the register whose address is contained in
the FSRn register (FSRn is a pointer).
• There are three indirect addressing registers. To address the
entire data memory space (4096 bytes), these registers are 12-
bit wide. To store the 12-bits of addressing information, two 8-
bit registers are required. These indirect addressing registers
are:
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
 Indirect Addressing, INDF and FSR
Registers
• Reading or writing to registers INDF0, INDF1 and
• INDF2 (which are not physically implemented
registers) activates indirect addressing, with the
value in the corresponding FSR register being the
address of the data.
• If an instruction writes a value to INDF0, the value
will be written to the address pointed to by
FSR0H:FSR0L.
• A read from INDF1 reads the data from the
address pointed to by FSR1H:FSR1L. INDFn can be
used in code anywhere an operand can be used.
INDIRECT ADDRESSING
INDIRECT ADDRESSING OPERATION
INDIRECT ADDRESSING OPERATION
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access (no change)
- INDFn
• Auto-decrement FSRn after an indirect access(post-
decrement) - POSTDECn
• Auto-increment FSRn after an indirect access(post-
increment) - POSTINCn
• Auto-increment FSRn before an indirect access(pre-
increment) - PREINCn
• Use the value in the WREG register as an offset to FSRn.
Do not modify the value of the WREG or the FSRn register
after an indirect access (nochange) - PLUSWn
HOW TO CLEAR RAM (BANK1) USING
INDIRECT ADDRESSING