Product Brief

NetSilicon® NS9360
NS9360 NET+ARM Processors
272-Pin BGA, Lead-Free, RoHS Compliant
• 32-bit, 177, 155, 103 MHz NET+ARM
processor
USB Host JTAG Test
44.25, 38.75 or 25.75 MHz Peripheral Bus

ARM
and Debug • 0.13 µm CMOS process
USB Device
ARM926EJ-S • 10/100Base-T Ethernet
177, 155 or 103 MHz Real-Time
1284
8 kB I-Cache Clock • Extensive on-chip peripherals
27-Channel DMA

4 kB D-Cache
32 b-D, 32 b-A

Serial • Comprehensive networking software

Module 10/100

16 GPIO
X4 Ethernet
Distributed DMA MII/RMII
GPIO (50 Pins)

UART MAC
88.5, 77.5 or 51.5 MHz AHB Bus
32 b-D, 32 b-A Memory
SPI
Controller

7 GPIO
Ext.
Peripheral
12C CLK Generation Controller
Vectored Interrupt
LCD Controller Controller

Power Manager
8 x Timers/Counters
or 4 PWM AHB Arbiter

Features/Benefits
> High performance 32-pit processor Overview
with rich set of peripherals
> 177 MHz ARM9 core (ARM926EJ-S) The NetSilicon NS9360 is the third ARM9 processor in our award-winning family
> Harvard architecture with 8 kB/4 kB of NET+ARM 32-bit processors. It is targeted at network-enabling embedded
instruction/data cache electronic equipment that requires a rich set of peripherals. The NS9360 provides
> DSP instruction set extensions
full duplex 10/100Base-T Ethernet functionality with additional processing
performance and bandwidth to handle sophisticated embedded applications.
> Jazelle® Java byte-code accelerator
> Full-duplex 10/100Base-T Ethernet MAC The NS9360 is based on the ARM926EJ-S, ARM’s most powerful ARM9 core,
> 88.5 MHz memory/peripherals controller which contains both DSP and Java byte code instructions. It operates at up to
> AM and PM color and monochrome 177 MHz and contains a broad set of industry standard peripherals, including
LCD controller 10/100Base-T Ethernet, USB, I2C, 1284, serial ports and a highly configurable
> USB 2.0 Full-Speed OHCI host and
LCD controller.
13-EP device
Like all of our processors, the NS9360 is supported by the royalty-fre
> Four multi-function serial ports;
UART or SPI (master or slave)
NET+Works® software development tool suite. The integrated NET+Works
package contains either Green Hills® MULTI® or Microcross GNU X-Tools™,
> I2C port (master or slave)
MAJIC™ debugger, Express Logic’s ThreadX® real-time operating system, a
> Programmable timers/counters/PWM TCP/IP stack, networking applications, software, utilities and numerous
> 73 General Purpose I/O (GPIO) pins networking applications examples. Support and Development kits for Linux and
> Highly configurable power management Microsoft® Windows® CE are also available.
> Supported by the comprehensive and
integrated NET+Works development suite
Please contact us at 1-877-OEM-DIGI or 952-912-3444
for additional information or to discuss your specific
> Complete Windows CE 5.0 Board Support
application requirements.
Package (BSP) available
> Royalty-free Linux 2.6 kernel distribution
available (LxNETES)

www.digi.com

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 Hardware Specifications
32-BIT ARM926EJ-S OPTIMIZED 10/100
RISC PROCESSOR ETHERNET MAC SERIAL PORTS
• 103, 155, 177 MHz • MII or RMII PHY interfaces • 4 serial modules, each
• 5-stage pipeline • Full or half duplex independently configurable to
• Harvard architecture • Station, broadcast, multicast address UART mode, SPI master mode,
filtering or SPI slave mode
• 8 kB I-cache and 4 kB D-cache
• 2 kB Rx FIFO • Bit rates from 75 bps to 1.8
• 32-bit ARM and 16-bit Thumb Mbps: asynchronous x8 mode
instruction sets, can be mixed for • 256 B Tx FIFO with on-chip buffer
performance/code density tradeoffs • Max bit rates for synchronous
descriptor ring (eliminates underruns mode are:
• MMU to support virtual memory and decreases bus traffic) - 1/16 CPU speed for SPI
based OS’s such as Linux, • Separate Tx and Rx DMA channels master
WinCE/Pocket PC, VxWorks, etc. - 1/32 CPU speed for SPI
• Intelligent receive-side buffer size
• DSP instruction extensions: improved selection slave
divide, single cycle multiply • UART provides:
accumulate • Support for full statistics gathering
• Support for external CAM filtering - High-performance hardware
• ARM Jazelle, 1060 CM (Caffeine and software flow control
Marks) Java Accelerator - Odd, even, or no parity
• Embedded ICE-RT debug unit - 5, 6, 7 or 8 bits
• JTAG boundary scan support - 1 or 2 stop bits
• Clock-gated processor for decreased - Receive-side character and
power dissipation buffer gap timers
FLEXIBLE LCD
• Internal or external clock
CONTROLLER support for synchronous mode
• Supports commercially available displays • 4 receive-side data match
up to SVGA detectors
• Active-matrix color TFT displays • 2 dedicated DMA channels per
EXTERNAL SYSTEM • Up to 18 bpp; 256K colors module, 8 total
BUS INTERFACE • Single and dual-panel color • 32 B Tx FIFO and 32 B Rx FIFO
passive-matrix displays per module
• 32-bit data bus, 28-bit external
- Up to 16 bpp 4:4:4 RGB;
address bus
3375 colors
• Glueless interface to SDRAM, SRAM,
• Single and dual-panel monochrome
EEPROM, buffered DIMM, Flash
STN displays
• Up to 256 MB SDRAM, up to 2 GB
DIMM • 1, 2, 4 bpp palletized grayscale I 2C P O R T
• 4 static and 4 dynamic chip selects • Formats image data and generates
timing control signals • I2C v.1.0, configurable to master
• 0-63 wait states per chip select
• Internal programmable palette-LUT and or slave mode
• Self-refresh during system sleep
grayscaler support different color • Bit rates: fast (400 kHz) or normal
• Automatic dynamic bus sizing to techniques (100 kHz) with clock stretching
8-bits, 16-bits, 32-bits
• Programmable panel-clock frequency • 7-bit and 10-bit address modes
• Burst-mode support with automatic
data width adjustment
• 2 external DMA channels for external
peripheral support

USB PORTS 1284 PARALLEL

• USB v.2.0 Full Speed (12 Mbps) and PERIPHERAL-TO-HOST PORT
low speed (1.5 Mbps) • All standard modes:
SYSTEM BOOT • OHCI host and 11 end points device - ECP, Byte, Nibble, Compatibility
• Single PHY can be used with either • RLE (Run Length Encoding) decoding
• High-speed boot from 8-bit, 16-bit,
host or device of compressed data in ECP mode
or 32-bit ROM or Flash
• Interface to external PHY for • Operating clock from 100 kHz to
• Hardware-supported low cost boot
simultaneous host and device operation 2 MHz
from serial EEPROM through SPI
port (patent pending) • USB host is a bus master • 4 dedicated DMA channels
• Each USB device endpoint is supported - 2 for data and 2 for control
by a dedicated DMA channel, 13 total • Microsoft Plug-and-Play, no Windows
• 20 B Rx FIFO and 20 B Tx FIFO driver needed

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 Hardware Specifications

SYSTEM BUS DMA SYSTEM TIMERS CLOCK GENERATOR

• Every system bus peripheral is a bus • Watchdog timer • Low cost external crystal
master with dedicated DMA engine • System bus monitor timer • Internal Phase-Locked Loop (PLL)
• Deterministic bus bandwidth • Peripheral bus monitor timer • Software programmable PLL parameters
allocation (patent pending) • Optional external oscillator
• Separate oscillator for USB

GENERAL PURPOSE I/O

EXTERNAL
PERIPHERAL DMA • 73 programmable GPIO pins OPERATING VOLTAGE
(muxed with other functions)
• 2-channel DMA engine - Includes 7 high-current (8 mA) • Core: 1.5V ± 0.1V
• Supports memory-to-memory GPIO pins
• I/O ring: 3.3V ± 10%
transfers • Software-readable power-up status
registers for customer-defined
bootstrapping

OPERATING
FREQUENCY
POWER MANAGEMENT EXTERNAL • 103 MHz: 0° C to 70° C
• Power save during normal operation INTERRUPTS • 155 MHz: -40° C to 85° C
• Disables unused modules • 177 MHz: 0° C to 70° C
• 4 external programmable interrupts
• Power save during sleep mode - Rising- or falling-edge sensitive
- Sets SDRAM to self-refresh mode - Low- or high-level sensitive
- Individually disables every module
except selected wakeup modules
- Wakeup on valid packets or
characters
POWER
• Patent pending technology CONSUMPTION
REAL TIME CLOCK • 177 MHz: 0.64 W
• 155 MHz: 0.59 W
• Time of day clock • 103 MHz: 0.52 W
• Alarm
VECTORED INTERRUPT • 100 year calendar
• Programmable periodic interrupt
CONTROLLER • 10 ms resolution
• Holds pointers to all interrupt service • Dedicated time domain in the
routines for rapid service system PLL PACKAGE
• Services all peripherals - RTC-only mode available
• Initial time from network through • 272-pin BGA including 16
• Hardware interrupt prioritization thermal balls
SNTP routine
- No battery backup • 1.27 mm ball pitch
• Additional benefits • 27 mm x 27 mm
- Frees CPU from math calculations • Lead-free, RoHS compliant
GENERAL PURPOSE - Decreased response time for
queries
TIMERS/CONTROLLERS/PWM
• 8 independent 16- or 32-bit
programmable timers, counters, or 4
PWM functions
• Each has an I/O pin
MICROSOFT® WINDOWS® LINUX SUPPORT
• Mode selectable into:
CE SUPPORT (LXNETES)
- Internal timer mode®
• Complete Windows CE 5.0 Board • Based on Linux 2.6.x kernel
- External gated timer mode
Support Package (BSP) • Complete GNU ToolSuite of compilers
- External event counter
- PWM • Custom-developed drivers to support and debuggers
peripherals, modules and • Bootloader for managing and
• Timers/counters can be concatenated
Development Kits installing software updates
• Minute-range events measurable
• Exclusive software to provide
• Source clock selectable debugging channel via Ethernet
• Internal clock or external pulse event connection
• Individually enabled/disabled

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 NET+Works Software Solutions
®

NETWORKING
NET+Works Integrated PROTOCOLS UTILITIES
Development Package
NET+ARM network-attached processors • TCP/IP stack • HTML compilation
are the core of the NET+Works family • TCP and UDP Sockets API • MIB compilation
• ICMP • Download of Flash images
of solutions that add intelligence and • IGMP • Bootloader
connectivity to electronic devices. We offer • PPP for serial communications • Code builds
extensive networking software to support • Address Configuration Executive (ACE): • Integrated flash file system
industrial automation, building automation, - ARP • Code Profiler
point-of-sale, office automation and other - RARP • Boundary Scan Description
enterprise applications. - Ping ARP Language (BSDL)
- AutoIP
- DHCP client
- BootP
DEVELOPMENT TOOLS • Fast IP TECHNICAL SUPPORT
• Fast sockets
• One year of software
• Green Hills® MULTI® IDE or • SSL, TLS maintenance and technical
Microcross GNU X-Tools™ support

NETWORKING SERVICES
RTOS • FTP server/client; TFTP
• ThreadX® picokernel • LDAPv3 agent, for access to DEVELOPMENT BOARD
network information services
• HTTP APIs for serving basic and • NS9360 development board
advanced web pages and JTAG debugger
• HTTPS for security
BOARD SUPPORT
• Email (POP3 and SMTP)
PACKAGE • SNMP v1/MIBII for remote
• 10/100Base-T Ethernet management
• UART • SNTP
• SPI • DNS
• HDLC • Telnet
• I2C • Multi-homing
• Flash
• USB host & device
• LCD
• 1284 peripheral
• Power save

MODEL......................PART NUMBERS
Model Worldwide
103 MHz, 0° C to 70° C operation NS9360B-0-C103
155 MHz, -40° C to 85° C operation NS9360B-0-I155
177 MHz, 0° C to 70° C operation NS9360B-0-C177

DIGI SERVICE AND SUPPORT

You can purchase with confidence knowing that Digi is here to support you with expert technical support and a strong one-year warranty. www.digi.com/support

Digi Internationa l Digi Internationa l Digi Internationa l Digi Internationa l www.digi.com

11001 Bren Road E. France KK (HK) Limited
Minnetonka, MN 55343 31 rue des Poissonniers NES Building South 8F Suite 1703-05, 17/F.,
U.S.A. 92200 Neuilly sur Seine 22-14 Sakuragaoka-cho, K Wah Centre email:
PH: 877-912-3444 PH: +33-1-55-61-98-98 Shibuya-ku 191 Java Road [email protected]
952-912-3444 FX: +33-1-55-61-98-99 Tokyo 150-0031, Japan North Point, Hong Kong
FX: 952-912-4952 www.digi.fr PH: +81-3-5428-0261 PH: +852-2833-1008
www.digi.com FX: +81-3-5428-0262 FX: +852-2572-9989
www.digi-intl.co.jp www.digi.cn
© 2004-2006 Digi International Inc. 91001266
Digi, Digi International, the Digi logo, the Making Device Networking Easy logo, NetSilicon, NET+ and NET+Works are trademarks or registered C2/1106
trademarks of Digi International, Inc. in the United States and other countries worldwide. ARM and NET+ARM are trademarks or registered trademarks
of ARM Limited. All other trademarks are property of their respective owners.

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