Proceedings of IETE 37th MTS:ICTIRD-2006, Kolkata, India P31-1

Incremental Encoder Reader Circuit with Error

Detection and Correction using Microcontroller
1
Arindam Sanyal, 2Snehasish Das, 3Sonai Ray, 4P.Venkateswaran, 5S.K.Sanyal and 6R.Nandi

Abstract--Design of incremental encoder interface involves

designing a circuit to decode the positional and directional
data embedded in the output signals of the encoder , as well as
designing a counter circuit to count the number of pulses.
This can be done either by using a custom IC or 5-10 discrete
ICs. Four monostable circuits would be needed to implement
the direction sensing unit. However, with the increase in
number of components, system reliability is reduced. Also, channel A
systems are easily susceptible for interference by noise. This
paper presents a way of implementing the above functions
using software only. In addition, the paper provides a
mechanism for efficient error correction, thus making it
suitable for servomotor control designs, even under noisy
conditions.
channel B

Fig. 1. Typical encoder waveform showing channel B being 900 offset

Index Terms--biphase , control system , encoder from channel A
reader circuit , error correction , forward pulse train ,
microcontroller . An incremental biphase encoder is the most commonly
used device in computer-controlled feedback system. The
microcomputer actuates several final control elements
based on the information obtained from the encoder. In
I. INTRODUCTION addition to providing positional and directional
information[1], the encoder interface circuit must also
Whenever mechanical rotary motions have to be perform some special functions to maintain proper
monitored, an encoder is the most important interface operations, such as missing pulse correction, error
between the mechanics and the control unit. Encoders correction, resetting the position counter based on control
transform rotary movement into a sequence of electrical signal from the microcomputer, etc. It requires 5-10
pulses. As a single channel can detect only incremental discrete ICs to implement all the above functions. Also,
rotation, a second signal, phase shifted by 90 degrees is also certain types of combinational logic are error prone due to
generated. This second signal, along with the first signal, gate delays or threshold offsets and multivibrator
enables the direction of rotation to be determined. The two imprecisions. This paper tries to do away with these errors
signals from channel A and B are shown in Fig. 1 as well as reducing drastically the amount of hardware
___________________________ needed. The scheme is explained in section II and the
implementation details are given in section III.
1
Arindam Sanyal is a B. E. Tel. E student of the Department of
Electronics & Tele-Communication , Jadavpur University , Kol-32.
( email : [email protected] ) (Corressponding author).
2
Snehasish Das is a B. E. Tel. E student of the Department of Electronics
& Tele-Communication , Jadavpur University, Kol-32.
( email : [email protected] ).
3
Sonai Ray is a M. S student of Computer Science and Engineering in
IIT Kharagpur ( email : [email protected]).
4
P.Venkateswaran is with the the Department of Electronics & Tele-
Communication , Jadavpur University , Kol-32 ( email : [email protected]).
II. PROPOSED SCHEME
5
S.K.Sanyal is with the Department of Electronics & Tele- A. Edge Detection algorithm
Communication , Jadavpur University, Kol-32.
( email : [email protected])
The change of states of signals A and B (Fig. 1) can
E
R.Nandi is with the Department of Electronics & Tele-Communication , be represented in the form of the following state diagram
Jadavpur University , Kol-32. ( email : [email protected]). (Fig. 2).
Proceedings of IETE 37th MTS:ICTIRD-2006, Kolkata, India P31-2

determining whether the state transition is in the forward or

reverse direction, and then generating the proper signal.

00

10 01
The direction of the current state transition is determined
on the basis of two previous transitions. If the transition is
an FPT and an error has occurred, then the present state is
given by An = Bn − 1 and Bn − 1 = An − 1 ⊕ 1 and , if the
11 transition is an RPT, then the present state is given by
An = Bn − 1 ⊕ 1 and Bn = An − 1 . Thus, any error in the
signals A and B can be readily corrected. However, the
noise interference may be such that it gives rise to a valid
Fig. 2 State transition diagram of a biphase incremental encoder.
transition. The algorithm can be used to give the correct
Dashed lines indicate erroneous transition. number of transitions even in such a case. An error will
occur if due to the noise, a ‘1’ appears as a ‘0’ and vice
The above state diagram has been formed taking the value versa. If a spike occurs in any channel, it can be
of channel A as the msb ( most significant bit ) and the considered as an FPT and an RPT in succession. The
value of channel B as the lsb ( least significant bit ). The program uses a counter to store the number of transitions.
state transition from 00→01→11 →10 is denoted by FPT( The counter is incremented by 1 for every forward
forward pulse train )[2] and the state transition from transition and decremented by 1 for every reverse
00→10→11→01 is denoted by RPT ( reverse pulse train ). transition. Thus, there will be no change in the value of
The erroneous state transitions are shown by dotted lines. the counter due to the spike. If the spike triggers an
From the state diagram it can be seen that for no state erroneous transition, then the program will automatically
change, An ⊕ An −1 = 0 and Bn ⊕ Bn −1 = 0 where An correct the error and generate the correct state. This has
been explained with simulation diagrams in the next
and Bn denote the nth states of A and B. For an FPT, section.
An ⊕ Bn − 1 = 0 and, Bn ⊕ An − 1 = 1 and , for an RPT ,
An ⊕ Bn −1 = 1 and Bn ⊕ An −1 = 0 , provided a valid
transition has occurred. The program detects all the four
edges (Fig. 1) in a single cycle. So any missing edge must
be due to an erroneous transition. From the state
diagram(Fig. 2), it is seen that if any erroneous transition
occurs, then An ⊕ An − 1 = 1 and Bn ⊕ Bn −1 = 1 . This
algorithm forms the basis of decoding the positional and
directional information from the output signals of the III. IMPLEMENTATION
biphase encoder. However, there may be errors due to
excessive noise. There are two ways to handle this error: We have used Intel 8031 Microcontroller[3,4] to
(i) the program increments an error counter at every implement the reader circuit. We have also used UMPS
instance of an error and if the error counter exceeds a given demo version 1.75C to simulate the encoder reader circuit.
limit, it sends a proper signal to the main system , (ii) We have used DS80C320 microcontroller to simulate the
otherwise, the program automatically corrects the error. reader circuit. In both the hardware implementation as well
The error handling mechanism is explained in the next as the simulator implementation, channel A was connected
section. to port pin P1.1 and channel B was connected to port pin
P1.0. The interface output was seen at port pin P1.2. The
output shows a transition for every edge detected. The
number of valid transitions are stored in the register R0. Its
value is shown in the snapshots of the two simulation
B. Error Handling algorithm diagrams(Fig. 3 and Fig. 4) given below. In Fig. 3
below, we had taken two error free inputs as signals A and
The error handling algorithm follows readily from the B. We had simulated 8 cycles of signals A and B and the
previous algorithm. The error correction is done by first value of position counter stored in register R0 correctly
gives the number of transitions as 32. In Fig. 4 , we had
Proceedings of IETE 37th MTS:ICTIRD-2006, Kolkata, India P31-3

simulated in the presence of noise, thus leading to distorted

signals A and B. In this case also, the value of program
counter is 32 as it should have been if the signals were
error free.

Fig. 3 Snapshot of the simulated waveform in the absence of noise

Fig. 4 Snapshot of the simulated waveform in the presence of noise

Proceedings of IETE 37th MTS:ICTIRD-2006, Kolkata, India P31-4

IV. CONCLUSION

An efficient error correction mechanism for biphase

encoder interface circuit has been described. The
implementation details and the simulation results have also
been given. Using this implementation, the system
reliability can be increased thus making it a favourable tool
for automatic control system.

V. REFERENCES

[1] E. S. Tez, “Interfacing bi-phase incremental encoders”, IEEE Trans.

Ind. Electron, Vol. IE – 33, No. 3, Aug. 1986, pp. 337-339
[2] Bernard Hebert, Michel Brule and Louis- A. Dessaint , “A high
efficiency interface for a biphase incremental encoder with error
detection” , IEEE Trans. Ind. Electron, Vol. 40, No. 1, Feb.
1998, pp. 155.
[3] Myke Predko Programming and Customizing the 8051
Microcontroller, Tata McGrawHill Edition, New Delhi, 1999.
[4] Advanced Electronic Systems “ALS SDA – 8031 Microcontroller Kit
User’s Manual”, , Bangalore, India.
.