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compiler design (APJ Abdul Kalam Technological University)

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MODULE 1

1. Explain in detail the various phases of the compiler with a neat diagram.
Illustrate the output of each phase for the input,
sum := a + b * 30
where a and b are float variables. (10)

2. Write notes on compiler construction tools. (8)

3. Differentiate tokens, patterns and lexemes with the help of an example. (5)

4. Explain input buffering (8)

MODULE 2

1. Problem from left factoring and left recursion

Eg: What is left factoring? Left factor the following grammar, C (3)
E→E+T | T
T → float | float ∗ T | (E)
2. Problem from th topic LL(1)
Eg : Prove that the following grammar is not LL(1)
S → iEtSS’ | a
S’ → eS | ɛ
E→b
3. Problem from the topic ambiguity
Eg: Show that the given grammar is ambiguous or not.
E→ E+E | E−E
E → E ∗ E | E/E
E→ E ^ E
E → (E) | id
Also eliminate ambiguity from the above grammar.
(Precedence order: id, ( ), ^ , * and /, + and - )
4. Problem from predictive parsing(non recursive predictive parsing)
Eg: Construct predictive parsing table for the following grammar:
E→ E + T | T
T→ T * F |F
F→ ~ F | (E) | id
5. Design a recursive descent parser for the grammar:
S→cAd, A→ab/ b

MODULE 3
1. Different parsing conflicts in the SLR parsing table?
A shift-reduce conflict occurs in a state that requests both a shift action and a reduce action.A
reduce-reduce conflict occurs in a state that requests two or more different reduce actions.
Write Any example also

2. Problem from SLR parsing table construction

Eg: S → L = R

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S→R
L→*R
L → id
R→ L
Also identify the shift reduce conflict here.

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EXAMPLE 2– Construct LR parsing table for the given context-free grammar

S–>AA
A–>aA|b
Solution:
STEP1 – Find augmented grammar
The augmented grammar of the given grammar is:-
S’–>.S [0th production]
S–>.AA [1st production]

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A–>.aA [2nd production]

A–>.b [3rd production]
STEP2 – Find LR(0) collection of items
Below is the figure showing the LR(0) collection of items. We will understand everything one by
one.

The terminals of this grammar are {a,b}.

The non-terminals of this grammar are {S,A}
RULE –
If any non-terminal has ‘ . ‘ preceding it, we have to write all its production and add ‘ . ‘ preceding
each of its production.
FOLLOW(S)=$
FOLLOW(A)=a,b,$

3. Problem from LR/ CLR parsing table construction. Study the method of parsing also
Eg: Derive LR (1) parsing table for following grammar
S → Aa | bAc | Bc | bBa
A→d
B→d
Step1 − Construct Augment Grammar Step 2: LR(1) items

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(0) S′ → S
(1) S → A a
(2) S → b A c
(3) S → B c
(4) S → b B a
(5) A → d
(6) B → d

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Step3: Parsing table

4. Problem from LALR parsing table construction

Eg: S --> CC
C --> cC
C --> d
(Refer ktu notes)

5. Handle and handle pruning

Handle is a substring that matches with the right side of the production and if the substring matches
with the right side of the production, it is reduced with the non-terminal on the left side of the
production

EXAMPLE
Consider the grammar
E  E+E
E  E*E
E  (E)
E id
And the input string is id1 + id2 * id3
The rightmost derivation is:
EE+E
E+E*E
 E + E * id3
 E + id2 * id3
 Id1 + id2 * id3

In the above derivation, the underlined substrings are called handles.

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HANDLE PRUNING
The process of obtaining rightmost derivation in reverse order is called “handle pruning”.
(i.e.) if w is a sentence or string of the grammar at hand, then w = n where n is the nth right
sentinel form of some rightmost derivation.

6.Actions of shift reduce parser

There are actually four possible actions a shift-reduce parser can make:
 Shift
 Reduce
 Accept
 Error
1. Shift: The next input symbol is shifted onto the top of the stack.
2. Reduce: The parser knows the right end of the string to be reduced must be at the
top of the stack. It must then locate the left end of the string within the stack and
decide with what nonterminal to replace the string.
3. Accept: Announce successful completion of parsing.
4. Error: Discover a syntax error has occurred and calls an error recovery routine.

MODULE 4
1.Write the SDD for a simple type declaration and draw the annotated parse tree for the
declaration int a,c

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2.Write the SDD for a desk calculator and draw the annotated parse tree for the expression:
4*5 + 6
Annotated parse tree
 The parse tree containing the values of attributes at each node for given input string is
called annotated or decorated parse tree.

3.Define the
following terms and give suitable example for each.
i) Three-address code ii) Triples iii) Quadruples
Quadruple – It is a structure which consists of 4 fields namely op, arg1, arg2 and result. op denotes
the operator and arg1 and arg2 denotes the two operands and result is used to store the result of the
expression.
Triples – This representation doesn‟t make use of extra temporary variable to represent a single

operation instead when a reference to another triple‟s value is needed, a pointer to that triple is

used. So, it consist of only three fields namely op, arg1 and arg2.

Indirect Triples – This representation makes use of pointer to the listing of all references to

computations which is made separately and stored.

Eg: a=(b*-c)+(b*-c)
t1 = uminus c
t2 = b * t1
t3 = uminus c
t4 = b * t3
t5 = t2 + t4

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a = t5

4.Explain static allocation and heap allocation strategies.

HEAP
ALLOCATION

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5. What are L-attributed definitions and S-attributed definitions in a syntax directed

translation scheme?
• S-attributed definition
 S stands for synthesized
 If an SDT uses only synthesized attributes, it is called as S-attributed SDT.
EXAMPLE:
A-->BC
{ A.a=B.a,C.a}
 S-attributed SDTs are evaluated in bottom-up parsing, as the values of the parent nodes depend
upon the values of the child nodes.
 Semantic actions are placed in rightmost place of RHS.
A-> BC{ }.
 Note: (Also write SDD for desk calculator as example).
• L –attributed definition
L stands for one parse from left to right
If an SDT uses both synthesized attributes and inherited attributes with a restriction that inherited
attribute can inherit values from parent and left siblings only, it is called as L-attributed SDT.
EXAMPLE:
A-->BCD {B.a=A.a, C.a=B.a}
C.a=D.a is not possible
Attributes in L-attributed SDTs are evaluated by depth-first and left-to-right parsing manner.
Semantic actions are placed anywhere in RHS.
A--> {}BC
B{ }C
BC{ }
Note: Also write SDD for declaration stmt
6. synthesized and inherited attributes
• Synthesized Attributes: These are those attributes which get their values from their children
nodes i.e. value of synthesized attribute at node is computed from the values of attributes at
children nodes in parse tree.
To illustrate, assume the following production:
EXAMPLE : S -> ABC
S.a= A.a,B.a,C.a
If S is taking values from its child nodes (A,B,C), then it is said to be a synthesized attribute
• Inherited Attributes: These are the attributes which inherit their values from their parent or
sibling nodes. i.e. value of inherited attributes are computed by value of parent or sibling nodes.
EXAMPLE:
A --> BCD { C.in = A.in, C.type = B.type }
B can get values from A, C and D. C can take values from A, B, and D. Likewise, D can take
values from A, B, and C.
7. Construct the syntax tree and then draw the DAG for the statement:(b*-c)+(b*-c)

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MODULE 5
1.llustrate the role of register descriptor and address descriptor in code generation phase.
Register and Address Descriptors:A register descriptor is used to keep track of what is currently
in each registers. Theregister descriptors show that initially all the registers are empty.
Write an example
An address descriptor stores the location where the current value of the name can befound at run
time.
Write an example

2.Explain the design issues of a code generator.

The following issues arise during the code generation phase :
1. Input to code generator
2. Target program
3. Memory management
4. Instruction selection
5. Register allocation
6. Evaluation order
1. Input to code generator:
The input to the code generation consists of the intermediate representation of the sourceprogram
produced by front end , together with information in the symbol table todetermine run-time
addresses of the data objects denoted by the names in theintermediate representation
Intermediate representation can be :
a. Linear representation such as postfix notation
b. Three address representation such as quadruples
c. Virtual machine representation such as stack machine code
d.Graphical representations such as syntax trees and dags.
Prior to code generation, the front end must be scanned, parsed and translated intointermediate
representation along with necessary type checking. Therefore, input to codegeneration is assumed to
be error-free.
2. Target program:
The output of the code generator is the target program. The output may be :
a. Absolute machine language- It can be placed in a fixed memory location and can be executed
immediately.
b. Relocatable machine language- It allows subprograms to be compiled separately.
c. Assembly language- Code generation is made easier.
3. Memory management:
Names in the source program are mapped to addresses of data objects in run-timememory by the
front end and code generator.It makes use of symbol table, that is, a name in a three-address
statement refers to asymbol-table entry for the name.Labels in three-address statements have to
be converted to addresses of instructions.For example,

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j : goto i generates jump instruction as follows :

 if i < j, a backward jump instruction with target address equal to location ofcode for quadruple i
is generated.
 if i > j, the jump is forward. We must store on a list for quadruple i thelocation of the first
machine instruction generated for quadruple j. When i isprocessed, the machine locations for all
instructions that forward jumps to iare filled.
4. Instruction selection:
The instructions of target machine should be complete and uniform.Instruction speeds and
machine idioms are important factors when efficiency of targetprogram is considered.The quality
of the generated code is determined by its speed and size.The former statement can be translated
into the latter statement a
5. Register allocationInstructions involving register operands are shorter and faster than those
involvingoperands in memory.
The use of registers is subdivided into two subproblems :
Register allocation – the set of variables that will reside in registers at a point inthe program is
selected.
Register assignment – the specific register that a variable will reside in ispicked.
Certain machine requires even-odd register pairs for some operands and results.For example ,
consider the division instruction of the form :
Dx, y
where, x – dividend even register in even/odd register pair
y – divisor
even register holds the remainder
odd register holds the quotient
6. Evaluation order
The order in which the computations are performed can affect the efficiency of thetarget code.
Some computation orders require fewer registers to hold intermediateresults than others
3.Explain different code optimization techniques

(Refer print 1)
4.Write the code generation algorithm and getreg function. Using this algorithm generate
code sequence for the expression x = (a –b) + (a + c) + (a + c)

The algorithm takes a sequence of three-address statements as input. For each three address
statement of the form x := y op z perform the various actions. These are as follows:

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Code generator uses getReg function to determine the status of available registers
and the location of name values. getReg works as follows:
 If variable Y is already in register R, it uses that register.
 Else if some register R is available, it uses that register.
 Else if both the above options are not possible, it chooses a register that
requires minimal no of load and store. It takes register which is already occupied, move its contents
into some memory using the instruction MOV R, M. and then uses the register R.

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