code
code
module Image
#(
parameter WIDTH = 768,
HEIGHT = 512,
INFILE = ".hex",
START_UP_DELAY = 100,
HSYNC_DELAY = 160
)
(
input HCLK,
input HRESETn,
output reg VSYNC,
output reg HSYNC,
output reg [7:0] DATA_R0, // 8-bit grayscale data
output reg ctrl_done
);
// FSM
reg [1:0] cstate, nstate;
localparam ST_IDLE = 2'b00, ST_VSYNC = 2'b01, ST_HSYNC = 2'b10, ST_DATA = 2'b11;
reg start;
reg [18:0] pixel_index;
// Reset xử lý
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
start <= 0;
cstate <= ST_IDLE;
pixel_index <= 0;
end
else begin
cstate <= nstate;
if (cstate == ST_DATA && pixel_index < PIXEL_COUNT - 1)
pixel_index <= pixel_index + 1;
end
end
endmodule
#Ghi
module Image_write
#(parameter WIDTH = 768, // Image
width
HEIGHT = 512,
// Image height
INFILE = "Out.bmp", // Output
image
BMP_HEADER_NUM = 54 //
Header for bmp image
)
(
input HCLK,
// Clock
input HRESETn,
// Reset active low
input hsync,
// Hsync pulse
input [7:0] DATA_WRITE_R0, // Red 8-bit data
(odd)
input [7:0] DATA_WRITE_G0, // Green 8-bit
data (odd)
input [7:0] DATA_WRITE_B0, // Blue 8-bit data
(odd)
input [7:0] DATA_WRITE_R1, // Red 8-bit data
(even)
input [7:0] DATA_WRITE_G1, // Green 8-bit
data (even)
input [7:0] DATA_WRITE_B1, // Blue 8-bit data
(even)
output reg Write_Done
);
integer BMP_header [0 : BMP_HEADER_NUM - 1]; // BMP header
reg [7:0] out_BMP [0 : WIDTH*HEIGHT*3 - 1]; // Temporary memory for image
reg [18:0] data_count; // Counting
data
wire done;
// done flag
// counting variables
integer i;
integer k, l, m;
integer fd;