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ALU

The document contains Verilog code for various digital components including half adder (HA), full adder (FA), an 8-bit carry lookahead adder (cla8bit), a multiplier, a divider, and an arithmetic logic unit (ALU1). Each module is defined with inputs and outputs, implementing basic arithmetic operations and logic functions. The ALU1 module integrates these components to perform multiple operations based on a selection input.

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11 views3 pages

ALU

The document contains Verilog code for various digital components including half adder (HA), full adder (FA), an 8-bit carry lookahead adder (cla8bit), a multiplier, a divider, and an arithmetic logic unit (ALU1). Each module is defined with inputs and outputs, implementing basic arithmetic operations and logic functions. The ALU1 module integrates these components to perform multiple operations based on a selection input.

Uploaded by

asmitshibani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as TXT, PDF, TXT or read online on Scribd
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module HA(

input a, b,
output d, cout
);
assign d = (a ^ b);
assign cout = (a & b);
endmodule

module FA(
input a, b, c,
output d, cout
);
assign d = (a ^ b ^ c);
assign cout = (a & b) | (b & c) | (c & a);
endmodule

module cla8bit(
input [7:0] a, b,
input cin,
output [7:0] sum,
output cout
);
wire [7:0] g, p;
wire [8:0] c;

assign g = a & b;
assign p = a | b;

assign c[0] = cin;


assign c[1] = g[0] | (p[0] & c[0]);
assign c[2] = g[1] | (p[1] & c[1]);
assign c[3] = g[2] | (p[2] & c[2]);
assign c[4] = g[3] | (p[3] & c[3]);
assign c[5] = g[4] | (p[4] & c[4]);
assign c[6] = g[5] | (p[5] & c[5]);
assign c[7] = g[6] | (p[6] & c[6]);
assign c[8] = g[7] | (p[7] & c[7]);

assign sum = p ^ c[7:0];


assign cout = c[8];
endmodule

module multiplier(
input [7:0] a,
input [7:0] b,
output reg [15:0] p
);
reg [15:0] partialsum [7:0];
integer i, j;

always @(*) begin


partialsum[0] = 16'b0;
partialsum[1] = 16'b0;
partialsum[2] = 16'b0;
partialsum[3] = 16'b0;
partialsum[4] = 16'b0;
partialsum[5] = 16'b0;
partialsum[6] = 16'b0;
partialsum[7] = 16'b0;

for (i = 0; i < 8; i = i + 1) begin


for (j = 0; j < 8; j = j + 1) begin
partialsum[i][i + j] = a[i] & b[j];
end
end

p = partialsum[0] + (partialsum[1] << 1) + (partialsum[2] << 2) +


(partialsum[3] << 3) + (partialsum[4] << 4) +
(partialsum[5] << 5) + (partialsum[6] << 6) +
(partialsum[7] << 7);
end
endmodule

module divider (
input [7:0] A, B,
output reg [7:0] quotient, remainder
);
always @(*) begin
if (B != 0) begin
quotient = A / B;
remainder = A % B;
end else begin
quotient = 8'd0;
remainder = 8'd0;
end
end
endmodule

module ALU1(
input [7:0] A, B,
input [3:0] ALU_Sel,
output [7:0] ALU_Out,
output CarryOut
);
reg [7:0] ALU_Result;
wire [8:0] tmp;
wire [7:0] quotient, remainder;
wire [15:0] product;
wire [7:0] sum, carry_out;
wire sum_carry_out;

assign ALU_Out = ALU_Result;


assign tmp = {1'b0, A} + {1'b0, B};
assign CarryOut = tmp[8];

divider div(.A(A), .B(B), .quotient(quotient), .remainder(remainder));


multiplier mul(.a(A), .b(B), .p(product));
cla8bit cla(.a(A), .b(B), .cin(0), .sum(sum), .cout(sum_carry_out));

always @(*) begin


case(ALU_Sel)
4'b0000: ALU_Result = sum;
4'b0001: ALU_Result = A - B;
4'b0010: ALU_Result = product[7:0];
4'b0011: ALU_Result = quotient;
4'b0100: ALU_Result = A << 1;
4'b0101: ALU_Result = A >> 1;
4'b0110: ALU_Result = {A[6:0], A[7]};
4'b0111: ALU_Result = {A[0], A[7:1]};
4'b1000: ALU_Result = A & B;
4'b1001: ALU_Result = A | B;
4'b1010: ALU_Result = A ^ B;
4'b1011: ALU_Result = ~(A | B);
4'b1100: ALU_Result = ~(A & B);
4'b1101: ALU_Result = ~(A ^ B);
4'b1110: ALU_Result = (A > B) ? 8'd1 : 8'd0;
4'b1111: ALU_Result = (A == B) ? 8'd1 : 8'd0;
default: ALU_Result = sum;
endcase
end
endmodule

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