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Design and Analysis of Power and Variability Aware Digital Summing Circuit

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 ACEEE Int. J. on Communication, Vol. 02, No. 02, July 2011

Design and Analysis of Power and Variability Aware

Digital Summing Circuit
Aminul Islam1, Mohd. Hasan2
1
Dept. of Electronics and Communication Engineering
Birla Institute of Technology (deemed university)
Mesra, Ranchi, Jharkhand, India, Email: [email protected]
2
Department of Electronics Engineering, Aligarh Muslim University
Aligarh, Uttar Pradesh, India, e-mail: [email protected]

Abstract— Due to aggressive scaling and process imperfection variations at 22 nm technology node. It also proposes CNFET
in sub-45 nm technology node Vt (threshold voltage) shift is - based 1-bit digital summing circuit (hereafter called TG(CNT))
more pronounced causing large variations in circuit response. for the most robust CMOS adder topology namely TG-based
Therefore, this paper presents the analyses of various popular full adder cell (hereafter called TG(MOS)). It demonstrates
1-bit digital summing circuits in light of PVT (process, voltage
that the TG(CNT) outperforms TG(MOS) not only in terms of
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
EDP but also in terms of robustness. The remainder of this
parameters and ±10% VDD (supply voltage) variation by applying paper is organized as follows. Impact of RDF (random dopant
Gaussian distribution and Monte Carlo analysis at 22 nm fluctuation) is briefly discussed in Section II. Various
technology node on HSPICE environment. Design guidelines topologies of 1-bit digital summing circuits are briefly analysed
are derived to select the most suitable topology for the design in Section III. Section IV presents brief introduction of CNFET
features required. Transmission Gate (TG)-based digital structure, which is used for the proposed design. Simulation
summing circuit is found to be the most robust against PVT results and comparisons between TG(MOS) and TG(CNT)
variations. Hence, a TG-based digital summing circuit is
are explained in Section V. Section VI concludes this article.
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP II. IMPACT OF RANDOM DOPANT FLUCTUATION
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
Due to aggressive device scaling, there are several design
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
challenges for nanoscaled circuit design. Intrinsic parameter
fluctuations like random dopant fluctuation (RDF), line edge
Index Terms—Carbon nanotube field effect transistor roughness (LER) and variation in oxide thickness fluctuate
(CNFET), transmission gate (TG), random dopant fluctuation threshold voltage (Vt). The intra-die Vt variation due to RDF
(RDF), line edge roughness (LER), energy delay product (EDP). results in deviation of design goal. The standard deviation
of the V t fluctuation due to RDF depends on the
I. INTRODUCTION manufacturing process, doping profile and the transistor
sizing and is given by [4]
As CMOS reaching the scaling limits, the need for
alternative technologies are necessary. Nanotechnology-
based fabrication is expected to offer the extra density and
potential performance to take electronic circuits the next step.
Several nanoscale electronic devices are demonstrated in the where Wdm is the maximum gate depletion width, εox is oxide
recent past by researchers, some of the most promising being relative permittivity, t ox is the oxide thickness, q is the
carbon nanotube based field effect transistor (CNFET). The electronic charge, NSUB is the substrate doping concentration,
digital summing circuit is one of the most important and critical L (W) is the channel length (width). Variation in Vt due to
building block of any Digital System. Many computation RDF is 30 mV (15 mV) in subthreshold (linear) region for a
intensive applications such as multimedia processing and sub-100 nm device with W = 50 nm, L = 100 nm, tox = 30 Å and
digital communication can now be realized in hardware to NSUB = 8.6×1017 cm -3 [5]. Propagation delay (t p), power
either speed up the operation or reduce the power dissipation (P) and EDP (energy delay product) are important
consumption. The essence of the digital computing lies in design metrics of digital circuit. The distributions of these
the full adder design. Hence, the optimization of the full adder metrics are even more problematic than their absolute values
cell in terms of speed and power dissipation is not only because meeting the design specification with variations in
important but also its robustness against PVT (process, them is difficult for a designer. The spread in these design
voltage and temperature) variations is essential. Some metrics are estimated based on Central Limit Theorem [6]. As
comparison among full adder circuits are found in the in the per the Central Limit Theorem, the distribution of a random
literature [1]–[3]. None of these previous works was targeted variable (say, Y) which is the summation of a large number of
for variability analysis. This paper investigates, for the first independent random variables (say, X1, ..., Xn) can be assumed
time to the best of our knowledge, various topologies of to be Normal with mean (µ) and the standard deviation (σ)
(including recently proposed) 1-bit full adder cell against PVT given by
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If all the variables are identically distributed (i.e. all with equal
mean µX and standard deviation σX) we further obtain

From (3), it is observed that, the spread (standard deviation

(σ)/mean(µ)) of the variable Y is less than the spread in the
variable X and the spread of Y reduces as more number of
variables is added together. Monte Carlo simulations are
carried out to investigate and measure the impact of PVT
Figure 2. Mirror full adder
variations on the tp, P and EDP in the sections to come.

III. ANALYSIS OF 1-BIT DIGITAL SUMMING CIRCUITS

This section presents analysis of the most popular
topologies of 1-bit digital summing circuits including recently
proposed circuits. The circuit diagram of static CMOS 1-bit
full adder cell is shown in Fig. 1 [7]. The circuit is described
by the following Boolean equations [8]

The main drawback of static CMOS circuits is the existence

of the PMOS block, which is slow because of the low mobility
of its holes (therefore, the PMOS devices are upsized (2-3×)
to attain the desired performance. The input capacitance of a
Figure 3. TG(MOS) version of 1-bit full adder
static CMOS gate is large because each input is connected
to the gate of at least a PMOS and an NMOS device. Another
static CMOS full adder analyzed is Mirror full adder shown in
Fig. 2 [7], [8]. This topology is implemented just by
connecting directly the series PMOS transistors to the supply
voltage, since when A = B = 0, the series connected PMOS
transistors are connected to VDD to raise the input of both
the inverters for sum (S) and carry (Co). The Transmission
gate (TG) based 1-bit full adder [8] called TG(MOS) shown in
Fig. 3, is a high-speed low-power full adder, but if cascaded
in series, its propagation delay increases which may be
unacceptable in case of long chain of full adders. This problem
is mitigated in TGdrivcap full adder [8] shown in Fig. 4.

Figure 4. TGdrivcap

Figure 1. Static CMOS 1-bit full adder

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Figure 5. Leap full adder

The LEAP (Lean Integration with Pass-Transistor) adder
shown in Fig. 5 is an attempt to clarify the possibilities of
top-down pass-transistor design [9]. Due to worst case 2×Vt
drop in transmission of input A and B at the input of first two
inverters two weak PMOS keeper transistors are used. This Figure 7. CPL version of 1-bit full adder
topology functions correctly at VDD = 1 V with Vt = 0.4 V [9], The CPL has topology with differential inputs and it is
but does not functions correctly at lower voltages. The implemented with NMOS pass-transistors. The cross-
hybrid full adder shown in Fig. 6 is based on XOR–XNOR coupled PMOS transistors for SUM (S) and CARRY (Co)
circuit that generates XOR and XNOR full swing outputs outputs are used as level restorer to reduce the short-circuit
simultaneously. Hybrid-CMOS design style gives more power dissipation. This topology provides high-speed and
freedom to the designer to select different modules in a circuit full-swing operation. It has good driving capability due to
depending upon the application [10]. The Complementary the presence of output static inverters and the fast differential
Pass-transistor Logic (CPL) [11] full adder considered for the stage of cross-coupled PMOS transistors. However, due to
analysis in this paper is shown in Fig. 7. the presence of a lot of internal nodes and static inverters,
there is large power dissipation. Other recently proposed 1-
bit full adders such as 8T, 10T full adder [12] shown in Fig. 8
and 9, 12T full adder [13] shown in Fig. 10, 14T and CLRCL
(complementary and level restoring carry logic) full adder
[14] shown in Fig. 11 and 12 are analyzed in this work. The
results of the analyses are not reported here because these
full adders function well up to 50 kHz at higher technology
nodes, whereas these analyses are carried out at 100 MHz at
VDD ranging from 1 V down to 0.7 V at 22 nm technology
node. The dynamic CMOS logic style provides a high speed
of operation because the logic is constructed with only high
mobility NMOS transistors. In addition, due to the absence
of the PMOS transistors, the input capacitance is also low,
thus enhancing the speed of operation. However, it has several
inherent drawbacks such as charge sharing and high clock
load. Albeit it has higher switching activity, it has lower noise
Figure 6. Hybrid full adder immunity; it consumes a larger portion of the power in driving
the clock lines. Moreover, dynamic logic style is more
susceptible to leakage. Due to these reasons, full adders
with dynamic logic style are not considered for analysis in
this paper.
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Figure 12. CLRCL full adder

Figure 8. 8T full adder

Figure 9. 10T full adder Figure 13. Propagation delay distribution

Since the overall speed of an n-bit full adder relies on the
delay of final carry output, it makes sense to estimate
propagation delay (tp) considering delay between Ci (carry
in) and Co (carryout). Thus, tp is estimated as the time interval
between the time the input signal (Ci) takes to reach 50% of
its logic swing and the time the output signal (Co) takes to
reach the same value. The power consumption (P) is estimated
by taking the average power Pavg) delivered by VDD.

Figure 10. 12T full adder

Figure 11. 14T full adder Figure 14. Power dissipation distribution

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Figure 1 7. Average energy delay produ ct of MOSFET fu ll adder

topologies
Thus, TG(MOS) full adder topology outperforms other two
Figure 15. EDP distribution
topologies in terms of average power dissipation. Fig. 17
shows average EDP of CPL, CMOS and TG(MOS) and exhibits
Reducing EDP (energy delay product) is a good direction for
superiority of TG(MOS) among these topologies.
optimizing VLSI design for portable use since ED product
reflects the battery consumption (E) for completing a job in a
IV. CNFET STRUCTURE AND ITS CHARACTERISTICS
certain time (D). The EDP is estimated as the product of (tp)2
with average dissipated power, P (i.e., Pavg). However, due to The cylindrical carbon nanotubes (CNTs) exhibit
lack of space measured values of tp, P and EDP of all full extraordinary strength and unique electrical properties. Their
adders are not reported here, rather their dispersions are pre- name is derived from their size, since the diameter of a
sented, since dispersion in these metrics are severe at highly nanotube is on the order of a few nanometres, while they can
scaled technology node such as 22 nm. As the S.D. (stan- be up to 18 centimetres in length (as of 2010) [15]. CNT is
dard deviation) is a measure of dispersion that states numeri- categorized as single-walled carbon nanotube (SWCNT) as
cally the extent to which individual observations vary on the shown in Fig. 18(a) and multi-walled carbon nanotube
average, it is used as a measure of variation in full adder (MWCNT) as shown in Fig. 18(b). Most SWCNTs have a
design metrics such as tp (propagation delay), P (power dissi- diameter of close to 1 nm, with a tube length that can be many
pation) and EDP (energy delay product). Dispersion analy- millions of times longer. The structure of a SWCNT can be
ses of full adder topologies of Fig. 1–7 are presented in Fig. conceptualized by wrapping a one-atom-thick layer of
13, 14 and 15. It is observed from these figures that TG(MOS) graphite called graphene into a flawless cylinder. One
is the best among all these MOSFET full adder topologies in useful application of SWCNTs is in the development of
terms of dispersion of these vital parameters at all consid- CNFET. Production of the first logic gate using CNFET has
ered supply voltages. This is attributed to the fact that the recently become possible [16]. As variation in feature size
parallel devices in TG average out the impact of PVT varia- and Vt is inherent to technology scaling, it is difficult to
tions. Therefore, it is selected for comparison with proposed improve device performance by reducing the feature size of
TG(CNT). Moreover, P and EDP of CPL, CMOS (representa- the devices beyond 45 nm technology generation. Hence,
tive of full adders with driving capability) and TG(MOS) (rep- last few years witnessed a tremendous increase in
resentative of full adder without driving capability) are plot- nanotechnology research, especially the nanoelectronics.
ted in Fig. 16 and 17. As mentioned earlier, due to the pres- CNTs are the most studied material because of their unique
ence of many internal nodes and static inverters, there is mechanical and electronic properties. With ultralong (~1µm)
large power dissipation in CPL. This is evident from Fig. 16, mean free path for elastic scattering, a ballistic or near-ballistic
which shows average power dissipation of CPL CMOS and transport can be obtained with the use of CNT under low
TG(MOS). voltage bias to achieve the ultimate device performance
[17]–[20]. Its quasi-1-D structure provides better electrostatic
control over the channel region. Ballistic transport operation
and low IOFF (off current) make the CNFET a suitable device
for high performance and increased integration. The CNT
acts as metal if n1 = n2 or (n1 – n2)/3 = i, where i is an integer..
Otherwise, CNT works as semiconductor. The Vt of CNFET
can be varied with CNT diameter (DCNT). Vt of CNFET is
approximated to the first order as the half band gap (Vt H” Eg/
2q), which is an inverse function of diameter. The DCNT and Vt
of CNT are calculated using chirality vector (n1, n2) and Vπ
Figure16. Average power dissipation of MOSFET full adder respectively as [21]
topologies
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hafnium (HfO2) having dielectric constant of (Kox) 16 and

thickness (tox) of 4 nm. The effective width (Fig. 19(a)) of the
multi-tubed CNFET (Wg) is defined as Wg = Pitch×(NCNT)+DCNT,
where Pitch is the distance between centre of two adjacent
tubes, NCNT is the number of tubes and DCNT is the diameter of
where Eg is energy gap, q = electronic charge, a = “3d = 2.49 tube. Other important device and technology parameters re-
Å is the lattice constant (where d H” 1.44 Å is the inter– lated to CNFET are tabulated in Table I. The I-V characteris-
carbon–atom distance) and Vπ = 3.033 eV is the carbon π–to– tics of used CNFETs with chirality vector (19, 0) and mini-
π bond energy in the tight bonding model. In this work, mum-sized square NMOS (22 nm × 22 nm) with zero bias
CNFETs with chiral vector value (19, 0) are used. The DCNT of threshold voltage, Vtn0 = 0.68858 V are plotted in Fig. 20. P-
the CNFET with chiral vector value (19, 0) is computed using type CNFET used in the proposed design has I-V character-
(6) to be 1.5 nm. The Vt of the CNFET with chiral vector value istics with opposite polarity (not shown). The threshold volt-
of (19, 0) is computed using (7) to be 0.29 V. ages of N-CNFET are computed using (6) and (7) with chirality
vector ranging from (7, 0) to (36, 0). First, the DCNT is esti-
mated substituting the value of the constant ð = 3.142, the
value lattice constant a = 2.49 Å and the value of n1 ranging
from 7 to 36 keeping n2 = 0. Next, the threshold voltage Vt is
estimated substituting the value of a = 2.49 Å, the value of
the carbon ð-to-ð bond energy Vð = 3.033 eV, the value of
electronic charge q = 1.6×10-19 C and the estimated value of
DCNT. The estimated values of threshold voltages for each
values of n1 ranging from 7 to 36 are plotted in Fig. 21. The
Figure 18. (a) SWCNT (Single-walled carbon nanotube), and (b)
MWCNT (Muli-walled carbon nanotube)
plot in Fig. 21 shows the Vts of N-type CNFET with CNTs of
different chirality vectors. For P-type CNFET, the Vt has an
opposite polarity. The plot in Fig. 21 shows two end-points
with Vt = 0.78857 V at n1 = 7 and Vt = 0.153 V at n1 = 36. Other
important point in this plot is (19, 0.29) which indicates Vt =
0.29 V at n1 = 19. This is the threshold voltage of CNFETs
used in the proposed design.
TABLE I. DEVICE AND TECHNOLOGY PARAMETERS FOR CNFET

Figure 19. A typical CNFET structure with (a) multiple CNT and
(b) single CNT (with high-k gate dielectric material HfO 2 ) [22],
[2 3]
Compared to CMOS circuits, the CNFET circuit with one to
ten CNTs per device is about two to ten times faster [22], [23].
Figure 20. Comparison of I-V characteristics of NMOS and N-CNFET
A typical structure of a CNFET with multiple CNTs is illus-
trated in Fig. 19(a). Fig. 19(b) illustrates a CNFET structure
with single CNT. CNTs are placed on substrate having di-
electric constant of Ksub = 4. The channel region of CNTs is
un-doped, and the other regions of CNTs are heavily doped.
The tubes are separated by a high-k (Hi-k) material called
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Figure 21. Threshold voltage (Vt) versus chirality vector (n 1 )

V. SIMULATION RESULTS OF PROPOSED CNFET-BASED 1-BIT Figure 23. Proposed TG(CNT)

DIGITAL SUMMING CIRCUIT AND COMPARISON
TABLE I. VARIABILITY OF PROPAGATION DELAY
To simulate real environment, buffers are used for all
inputs of the test circuit. A minimum output load of fan-out of
four inverters (FO4) is used for power, delay and EDP
measurements. The simulation test bench for the 1-bit full
adder, which is circuit under test (CUT), is shown in Fig. 22.
All the previous and following simulations are carried out
using this simulation test bench. Analyses of full adders in
Section III show that the TG-based 1-bit full adder topology
exhibits immunity against PVT variations compared to other
digital summing circuits. Therefore, in this paper CNFET-
based 1-bit full adder cell of TG topology is designed, and its
performance is assessed and compared with MOSFET
version, i.e., TG(MOS). Fig. 23 shows the proposed design.
Equations (4) and (5) are implemented by the proposed design
as is done by its CMOS counterpart. The summation of two
currents IDn and IDp flowing through NMOS and PMOS Figure 24. Propagation delay variation versus VDD plot
transistors of a transmission gate is primarily responsible for This happens because a variation in the gate oxide thickness
the lower value of variability in case of TG-based design. that strongly affects the drive current and capacitance of
This averaging is impossible in case of other designs due to CMOS transistors has a negligible impact on the CNFET’s
absence of parallel transistors. Variability of tp is estimated as operation. Hence, TG(CNT) is superior to TG(MOS) 1-bit full
the standard deviation of delay divided by mean delay. The adder in terms of delay. It is needless to say that, TG(CNT)
comparison of tp distribution between TG(MOS) and TG(CNT) digital summing circuit will outperform the other full adder
is reported in Table II and plotted in Fig. 24 for making topologies analyzed earlier. The only drawback of TG(CNT)
comparison easier. The values normalized with respect to is its configuration, which is transmission gate based. With
TG(CNT) are reported in bracket. It is observed from the Table this configuration, the output is not isolated from the input,
II that the variability of tp of TG(MOS) is wider than that of whereas the topologies such as static CMOS, Mirror, and
TG(CNT) at all supply voltages, particularly at nominal voltage CPL adder circuits isolate the output from the input and their
of VDD =0.950 V, it is 3× wider than that of TG(CNT). driving capability is higher. As observed from Fig. 20, the
drive current of CNFET is higher than that of a minimum-
sized NMOS transistor. This is due to appropriate selection
of chirality vector to estimate its Vt as shown in Fig. 21, which
shows that the Vt of CNFET can be varied from 0.78857 V to
0.153 V with n1 ranging from 7 to 36 keeping n2 = 0. The Vt
used for CNFET is much lower than that that of MOSFET. Of
Figure 22. Simulation test bench
course, the drive current of CNFET used in TG(CNT) can
further be enhanced by using more number of tubes. CNFETs
with four tubes are used for increasing the driving capability
of TG(CNT) digital summing circuit proposed in this paper.
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The comparison of power variation between TG(MOS) and VI. CONCLUSION

TG(CNT) is reported in Table III. The values normalized with
This paper analyzes the robustness of various digital
respect to TG(CNT) are reported in bracket. It is observed
summing circuits and proposes a CNFET version of the most
from the Table III, that the power dissipation variability of
robust MOSFET topology. It demonstrates that CNFET-based
TG(MOS) is wider than that of TG(CNT) full adder circuit.
digital summing circuit is more robust against process and
temperature variations compared to MOSFET digital summing
TABLE III. VARIABILITY OF POWER DISSIPATION circuits. It also demonstrates with simulation results that the
proposed design performs well with supply voltage variation
(±10% of VDD) under appropriate loading conditions at 22 nm
technology node. The proposed CNFET-based design will
be an attractive choice to replace MOSFET version of digital
The likely causes are attributed to the fact that the gate width summing circuit to achieve higher immunity against PVT
in CNFET is not the effective channel width of the transistor. variations.
The channel width actually depends only on the tube diameter
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vol. 87, no. 25, pp. 256805/1-256805/4, Dec. 2001. Aminul Islam (M’10) graduated in Computer Engineering from
[17] A. Javey, et al., “Carbon nanotube field-effect transistors with The Institution of Engineers (India) in 2001, and post graduated in
integrated ohmic contacts and high-k gate dielectrics,” Nano Lett., Electronics and Communication Engineering from Birla Institute of
vol. 4, no. 3, pp. 447–450, Feb. 2004. Technology (BIT) (deemed university), Mesra, Ranchi, Jharkhand,
[18] Z. Yao, C. L. Kane, and C. Dekker, “High-field electrical India in 2006. Until November 2006, he was with Indian Air Force.
transport in single-wall carbon nanotubes,” Phys. Rev. Lett., vol. Since November 2006, he has been with the Electronics and Com-
84, no. 13, pp. 2941– 2944, Mar. 2000. munication Engineering Department, BIT, Mesra, Ranchi,
[19] D. Mann, A. Javey, J. Kong, Q. Wang, and H. Dai, “Ballistic Jharkhand, India, where he is currently an Asst. Professor. His
transport in metallic nanotubes with reliable Pd ohmic [1] research interests include VLSI design for nanoscale Silicon and
contacts,” Nano Lett., vol. 3, no. 11, pp. 1541–1544, Oct. 2003. non-Silicon technologies, robust design of ultralow power nanoscale
[20] Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber, circuit. He is currently working toward the Ph.D. degree in the field
“High performance silicon nanowire field effect transistors,” Nano of VLSI design from the Department of Electronics Engineering,
Lett., vol. 3, no. 2, pp. 149–152, Jan. 2003. Aligarh Muslim University (AMU), Aligarh, (U.P.), India. He has
[21] Stanford University CNFET Model, (2008). [Online]. published more than 15 research papers in reputed Conferences
Available: http://nano.stanford.edu/model.php?id=23 and Journals.
[22] J. Deng, and H.-S. P. Wong, “A compact SPICE model for Dr. Mohd Hasan (M’10) received the B.Tech. degree in Electron-
carbon-nanotube field-effect transistors including nonidealities and ics Engineering from AMU, India in 1990, the M.Tech. degree in
its application - part I: model of the intrinsic channel region,” IEEE Integrated Electronics and Circuits from the IIT, Delhi, India in
Trans. Electron Devices, vol. 54, no. 12, pp. 3186-3194, Dec. 2007 1992 and joined as Lecturer in Electronics Engineering Department
[23] J. Deng, and H.-S. P. Wong, “A compact SPICE model for of AMU in 1992. He received the Ph.D. degree from the University
carbon-nanotube field-effect transistors including nonidealities and of Edinburgh, UK in 2004. He has also worked as a postdoctoral
its application - part II: full device model and circuit performance visiting researcher in the School of Engineering, University of
benchmarking,” IEEE Trans. Electron Devices, vol. 54, no. 12, pp. Edinburgh, UK. He has been currently working as Professor at
3195-3205, Dec. 2007. AMU, since 2005. He has published more than 80 research papers
in reputed Journals and Conferences. His research interest includes
Low power VLSI design, Nanoelectronics, FPGA Architectures
along with Embedded System Design.

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© 2011 ACEEE
DOI: 01.IJCOM.02.02.529
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