MODULE-2

INSTRUCTION SET

Prepared & Presented by

Chandra Prabha Nagarajan
 I. 8051 ADDRESSING MODES
• Introduction
• Types
• Explanation
 Types
1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
5. Relative addressing.
6. Absolute addressing.
7. Long addressing.
8. Indexed addressing.
9. Bit inherent addressing.
10. Bit direct addressing.
1. Immediate addressing.
• In this addressing mode the data is provided

as a part of instruction itself.

• In other words data immediately follows the

instruction.
• Eg. MOV A,#30H

ADD A, #83
• # Symbol indicates the data is immediate.
2. Register addressing
• In this addressing mode the register will hold

the data.
• One of the eight general registers (R0 to R7)

can be used and specified as the operand.

• Eg. MOV A,R0

• ADD A,R6

• R0 – R7 will be selected from the current

selection of register bank. The default register

bank will be bank 0
3. Direct addressing

• There are two ways to access the internal

memory.
• Using direct address and indirect address.
• Using direct addressing mode we can not only
address the internal memory but SFRs also.
• In direct addressing, an 8 bit internal data
memory address is specified as part of the
instruction and hence, it can specify the
address only in the range of 00H to FFH.
• In this addressing mode, data is obtained
directly from the memory.
• Eg. MOV A,60h
ADD A,30h
4. Indirect addressing
• The indirect addressing mode uses a register
to hold the actual address that will be used in
data movement.
• Registers R0 and R1 and DPTR are the only
registers that can be used as data pointers.
• Indirect addressing cannot be used to refer to
SFR registers.
• Both R0 and R1 can hold 8 bit address and
DPTR can hold 16 bit address.
• Eg. MOV A,@R0
ADD A,@R1
MOVX A,@DPTR
5. Indexed addressing.
• In indexed addressing, either the program counter (PC), or
the data pointer (DTPR)—is used to hold the base address,
and the A is used to hold the offset address.
• Adding the value of the base address to the value of the
offset address forms the effective address.
• Indexed addressing is used with JMP or MOVC instructions.
• Look up tables are easily implemented with the help of
index addressing.
• Eg. MOVC A, @A+DPTR // copies the contents of memory
location pointed by the sum of the accumulator A and the
DPTR into accumulator A.
MOVC A, @A+PC // copies the contents of memory
location pointed by the sum of the accumulator A and the
program counter into accumulator A.
6. Relative Addressing.
• Relative addressing is used only with conditional jump
instructions.
• The relative address, (offset), is an 8 bit signed
number, which is automatically added to the PC to
make the address of the next instruction.
• The 8 bit signed offset value gives an address range of
+127 to —128 locations.
• The jump destination is usually specified using a label
and the assembler calculates the jump offset
accordingly.
• The advantage of relative addressing is that the
program code is easy to relocate and the address is
relative to position in the memory.
• Eg. SJMP LOOP1
JC BACK
7. Absolute addressing
• Absolute addressing is used only by the AJMP
(Absolute Jump) and ACALL (Absolute Call)
instructions. These are 2 bytes instructions.
• The absolute addressing mode specifies the
lowest 11 bit of the memory address as part
of the instruction.
• The upper 5 bit of the destination address are
the upper 5 bit of the current program
counter.
• Hence, absolute addressing allows branching
only within the current 2 Kbyte page of the
program memory.
• Eg. AJMP LOOP1
ACALL LOOP2
8. Long Addressing
• The long addressing mode is used with the

instructions LJMP and LCALL. These are 3 byte

instructions.
• The address specifies a full 16 bit destination

address so that a jump or a call can be made

to a location within a 64 Kbyte code memory
space.
• Eg. LJMP FINISH

LCALL DELAY
9. Bit Inherent Addressing
• In this addressing, the address of the flag

which contains the operand, is implied in the

opcode of the instruction.
• Eg. CLR C ; Clears the carry flag to 0
10. Bit Direct Addressing
• In this addressing mode the direct address of

the bit is specified in the instruction.

• The RAM space 20H to 2FH and most of the

special function registers are bit addressable.

• Bit address values are between 00H to 7FH.

• Eg. CLR 07h ; Clears the bit 7 of 20h RAM

space
SETB 07H ; Sets the bit 7 of 20H RAM space
 II. DATA TRANSFER
INSTRUCTIONS-8051
• Definition
• Examples
• Description
a. Move the contents of a register Rn to A
i. MOV A,R2
ii. MOV A,R7

b. Move the contents of a register A to Rn

i. MOV R4,A
ii. MOV R1,A

c. Move an immediate 8 bit data to register A or to Rn

or to a memory location(direct or indirect)
i. MOV A, #45H
ii. MOV R6, #51H
iii.MOV 30H, #44H
iv. MOV @R0, #0E8H
v. MOV DPTR, #0F5A2H
vi. MOV DPTR, #5467H
d. Move the contents of a memory location to A or A to
a memory location using direct and indirect addressing
i. MOV A, 65H
ii. MOV A, @R0
iii. MOV 45H, A
iv. MOV @R1, A

e. Move the contents of a memory location to Rn or Rn

to a memory location using direct addressing
i. MOV R3, 65H
ii. MOV 45H, R2

f. Move the contents of memory location to another

memory location using direct and indirect addressing
i. MOV 47H, 65H
ii. MOV 45H, @R0
g. Move the contents of an external memory to
A or A to an external memory
i. MOVX A,@R1
ii. MOVX @R0,A
iii.MOVX A,@DPTR
iv. MOVX@DPTR,A

h. Move the contents of program memory to A

i. MOVC A, @A+PC
ii. MOVC A, @A+DPTR
i. Push and Pop instructions
[SP]=07 //CONTENT OF SP IS 07 (DEFAULT VALUE)

MOV R6, #25H

[R6]=25H //CONTENT OF R6 IS 25H

MOV R1, #12H

[R1]=12H //CONTENT OF R1 IS 12H

MOV R4, #0F3H

[R4]=F3H //CONTENT OF R4 IS F3H

PUSH 6 [SP]=08 [08]=[06]=25H //CONTENT OF 08 IS 25H

PUSH 1 [SP]=09 [09]=[01]=12H //CONTENT OF 09 IS 12H
PUSH 4 [SP]=0A [0A]=[04]=F3H //CONTENT OF 0A IS F3H

POP 6 [06]=[0A]=F3H [SP]=09 //CONTENT OF 06 IS F3H

POP 1 [01]=[09]=12H [SP]=08 //CONTENT OF 01 IS 12H
POP 4 [04]=[08]=25H [SP]=07 //CONTENT OF 04 IS 25H
j. Exchange instructions.The content of source
ie., register, direct memory or indirect memory
will be exchanged with the contents of
destination ie., accumulator.
i. XCH A,R3
ii. XCH A,@R1
iii. XCH A,54h

k. Exchange digit. Exchange the lower order

nibble of Accumulator (A0-A3) with lower order
nibble of the internal RAM location which is
indirectly addressed by the register.
i. XCHD A,@R1
ii. XCHD A,@R0
 III. ARITHMETIC INSTRUCTIONS-8051
• Introduction
• Examples
• Description

Introduction: The 8051 can perform addition,

subtraction. Multiplication and division
operations on 8 bit numbers.
 Addition
i. Add the contents of A with immediate data with or without carry.
i. ADD A, #45H
ii. ADDC A, #OB4H

ii. Add the contents of A with register Rn with or without carry.

i. ADD A, R5
ii. ADDC A, R2

iii. Add the contents of A with contents of memory with or without

carry using direct and indirect addressing
i. ADD A, 51H
ii. ADDC A, 75H
iii. ADD A, @R1
iv. ADDC A, @R0

CY AC and OV flags will be affected by this operation.

 Subtraction
i. Subtract the contents of A with immediate data with or without
carry.
i. SUBB A, #45H
ii. SUBB A, #OB4H

ii. Subtract the contents of A with register Rn with or without carry.

i. SUBB A, R5
ii. SUBB A, R2

iii. Subtract the contents of A with contents of memory with or

without carry using direct and indirect addressing
i. SUBB A, 51H
ii. SUBB A, 75H
iii. SUBB A, @R1
iv. SUBB A, @R0

CY AC and OV flags will be affected by this operation.

 Multiplication
MUL AB:
This instruction multiplies two 8 bit unsigned
numbers which are stored in A and B register.
After multiplication the lower byte of the result
will be stored in accumulator and higher byte of
result will be stored in B register.

Eg.
MOV A,#45H ;[A]=45H
MOV B,#0F5H ;[B]=F5H
MUL AB ;[A] x [B] = 45 x F5 = 4209

[A]=09H, [B]=42H
 Division
DIV AB:
This instruction divides the 8 bit unsigned number
which is stored in A by the 8 bit unsigned number
which is stored in B register. After division the result
will be stored in accumulator and remainder will be
stored in B register.

Eg.
MOV A,#45H ;[A]=0E8H
MOV B,#0F5H ;[B]=1BH
DIV AB ;[A] / [B] = E8 /1B = 08 H with
remainder 10H

[A] = 08H, [B]=10H

 DA A (Decimal Adjust After Addition)
When two BCD numbers are added, the answer is a non-BCD number.
To get the result in BCD, we use DA A instruction after the addition. DA
A works as follows.
• If lower nibble is greater than 9 or auxiliary carry is 1, 6 is added to
lower nibble.
• If upper nibble is greater than 9 or carry is 1, 6 is added to upper
nibble.

Eg 1:
MOV A,#23H
MOV R1,#55H
ADD A,R1 // [A]=78
DA A // [A]=78 no changes in the accumulator after DA A
Eg 2:
MOV A,#53H
MOV R1,#58H
ADD A,R1 // [A]=ABH
DA A // [A]=11, C=1 . ANSWER IS 111. Accumulator data is
changed after DA A
 Increment
Increments the operand by one.
INC A
INC Rn
INC DIRECT
INC @Ri
INC DPTR

INC increments the value of source by 1. If the initial value of

register is FFh, incrementing the value will cause it to reset to
0.

The Carry Flag is not set when the value "rolls over" from 255
to 0.

In the case of "INC DPTR", the value two-byte unsigned integer

value of DPTR is incremented. If the initial value of DPTR is
FFFFh, incrementing the value will cause it to reset to 0.
 Decrement
Decrements the operand by one.
DEC A
DEC Rn
DEC DIRECT
DEC @Ri

DEC decrements the value of source by 1.

If the initial value of is 0, decrementing the value

will cause it to reset to FFh.

The Carry Flag is not set when the value "rolls

over" from 0 to FFh.
 IV. LOGICAL INSTRUCTIONS-8051
• Introduction
• Examples
• Description
 Logical AND
• ANL destination, source:
ANL does a bitwise "AND" operation between source and
destination,leaving the resulting value in destination.

• The value in source is not affected.

• "AND" instruction logically AND the bits of source and

destination.

ANL A,#DATA
ANL A, Rn
ANL A,DIRECT
ANL A,@Ri
ANL DIRECT,A
ANL DIRECT, #DATA
 Logical OR
• ORL destination, source:
ORL does a bitwise "OR" operation between source and
destination, leaving the resulting value in destination.

• The value in source is not affected.

• " OR " instruction logically OR the bits of source and

destination.

ORL A,#DATA
ORL A, Rn
ORL A,DIRECT
ORL A,@Ri
ORL DIRECT,A
ORL DIRECT, #DATA
 Logical Ex-OR
• XRL destination, source:
XRL does a bitwise "EX-OR" operation between source and
destination, leaving the resulting value in destination.

• The value in source is not affected.

• " XRL " instruction logically EX-OR the bits of source and
destination.

XRL A,#DATA
XRL A,Rn
XRL A,DIRECT
XRL A,@Ri
XRL DIRECT,A
XRL DIRECT, #DATA
 Logical NOT
• CPL complements operand, leaving the result
in operand. If operand is a single bit then the
state of the bit will be reversed.

• If operand is the Accumulator then all the bits

in the Accumulator will be reversed.

• CPL A, CPL C, CPL bit address

• SWAP A – Swap the upper nibble and lower

nibble of A.
 Rotate Instructions
RR A:
This instruction is rotate right the accumulator.
Its operation is illustrated below. Each bit is
shifted one location to the right, with bit 0 going
to bit 7.
RL A:

Rotate left the accumulator. Each bit is shifted

one location to the left, with bit 7 going to bit 0
RRC A:

Rotate right through the carry. Each bit is shifted

one location to the right, with bit 0 going into
the carry bit in the PSW, while the carry was at
goes into bit 7.
RLC A:

Rotate left through the carry. Each bit is shifted

one location to the left, with bit 7 going into the
carry bit in the PSW, while the carry goes into bit
0.
V. JUMP & CALL INSTRUCTIONS-8051
• Branch (JUMP) Instructions
• Jump and Call Program Range
There are 3 types of jump instructions.
1. Relative Jump
2. Short Absolute Jump
3. Long Absolute Jump
 Relative Jump
Jump that replaces the PC (program counter)
content with a new address that is greater than
(the address following the jump instruction by
127 or less) or less than (the address following
the jump by 128 or less) is called a relative jump.
Advantages:
1. Only 1 byte of jump address needs to be
specified in the 2's complement form, ie. For
jumping ahead, the range is 0 to 127 and for
jumping back, the range is -1 to -128.

2. Specifying only one byte reduces the size of

the instruction and speeds up program
execution.

3. The program with relative jumps can be

relocated without reassembling to generate
absolute jump addresses.
Disadvantages:
1. Short jump range (-128 to 127 from the
instruction following the jump instruction)
Instructions that use Relative Jump

SJMP <relative address>; this is unconditional jump

The remaining relative jumps are conditional jumps

JC <relative address>
JNC <relative address>
JB bit <relative address>
JNB bit <relative address>
JBC bit <relative address>
CJNE <destination byte>,<source byte>, <relative
address>
DJNZ <byte>, <relative address>
JZ <relative address>
JNZ <relative address>
 Short Absolute Jump

In this case only 11 bits of the absolute jump

address are needed. The absolute jump address
is calculated in the following manner.

In 8051, 64 kbyte of program memory space is

divided into 32 pages of 2 kbyte each.
The hexadecimal addresses of the pages are
given as follows:-
It can be seen that the upper 5 bits of the program
counter (PC) hold the page number and the lower
11bits of the PC hold the address within that page.

Thus, an absolute address is formed by taking page

numbers of the instruction (from the program
counter) following the jump and attaching the
specified 11 bits to it to form the 16-bit address.

Advantage: The instruction length becomes 2 bytes.

Example of short absolute jump:

ACALL <address 11>
AJMP <address 11>
 Long Absolute Jump/Call
Applications that need to access the entire
program memory from 0000H to FFFFH use long
absolute jump.

Since the absolute address has to be specified in

the op-code, the instruction length is 3 bytes
(except for JMP @ A+DPTR).

This jump is not re-locatable.

Example:
LCALL <address 16>
LJMP <address 16>
JMP @A+DPTR

Another classification of jump instructions:

1. Unconditional Jump
2. Conditional Jump
1. The unconditional jump is a jump in which control is
transferred unconditionally to the target location.

a. LJMP (long jump): This is a 3-byte instruction. First byte is

the op-code and second and third bytes represent the 16-bit
target address which is any memory location from 0000 to
FFFFH eg: LJMP 3000H

b. AJMP: this causes unconditional branch to the indicated

address, by loading the 11 bit address to 0 -10 bits of the
program counter. The destination must be therefore within the
same 2K blocks.

c. SJMP (short jump): This is a 2-byte instruction. First byte is

the op-code and second byte is the relative target address, 00
to FFH (forward +127 and backward -128 bytes from the
current PC value). To calculate the target address of a short
jump, the second byte is added to the PC value which is
address of the instruction immediately below the jump.
2. Conditional Jump instructions:

All conditional jumps are short jumps.

 Bit level jump instructions
Bit level JUMP instructions will check the conditions
of the bit and if condition is true, it jumps to the
address specified in the instruction. All the bit jumps
are relative jumps.

JB bit, rel ; jump if the direct bit is set to the relative

address specified.

JNB bit, rel ; jump if the direct bit is clear to the

relative address specified.

JBC bit, rel ; jump if the direct bit is set to the

relative address specified and then clear the bit.
 VI. STACK & SUBROUTINE
INSTRUCTIONS-8051
Subroutines are handled by CALL and RET
instructions.

There are two types of CALL instructions:

1. LCALL address(16 bit)
2. ACALL address(11 bit)
 1. LCALL address(16 bit)
This is long call instruction which unconditionally calls the subroutine located
at the indicated 16 bit address. This is a 3 byte instruction.

a. During execution of LCALL, [PC] = [PC]+3; (if address where LCALL resides is
say, 0x3254; during execution of this instruction [PC] = 3254h + 3h = 3257h

b. [SP]=[SP]+1; (if SP contains default value 07, then SP increments and

[SP]=08

c. [[SP]] = [PC7-0]; (lower byte of PC content ie., 57 will be stored in memory

location 08.

d. [SP]=[SP]+1; (SP increments again and [SP]=09) e. [[SP]] = [PC15-8]; (higher

byte of PC content ie., 32 will be stored in memory location 09.

With these the address (0x3254) which was in PC is stored in stack.

f. [PC]= address (16 bit); the new address of subroutine is loaded to PC. No
flags are affected.
 2. ACALL address(11 bit)
This is absolute call instruction which unconditionally calls the subroutine
located at the indicated 11 bit address. This is a 2 byte instruction.

a. During execution of SCALL, [PC] = [PC]+2; (if address where LCALL resides is
say, 0x8549; during execution of this instruction [PC] = 8549h + 2h = 854Bh

b. [SP]=[SP]+1; (if SP contains default value 07, then SP increments and

[SP]=08

c. [[SP]] = [PC7-0]; (lower byte of PC content ie., 4B will be stored in memory

location 08.

d. [SP]=[SP]+1; (SP increments again and [SP]=09)

e. [[SP]] = [PC15-8]; (higher byte of PC content ie., 85 will be stored in

memory location 09.

With these the address (0x854B) which was in PC is stored in stack.

f. [PC10-0]= address (11 bit); the new address of subroutine is loaded to PC.
No flags are affected.
 RET instruction
RET instruction pops top two contents from the
stack and load it to PC.

g. [PC15-8] = [[SP]] ;content of current top of the

stack will be moved to higher byte of PC.

h. [SP]=[SP]-1; (SP decrements)

i. [PC7-0] = [[SP]] ;content of bottom of the stack

will be moved to lower byte of PC.

j. [SP]=[SP]-1; (SP decrements again)