THE SYNTHESIS APPROACH TO

DIGITAL SYSTEM DESIGN

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 THE SYNTHESIS APPROACH TO
DIGITAL SYSTEM DESIGN

edited by

Petra Michel
Ulrich Lauther
PeterDuzy

SiemensAG

foreword by
A. Richard Newton

"
~.

SPRINGER SCIENCE+BUSINESS MEDIA, LLC

 Library of Congress Cataloging-in-Publication Data

The Synthesis approach to digital system design I edited by Petra

Michel, Ulrich Lauther, Peter Duzy.
p. cm. -- (The Kluwer international series in engineering and
computer science. VLSI, computer arcbitecture, and digital signal
processing)
Includes bibliographical references and index.
ISBN 978-1-4613-6615-7 ISBN 978-1-4615-3632-1 (eBook)
DOI 10.1007/978-1-4615-3632-1
1. Digital electronics--Data processing. 2. Electronic circuit
design-oData processing. 3. Computer-aided design. 1. Micbel,
Petra. II. Lautber, U. III. Duzy, Peter. IV. Series.
TK7868.DSS96 1992
621.381--dc20 91-46109
CIP

Copyright © 1992 Springer Science+Business Media New York

Originally published by Kluwer Academic Publishers in 1992
Softcover reprint ofthe hardcover Ist edition 1992
AlI rights reserved. No part of this publication may be reproduced, stored in a retrieval
system or transmitted in any form or by any means, mechanical, photo-copying, recording,
or otherwise, without the prior written permission of the publisher, Springer
Science+Business Media, LLC .

Printed on acid-free paper.

Contents

Foreword xi

Acknowledgements xiii

1 Introduction to Synthesis 1
1.1 The Y-Chart-Levels and Domains of Description 3
1.2 Design Flow and Taxonomy of Synthesis 9
1.2.1 System-Level Synthesis . . . . . 9
1.2.2 High-Level Synthesis . . . . . . . 9
1.2.3 Register-Transfer Level Synthesis 10
1.2.4 Logic-Level Synthesis .. 11
1.2.5 Technology Mapping . . . 11
1.3 Entry Points and User Interfaces 12
1.4 Validation 13
1.5 Testing 13

2 Hardware Description Languages and their Relevance to Syn-

thesis 15
2.1 Introduction................. 15
2.2 VHDL Example - Bar-Code Preprocessor 16
2.3 VHDL Hardware Description Language 19
2.4 Relevance of HDLs to Synthesis. . 29
2.4.1 Multi-Level Descriptions. . . . . 30
2.4.2 Formal Semantics of HDLs .. . 30
2.4.3 Synthesis-Specific Language Requirements . 30
2.4.4 Validation Aspect . . . . . 32
2.4.5 Synthesis Subset Definition 33
2.5 Outlook . . . . . . . . . 36
2.6 Problems for the Reader . . . . . . 37
Vi The Synthesis Approach to Digital System Design

3 Logic-Level Synthesis 39
3.1 Introduction................ .. 39
3.2 Preliminaries and Definitions . . . . . . .. 41
3.2.1 Representation of Boolean Functions 45
3.2.2 Manipulation of Boolean Functions. 48
3.3 Minimization of Two-Level Logic . 50
3.3.1 Optimization Problem . 50
3.3.2 Basics of Two-Level Logic Minimization 52
3.3.3 Exact Algorithm . . . . . . . . . .. 56
3.3.4 Simple Minimization Heuristic . . . 57
3.3.5 Minimization Heuristic ESPRESSO 58
3.4 Optimization of Multi-Level Logic 59
3.4.1 Synthesis Strategy . . . . 59
3.4.2 Optimization Problem .. 60
3.4.3 Optimization Algorithms 60
3.5 Outlook . 67
3.6 Problems for the Reader . . . . . 69
4 Technology Mapping 71
4.1 Introduction............................. 71
4.2 Abstraction of Technology . . . . . . . . . . . . . . . . . . . .. 73
4.2.1 Advantages and Disadvantages of Technology Abstraction 73
4.2.2 When to Select the Target Technology. 74
4.2.3 When to Perform Technology Mapping. 74
4.3 Logic-Level Technology Mapping 75
4.3.1 Local Methods . . . . . 77
4.3.2 Randomized Methods .. 77
4.3.3 Tree Covering Methods 77
4.4 Register-Transfer Level Technology Mapping 80
4.4.1 Module Generators. 81
4.4.2 Rule-Based Methods 82
4.5 Outlook . . . . . . . . . 84
4.6 Problems for the Reader . . 85

5 Register-Transfer Level Synthesis 87

5.1 Introduction . 87
5.2 Data Path Synthesis . 88
5.2.1 Optimization Strategies 88
5.2.2 Retiming and Resynthesis 90
5.2.3 Resource Allocation and Assignment 96
5.3 Controller Synthesis . 98
Contents Vll

5.3.1 Tasks of Controller Synthesis . 98

5.3.2 State Assignment for Controllers . 101
5.3.3 State Assignment for Single PLA Controllers 103
5.3.4 State Assignment Targeting Multi-Level Logic 110
5.4 Outlook . . . . . . . . . 113
5.5 Problems for the Reader 114

6 High-Level Synthesis 115

6.1 Introduction.... 115
6.1.1 The Starting Point 115
6.1.2 The Target . . . . 117
6.1.3 Design Space and Constraints. 119
6.1.4 The Classical High-Level Synthesis Tasks 120
6.1.5 Practicality of High-Level Synthesis 124
6.2 Internal Representation 125
6.2.1 Internal Representation of the Algorithmic Description. 128
6.2.2 Internal Representation of the Synthesized Structure 132
6.3 Synthesis of the Register-Transfer Level Structure 133
6.3.1 Synthesis of the Differential Equation Example 135
6.3.2 Classification of Synthesis Approaches 140
6.4 Scheduling.................... . . . . . 142
6.4.1 Terminology and Assumptions . . . . . . . . . 144
6.4.2 The Two Basic Instances of the Scheduling Problem 146
6.4.3 Resource Constrained Scheduling . 149
6.4.4 Time Constrained Scheduling 161
6.4.5 Scheduling and Control Flow . . . 167
6.4.6 Pipelining.............. 173
6.4.7 Classification of Scheduling Approaches 188
6.5 Allocation and Assignment Tasks . 189
6.5.1 Alternative Approach . 189
6.5.2 Completing the Data Part . . . . . . . . 192
6.5.3 Approaches to Allocation and Assignment 193
6.5.4 Register Allocation and Assignment . . . 196
6.5.5 Separate Scheme for Allocation and Assignment 205
6.5.6 Synthesis Results . . . . . . . . . 213
6.5.7 Bus Allocation and Assignment. 214
6.6 Outlook . . . . . . . . . 216
6.7 Problems for the Reader. . . . . . . . . 218
Vlll The Synthesis Approach to Digital System Design

7 System-Level Synthesis 221

7.1 Introduction........... 221
7.1.1 What is a System? . . . 221
7.1.2 System-Level Synthesis 223
7.2 System-Level Partitioning . . . 224
7.2.1 Multi-Stage Clustering and Architectural Partitioning 226
7.2.2 Constrained Partitioning of Behavioral Models 233
7.3 Behavioral Transformations . . . . . . . . . . . . . . . . . .. 236
7.3.1 Optimizing Transformations. . . . . . . . . . . . . .. 237
7.3.2 Behavioral Transformations for System-Level Synthesis 239
7.3.3 Pipelining and Functional Pipelining . 242
7.4 Synthesizing from System-Level Descriptions 245
7.4.1 Fork/Join............. 246
7.4.2 Extended Finite State Machines 250
7.4.3 Object Oriented Techniques. 252
7.4.4 Communication. 257
7.5 Outlook . . . . . . . . . . . . 259

8 Formal Methods for Synthesis 261

8.1 Introduction......................... 261
8.2 Formal Reasoning about Digital Systems. . . . . . . . . 262
8.2.1 Motivation and Choice of a Suitable Formalism. 262
8.2.2 A Proof System for Higher-Order Logic . . . 265
8.2.3 Functional and Relational Description Styles 272
8.2.4 Formalizing Abstractions of Data and Time 275
8.2.5 Generic Hardware Models . . . . . . . . 276
8.3 Interactive, Formal Synthesis . . . . . . . . . . 278
8.3.1 The Hierarchical Refinement Approach. 279
8.3.2 Transformational Hardware Design 288
8.4 Formally Verified Synthesis Functions 295
8.4.1 Overview of Research Activities. 295
8.4.2 Generation of Instances 297
8.5 Outlook . . . . . . . . . 298
8.6 Problems for the Reader . . . . 299

9 Synthesis Related Aspects of Simulation 303

9.1 Introduction.......... 303
9.2 Multi-Level Modeling . . . . 305
9.2.1 Levels of Abstraction. 305
9.2.2 Modeling Concepts 307
9.2.3 Modeling of Time .. 310
Contents IX

9.3 Simulation Techniques . . . . . . . . 318

9.3.1 Streamline Code Simulation. 318
9.3.2 Equitemporal Iteration .. 322
9.3.3 Critical Event Scheduling 322
9.4 Multi-Level Simulation . . . . 325
9.4.1 Broadband Simulator 325
9.4.2 Multi-Simulators 326
9.5 Outlook . 329
9.6 Problems for the Reader 333

10 Synthesis Related Aspects in Testing 335

10.1 Introduction. . . . . . . . . 335
10.2 General Testability Aspects 337
10.3 Test Objects in Synthesis . 339
10.4 Test Methods for Synthesis 340
10.4.1 Scan Techniques . . 340
10.4.2 Modular Test Methods. 345
10.4.3 Built-In Self-Test (BIST) 350
10.4.4 Easily Testable Controllers 363
10.4.5 Elimination of Redundancies and Logic Optimization 365
10.4.6 Modification of Data and Control Flow Graph 367
10.5 Test Data Generation . 370
10.6 Outlook . . . . . . . . . 371
10.7 Problems for the Reader 372

Bibliography 373

Index 405
Foreword

Over the past decade there has been a dramatic change in the role played by
design automation for electronic systems. Ten years ago, integrated circuit
(IC) designers were content to use the computer for circuit, logic, and limited
amounts of high-level simulation, as well as for capturing the digitized mask
layouts used for IC manufacture. The tools were only aids to design-the
designer could always find a way to implement the chip or board manually
if the tools failed or if they did not give acceptable results. Today, however,
design technology plays an indispensable role in the design of electronic systems
and is critical to achieving time-to-market, cost, and performance targets.
In less than ten years, designers have come to rely on automatic or semi-
automatic CAD systems for the physical design of complex ICs containing over
a million transistors. In the past three years, practical logic synthesis systems
that take into account both cost and performance have become a commercial
reality and many designers have already relinquished control of the logic netlist
level of design to automatic computer aids.
To date, only in certain well-defined areas, especially digital signal process-
ing and telecommunications. have higher-level design methods and tools found
significant success. However, the forces of time-to-market and growing system
complexity will demand the broad-based adoption of high-level, automated
methods and tools over the next few years.
Research in the area of high-level design automation has been ongoing,
world wide, for more than twenty years now. Many of the techniques used
today have been adapted from earlier approaches, made practical by changes
in hardware implementation technologies, design requirements, and the power
of modern computers and workstations. However, today's researchers are cer-
tainly adding their share of new design techniques and algorithms to the broad
body of knowledge already assembled. A significant portion of the overall chal-
lenge of making high-level design automation practical involves sorting through
the existing collection of techniques and finding the right combination of meth-
ods and tools for a particular problem domain.
xu The Synthesis Approach to Digital System Design

I am very pleased that the many talented contributors to this book have
taken the time to document this collection of state-of-the-art techniques and
algorithms used in high-level description, synthesis and verification, and have
presented them in a way that new students in the field will find them under-
standable on their own as well as in the context of the CALLAS design system.
By using a complete, high-level design system as a vehicle for the text, the
authors have captured a number of the essential aspects of high-level design
methods as well as the basic algorithms and data structures that support them.
The text is an excellent starting point for the developers of new high-level de-
sign aids and for potential users of such systems as well.
A. Richard Newton
Berkeley, California
October, 1991
Acknowledgements

Many discussions must precede the development of a book like this. While
the contributors mentioned throughout this book have played a major part in
its writing, their many other colleagues in our department have been closely
involved as well. Especially, we would like to acknowledge the contributions of
those colleagues who are directly involved in synthesis, verification, hardware-
description languages, and testing in the Systems Design Automation Group
in Corporate Research and Development of Siemens AG.
But in addition to those colleagues from Siemens, we would like to acknowl-
edge the contributions made by one other person in particular. A. Richard
Newton was involved in the development of this book throughout all stages of
its evolvement. He participated in the many discussions on the taxonomy of
synthesis, he influenced our work in the various fields of system design, and he
reviewed most of the chapters in this book. All contributors appreciated his
valuable advice.
Special thanks go to the following people for their help in certain chap-
ters of this book: To Birgit Lutter for her efforts in helping with the figures in
Chapter 1i to Wendell Baker for helpful discussions and suggestions concerning
readability and contents of Chapter 6; to Franz Rammig for his really quick re-
sponse when we asked him to write Chapter 9, and to Michael Hohenbichler for
his help in editing this chapter. All of us appreciated the suggestions of Joyce
McLean regarding the correct use of English language. Certainly everybody
relied on one of the authors, Wolfgang Glunz, to prepare the camera-ready copy
of the book. Special thanks go to Carl Harris for his patience when we delayed
the date for the final manuscript month after month and to Egon Horbst for his
understanding when for some time everybody seemed to be engaged exclusively
with this book.
Our final thanks go to our families who supported .us while we were working
through nights and early mornings.
Petra Michel
0ctober, 1991
THE SYNTHESIS APPROACH TO
DIGITAL SYSTEM DESIGN