Lecture 5:

Power

1. Power and Energy

2. Dynamic Power
3. Static Power
4. Low Power Techniques
 1. Power and Energy
 Power is drawn from a voltage source attached to
the VDD pin(s) of a chip.

 Instantaneous Power: P(t ) = I (t )V (t )

T
 Energy: E = ∫ P(t )dt
0
T
 Average Power: E 1
Pavg= = ∫
T T 0
P(t )dt

7: Power CMOS VLSI Design 4th Ed. 2

 Power in Circuit Elements
PVDD ( t ) = I DD ( t ) VDD

VR2 ( t )
P
=R ( t ) = I R (t ) R
2

∞ ∞
dV
EC I ( t )V ( t ) dt ∫ C V ( t ) dt
∫0= 0
dt
VC

∫ V ( t )dV
C=
0
1
2 CVC2

7: Power CMOS VLSI Design 4th Ed. 3

 2. Dynamic Power
Charging a Capacitor
 When the gate output rises
– Energy stored in capacitor is
2
EC = 12 CLVDD
– But energy drawn from the supply is
∞ ∞
dV
=EVDD I ( t )VDD dt
∫= ∫ CL VDD dt
0 0
dt
VDD

LVDD ∫ dV
2
= C= CLVDD
0
– Half the energy from VDD is dissipated in the
pMOS transistor as heat, other half stored in
capacitor
 When the gate output falls
– Energy in capacitor is dumped to GND
– Dissipated as heat in the nMOS transistor

7: Power CMOS VLSI Design 4th Ed. 4

 Sources of Power Dissipation

Dynamic Power Dissipation

Charging and discharging of load capacitances
“Short-circuit” current while both p- and n-MOS networks are
partially on

Static Dissipation
Subthreshold leakage (through OFF transistors)
Gate leakage through gate dielectric
Junction leakage from source/drain diffusion
Contention current in ratioed circuits

ECE Department, University of Texas at Austin Lecture 18. Design for Low Power
 Switching Waveforms
 Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz

7: Power CMOS VLSI Design 4th Ed. 6

 Switching Power
T
1
Pswitching = ∫ iDD (t )VDD dt
T 0
T
VDD
=
T 0∫ iDD (t )dt

VDD
= [Tfsw CVDD ] VDD
T iDD(t)
fsw

= CVDD 2 fsw
C

7: Power CMOS VLSI Design 4th Ed. 7

 Activity Factor
 Suppose the system clock frequency = f
 Let fsw = αf, where α = activity factor
– If the signal is a clock, α = 1
– If the signal switches once per cycle, α = ½

 Dynamic power:
Pswitching = α CVDD 2 f

7: Power CMOS VLSI Design 4th Ed. 8

Lowering Dynamic Power
Capacitance: Supply voltage:
Function of fan-out, Has been dropping with
wire length, transistor successive generations
sizes

Pdyn = CL VDD2 P0→1 f

Activity factor: Clock frequency:

How often, on average, do Increasing…
wires switch?

CMOS VLSI Design 4th Ed.

 Short Circuit Current
 When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once
 Leads to a blip of “short circuit” current.
 < 10% of dynamic power if rise/fall times are
comparable for input and output
 We will generally ignore this component

7: Power CMOS VLSI Design 4th Ed. 10

Power Dissipation Sources
 Ptotal = Pdynamic + Pstatic
 Dynamic power: Pdynamic = Pswitching + Pshortcircuit
– Switching load capacitances
– Short-circuit current
 Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD
– Subthreshold leakage
– Gate leakage
– Junction leakage
– Contention current

7: Power CMOS VLSI Design 4th Ed. 11

CMOS Energy & Power Equations

E = CL VDD2 P0→1 + tsc VDD Ipeak P0/1→1/0 + VDD Ileak

f = P * fclock

P = CL VDD2 f + tscVDD Ipeak f + VDD Ileak

Dynamic power Short-circuit Leakage power

(~90% today and power (~2% today and
decreasing (~8% today and increasing)
relatively) decreasing
absolutely)

CSE477 L12&13 Low Power.12 Irwin&Vijay, PSU, 2003

 Power and Energy Design Space

Constant Variable
Throughput/Latency Throughput/Latency
Energy Design Time Non-active Modules Run Time
Logic design
DFS, DVS
Active Reduced Vdd
Clock Gating (Dynamic Freq,
(Dynamic) TSizing Voltage
Scaling)
Multi-Vdd
Sleep Transistors
Multi-VT
Leakage Multi-Vdd
Stack effect Variable VT
(Standby) Variable VT
Pin ordering
Input control

CSE477 L12&13 Low Power.13 Irwin&Vijay, PSU, 2003

Estimate dynamic power
 1 billion transistor chip
– 50M logic transistors
• Average width: 12 λ
• Activity factor = 0.1
– 950M memory transistors
• Average width: 4 λ
• Activity factor = 0.02
– 1.0 V 65 nm process
– C = 1 fF/µm (gate) + 0.8 fF/µm (diffusion)
 Estimate dynamic power consumption @ 1 GHz.
Neglect wire capacitance and short-circuit current.

7: Power CMOS VLSI Design 4th Ed. 14

 Solution
(
Clogic = 50 × 10 6
) (12λ )( 0.025µ m / λ )(1.8 fF / µ m ) =
27 nF

( 950 ×106 ) ( 4λ )( 0.025µ m / λ )(1.8 fF / µ m ) =

Cmem = 171 nF
0.1Clogic + 0.02Cmem  (1.0 ) (1.0 GHz ) =
2
Pdynamic = 6.1 W

7: Power CMOS VLSI Design 4th Ed. 15

 Dynamic Power Reduction

P
 switching = α CV 2
DD f

 Try to minimize:
– Activity factor
– Capacitance
– Supply voltage
– Frequency

7: Power CMOS VLSI Design 4th Ed. 16

 Activity Factor Estimation
 Let Pi = Prob(node i = 1)
– Pi = 1-Pi
 αi = Pi * Pi
 Completely random data has P = 0.5 and α = 0.25
 Data is often not completely random
– e.g. upper bits of 64-bit words representing bank
account balances are usually 0
 Data propagating through ANDs and ORs has lower
activity factor
– Depends on design, but typically α ≈ 0.1

7: Power CMOS VLSI Design 4th Ed. 17

 Dynamic Power Consumption is Data Dependent
 Switching activity, P0→1, has two components
 A static component – function of the logic topology
 A dynamic component – function of the timing behavior (glitching)

Static transition probability

P0→1 = Pout=0 x Pout=1
2-input NOR Gate
= P0 x (1-P0)
A B Out
0 0 1
With input signal probabilities
0 1 0
PA=1 = 1/2
1 0 0 PB=1 = 1/2
1 1 0
NOR static transition probability
= 3/4 x 1/4 = 3/16
CSE477 L12&13 Low Power.18 Irwin&Vijay, PSU, 2003
 NOR Gate Transition Probabilities
 Switching activity is a strong function of the input signal
statistics
 PA and PB are the probabilities that inputs A and B are one

0
A B
CL PA
1 0 1
PB

P0→1 = P0 x P1 = (1-(1-PA)(1-PB)) (1-PA)(1-PB)

CSE477 L12&13 Low Power.19 Irwin&Vijay, PSU, 2003

 Switching Probability

7: Power CMOS VLSI Design 4th Ed. 20

 Example
 A 4-input AND is built out of two levels of gates
 Estimate the activity factor at each node if the inputs
have P = 0.5

7: Power CMOS VLSI Design 4th Ed. 21

 Transition Probabilities for Some Basic Gates

P0→1 = Pout=0 x Pout=1

NOR (1 - (1 - PA)(1 - PB)) x (1 - PA)(1 - PB)
OR (1 - PA)(1 - PB) x (1 - (1 - PA)(1 - PB))
NAND PAPB x (1 - PAPB)
AND (1 - PAPB) x PAPB
XOR (1 - (PA + PB- 2PAPB)) x (PA + PB- 2PAPB)
X
0.5 A
Z
0.5 B

For X: P0→1 = P0 x P1 = (1-PA) PA

= 0.5 x 0.5 = 0.25
For Z: P0→1 = P0 x P1 = (1-PXPB) PXPB
= (1 – (0.5 x 0.5)) x (0.5 x 0.5) = 3/16
CSE477 L12&13 Low Power.23 Irwin&Vijay, PSU, 2003
 Example
 Determine the activity factors at each node in the
circuit assuming the input probabilities
PA = PB = PC = PD = 0.5.

7: Power CMOS VLSI Design 4th Ed. 24

 Example
 Determine the activity factors at each node in the
circuit assuming the input probabilities
PA = PB = PC = PD = 0.5.

7: Power CMOS VLSI Design 4th Ed. 25

 Inter-signal Correlations
 Determining switching activity is complicated by the fact
that signals exhibit correlation in space and time
 reconvergent fan-out

(1-0.5)(1-0.5)x(1-(1-0.5)(1-0.5)) = 3/16
0.5 A
X
0.5 B
Z

(1- 3/16 x 0.5) x (3/16 x 0.5) = 0.085

Reconvergent

P(Z=1) = P(B=1) & P(A=1 | B=1)

 Have to use conditional probabilities

CSE477 L12&13 Low Power.26 Irwin&Vijay, PSU, 2003
 Logic Restructuring
 Logic restructuring: changing the topology of a logic
network to reduce transitions
AND: P0→1 = P0 x P1 = (1 - PAPB) x PAPB
3/16
0.5 A Y
0.5 (1-0.25)*0.25 = 3/16
A W 7/64 0.5 B 15/256
B X F
15/256 0.5
0.5 C C
0.5 D F
0.5 0.5 D Z
3/16

Chain implementation has a lower overall switching activity

than the tree implementation for random inputs
Ignores glitching effects

CSE477 L12&13 Low Power.27 Irwin&Vijay, PSU, 2003

 Input Ordering

(1-0.5x0.2)x(0.5x0.2)=0.09 (1-0.2x0.1)x(0.2x0.1)=0.0196
0.5 0.2
A B X
X
B C
F 0.1 A F
0.2 C
0.1 0.5

Which is better wrt transition probabilities?

Beneficial to postpone the introduction of signals with a

high transition rate (signals with signal probability
close to 0.5)

CSE477 L12&13 Low Power.29 Irwin&Vijay, PSU, 2003

 Glitching in Static CMOS Networks
 Gates have a nonzero propagation delay resulting in
spurious transitions or glitches (dynamic hazards)
 glitch: node exhibits multiple transitions in a single cycle before
settling to the correct logic value

A X
B
C Z

ABC 101 000

Unit Delay
CSE477 L12&13 Low Power.31 Irwin&Vijay, PSU, 2003
 Glitching in an RCA

Cin

S15 S14 S2 S1 S0

CSE477 L12&13 Low Power.32 Irwin&Vijay, PSU, 2003

 Balanced Delay Paths to Reduce Glitching
 Glitching is due to a mismatch in the path lengths in
the logic network; if all input signals of a gate change
simultaneously, no glitching occurs

0 0
0 F1 1 0 F1 1
0 F2 2
F3
0 F3 0
0 F2 1

So equalize the lengths of timing paths through logic

CSE477 L12&13 Low Power.33 Irwin&Vijay, PSU, 2003

 3. Static Power
 Static power is consumed even when chip is
quiescent.
– Leakage draws power from nominally OFF
devices
– Ratioed circuits burn power in fight between ON
transistors

7: Power CMOS VLSI Design 4th Ed. 34

 Leakage (Static) Power Consumption

VDD Ileakage

Vout
Drain junction
leakage

Gate leakage Subthreshold current

Sub-threshold current is the dominant factor.

All increase exponentially with temperature!

CSE477 L12&13 Low Power.35 Irwin&Vijay, PSU, 2003

 Leakage Current Mechanisms

I1 p-n junction reverse

bias current (drain
I7 I8 junction)
Polysilicon I2 weak inversion
Gate oxide
Gate (subthreshold current)
I3 DIBL
Source Drain
I4 GIDL
n+ I I I n+
2 3 6
I1 I5 punchthrough
I5
I4
p substrate I6 narrow width effect
Bulk (Body)
I7 gate oxide tunneling
(gate leakage)
I8 hot carrier injection

CSE477 L12&13 Low Power.36 Irwin&Vijay, PSU, 2003

 Static Power Example
 Revisit power estimation for 1 billion transistor chip
 Estimate static power consumption
– Subthreshold leakage
• Normal Vt: 100 nA/µm
• High Vt: 10 nA/µm
• High Vt used in all memories and in 95% of
logic gates
– Gate leakage 5 nA/µm
– Junction leakage negligible

7: Power CMOS VLSI Design 4th Ed. 37

 Solution

( 50 ×106 ) (12λ )( 0.025µ m / λ )( 0.05) =

Wnormal-Vt = 0.75 ×106 µ m

Whigh-Vt = ( 50 ×106 ) (12λ )( 0.95 ) + ( 950 ×106 ) ( 4λ )  ( 0.025µ m / λ ) = 109.25 ×106 µ m

I sub = Wnormal-Vt ×100 nA/µ m+Whigh-Vt ×10 nA/µ m  / 2 =

584 mA

( )
I gate=  Wnormal-Vt + Whigh-Vt × 5 nA/µ m  / 2= 275 mA
 
Pstatic = ( 584 mA + 275 mA )(1.0 V ) = 859 mW

7: Power CMOS VLSI Design 4th Ed. 38

 Subthreshold Leakage
 For Vds > 50 mV Typical values in 65 nm
Vgs +η (Vds −VDD ) − kγ Vsb Ioff = 100 nA/µm @ Vt = 0.3 V
I sub ≈ I off 10 S Ioff = 10 nA/µm @ Vt = 0.4 V
Ioff = 1 nA/µm @ Vt = 0.5 V
η = 0.1
 Ioff = leakage at Vgs = 0, Vds = VDD
kγ = 0.1
S = 100 mV/decade

7: Power CMOS VLSI Design 4th Ed. 39

 Stack Effect
 Series OFF transistors have less leakage
– Vx > 0, so N2 has negative Vgs
η (Vx −VDD ) −Vx +η ( (VDD −Vx ) −VDD ) − kγ Vx

= off 10
I sub I= I off 10
S S
    
N2 N1

ηVDD
Vx =
1 + 2η + kγ
 1+η + kγ 
−ηVDD  
 1+ 2η + kγ  −ηVDD
 
=I sub I off 10 S
≈ I off 10 S

– Leakage through 2-stack reduces ~10x

– Leakage through 3-stack reduces further

7: Power CMOS VLSI Design 4th Ed. 40

 Leakage Control
 Leakage and delay trade off
– Aim for low leakage in sleep and low delay in
active mode
 To reduce leakage:
– Increase Vt: multiple Vt
• Use low Vt only in critical circuits
– Increase Vs: stack effect
• Input vector control in sleep
– Decrease Vb
• Reverse body bias in sleep
• Or forward body bias in active mode

7: Power CMOS VLSI Design 4th Ed. 41

 Gate Leakage
 Extremely strong function of tox and Vgs
– Negligible for older processes
– Approaches subthreshold leakage at 65 nm and
below in some processes
 An order of magnitude less for pMOS than nMOS
 Control leakage in the process using tox > 10.5 Å
– High-k gate dielectrics help
– Some processes provide multiple tox
• e.g. thicker oxide for 3.3 V I/O transistors
 Control leakage in circuits by limiting VDD

7: Power CMOS VLSI Design 4th Ed. 42

 NAND3 Leakage Example
 100 nm process
Ign = 6.3 nA Igp = 0
Ioffn = 5.63 nA Ioffp = 9.3 nA

Data from [Lee03]

7: Power CMOS VLSI Design 4th Ed. 43

 Junction Leakage
 From reverse-biased p-n junctions
– Between diffusion and substrate or well
 Ordinary diode leakage is negligible
 Band-to-band tunneling (BTBT) can be significant
– Especially in high-Vt transistors where other
leakage is small
– Worst at Vdb = VDD
 Gate-induced drain leakage (GIDL) exacerbates
– Worst for Vgd = -VDD (or more negative)

7: Power CMOS VLSI Design 4th Ed. 44

 Power and Energy Design Space

Constant Variable
Throughput/Latency Throughput/Latency
Energy Design Time Non-active Modules Run Time
Logic design
DFS, DVS
Active Reduced Vdd
Clock Gating (Dynamic Freq,
(Dynamic) TSizing Voltage
Scaling)
Multi-Vdd
Sleep Transistors
Multi-VT
Leakage Multi-Vdd
Stack effect Variable VT
(Standby) Variable VT
Pin ordering
Input control

CSE477 L12&13 Low Power.45 Irwin&Vijay, PSU, 2003

4. Low Power Methodology
 Resonant circuits: reduce switching power consumption
 Clock gating: turn off the clock to registers in unused
blocks to reduce the activity
 Reduce capacitance: wire/gate capacitance
 Dynamic Voltage Scaling: Adjust VDD and f according
to workload
 Power gating: Turn OFF power to blocks when they are
idle to save leakage

7: Power CMOS VLSI Design 4th Ed. 46

 Resonant Circuits
 Letting energy slosh back and forth between storage
elements such as capacitors and inductors rather
than dumping the energy to ground.
 The technique is best suited to applications such as
clocks that operate at a constant frequency.

7: Power CMOS VLSI Design 4th Ed. 47

 Clock Gating
 The best way to reduce the activity is to turn off the
clock to registers in unused blocks
– Saves clock activity (α = 1)
– Eliminates all switching activity in the block
– Requires determining if block will be used

7: Power CMOS VLSI Design 4th Ed. 48

 Capacitance
 Gate capacitance
– Fewer stages of logic
– Small gate sizes
 Wire capacitance
– Good floorplanning to keep communicating
blocks close to each other
– Drive long wires with inverters or buffers rather
than complex gates

7: Power CMOS VLSI Design 4th Ed. 49

 Voltage / Frequency
 Run each block at the lowest possible voltage and
frequency that meets performance requirements
 Voltage Domains
– Provide separate supplies to different blocks
– Level converters required when crossing
from low to high VDD domains

 Dynamic Voltage Scaling

– Adjust VDD and f according to
workload

7: Power CMOS VLSI Design 4th Ed. 50

 Power Gating
 Turn OFF power to blocks when they are idle to
save leakage
– Use virtual VDD (VDDV)
– Gate outputs to prevent
invalid logic levels to next block

 Voltage drop across sleep transistor degrades

performance during normal operation
– Size the transistor wide enough to minimize
impact
 Switching wide sleep transistor costs dynamic power
– Only justified when circuit sleeps long enough
7: Power CMOS VLSI Design 4th Ed. 51
 Low Power Design
 Reduce dynamic power
– α: clock gating, sleep mode
– C: small transistors (esp. on clock), short wires
– VDD: lowest suitable voltage
– f: lowest suitable frequency
 Reduce static power
– Selectively use ratioed circuits
– Selectively use low Vt devices
– Leakage reduction: stacked devices, body bias,
low temperature, …

D. Z. Pan CMOS VLSI Design 4th Ed.

Low Power Design Techniques

Algorithm

Architecture

Logic/circuit

Technology/circuit

 Need combination of techniques at all levels

D. Z. Pan CMOS VLSI Design 4th Ed.

 Review
1. What is dynamic power?
2. What is static power?
3. Why does switching probability affect to dynamic power?
4. Describe some low power techniques
5. Describe resonant circuits
6. What are difference between clock gating and power gating
7. Calculate activity factors of the following circuits:
(PA = PB = PC = PD = 0.5)

7: Power CMOS VLSI Design 4th Ed. 54