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Vlsi 1096

The document provides an overview of Verilog HDL design, covering topics such as VLSI design methodology, modeling styles, and levels of abstraction. It explains the behavioral and structural aspects of hardware modeling, the declaration of Verilog modules, and the process of instantiation. Additionally, it discusses testbench techniques and the role of ports in Verilog modules.

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0% found this document useful (0 votes)
3 views18 pages

Vlsi 1096

The document provides an overview of Verilog HDL design, covering topics such as VLSI design methodology, modeling styles, and levels of abstraction. It explains the behavioral and structural aspects of hardware modeling, the declaration of Verilog modules, and the process of instantiation. Additionally, it discusses testbench techniques and the role of ports in Verilog modules.

Uploaded by

adamasabj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
You are on page 1/ 18

Verilog HDL Design [Session-1]

• Introduction
• VLSI Design Methodology
• Modeling Styles
• Levels Of Abstraction
• Verilog Module Declaration
Verilog® HDL • Elements of Verilog Module
• Instantiation
• Testbench and Simulation Technique
• Ports and Signal Pins
• Reserved Keywords

Verilog HDL IIT Guwahati 1


Introduction

Hardware Modeling

There are two fundamental aspects of any piece of hardware:


Behavioral
The behavioral aspects tells us about the behavior of hardware. What is its
functionality and speed (without bothering about the constructional and operational
details).

Structural
The structural aspect tells us about the hardware construction. The design is
comprised of which parts and how the design is constructed from these parts i.e. how
they have been interconnected.

Verilog HDL IIT Guwahati 2


Introduction

Of course, complete information on the hardware requires a combination of both


the behavioral and structural aspects. However, in many practical situations, we
may need to focus only on a single aspect. This is called abstraction in designing.

Any manner of maintaining/providing/exchanging information on a piece of


hardware, therefore must address both these aspects individually or in
combination.

The hardware description language Verilog has been developed to provide a


means of describing, validating, maintaining and exchanging design information on
complex digital VLSI chips across several levels of design abstractions used in
design process.

Verilog HDL IIT Guwahati 3


VLSI Design Methodology

▪ Top-Down Design:
Realizing the desired behavior by partitioning Top-Level Block
it into an interconnection of simpler sub-
behaviors. The designer controls the partitioning
and specifies the sub-behavior of each partition.
Sub-Block1 / Sub-Block 2 /
macro cell 1 macro cell 2
▪ Bottom-Up Design
Realizing the desired behavior by
interconnecting available parts
components. Leaf Leaf Leaf Leaf
cell cell cell cell

▪ Mixed Top-Down and Bottom-Up Design


Complex
It is a blend of top-down and bottom-up System Level
methodology.

Silicon (Switch) Mixing In


Level Same Model

Verilog HDL IIT Guwahati 4


Modeling Styles
Verilog is both, behavioral and structural language. Designs in Verilog can be described at all the four
levels of abstraction depending on needs of design.
Behavioral Level: -
Used to model behavior of design without concern for the hardware implementation details. Designing at
this level is very similar to C programming.
Dataflow Level [RTL]: -
Module is specified by specifying the data flow. The designer is aware of how the data flows between
registers.
Gate Level: -
Module is implemented in terms of logic gates & interconnections between them. Design at this level is
similar to describing design in terms of gate level logical diagram.
Switch Level: -
lowest level of abstraction provided by Verilog. Module can be implemented in terms of switches, storage
nodes & interconnection between them.

Verilog HDL IIT Guwahati 5


Levels Of Abstraction

Switch Level
(Synthesis Only)
Custom ASIC
Technology
Gate Level Independent
(Synthesis Only)
ASIC/PLD
Technology
Specific
RTL Level (Synthesis
Only) ASIC/PLD

Behavioral Level
ASIC/PLD

Intense Definition Level Of Abstraction Very


Abstract

Verilog HDL IIT Guwahati 6


Top Level Of Abstraction

Lower Level Of
Abstraction More Abstract
Level

Analysis Synthesis

Less Abstract
Level
Next Level Of
Abstraction

Verilog HDL IIT Guwahati 7


Verilog Module Declaration
In Verilog, a module models a piece of digital hardware. A module has a name, a port list, description of type of
each port. The description can either be a behavior description, or a structural description or a mixed
behavioral – structural description of hardware as well.

module module_name(port_list);
{module item}
endmodule

module D_FF(q,clock,data); //module is keyword, D_FF is a identifier


output q; //From here it is a module item declaration zone
reg q; //where ports are descriibed with their identifiers
input clock,data; //and direction (mode) of the ports
initial
q = 0; //here starts the module item which describes
always @(negedge clock) //h/w behavior always and endmodule are key words
#10 q = data;
endmodule

Verilog HDL IIT Guwahati 8


Elements of Verilog Module

module MY_MODULE
Port declaration Initial
Module Parameter declaration
Always
Type declaration
-Procedural assignment
Event declaration
-Non-blocking assignment
Verilog Continuous assignment
-Procedural continous assignment
HDL Primitive declaration
Program -Loops(for, repeat, while, forever)
Module instantiation
Specify block -Flow control (if, conditional,
case, wait, disable)
Task declaration
-system task and functions
Function declaration
-Event trigger
End Module Behavioral Statements
-Task calls
-Fucntion calls
endmodule
Verilog HDL IIT Guwahati 9
Gate Level Half Adder

// Adder Module
module half_adder(sum,carry,A,B);
output sum;
output carry;
input A, B;
xor my_xor(sum,A,B);
and my_and(carry,A,B);
endmodule

Verilog HDL IIT Guwahati 10


Dataflow Level Half Adder

// Adder Module
module half_adder(sum,carry,A,B);
output sum;
output carry;
input A, B;
assign sum = (~A&B) + (A&~B);
assign carry = A&B;
endmodule

Verilog HDL IIT Guwahati 11


Behavioral Level Half Adder

// Adder Module
module half_adder(sum,carry,A,B);
output sum; reg sum;
output carry; reg carry;
input A, B;
always @(A or B)
begin
{carry, sum} = A + B;
end
endmodule

Verilog HDL IIT Guwahati 12


Instantiation

A module provides a template from which you can create actual objects. When a module is invoked,
Verilog creates a unique object from the template. Each object has its own name, variables,
parameters, and I/O interface. The process of creating objects from a module template is called
instantiation, and the objects are called instances.

module D_FF(d, q, clk, reset);


output q;
input clk, reset; module T_FF(q, clk, reset);
input d; output q;
always @(posedge clk) input clk, reset;
if (!reset) wire d;
q <= 0; D_FF dff0(q, d, clk, reset); // Instantiate D_FF. Call it dff0.
else not n1(d, q); // not gate is a Verilog primitive. Explained later.
q <= d endmodule
end
endmodule

Verilog HDL IIT Guwahati 13


Testbench and Simulation Technique
The functionality of the design block can be tested by applying stimulus and checking results. We call such a
block the stimulus block.

Two styles of stimulus application are possible: -


▪ Stimulus Block Instantiates Design Block

Verilog HDL IIT Guwahati 14


Testbench and Simulation Technique

▪ Stimulus and Design Blocks Instantiated in a Dummy Top-Level Module

Verilog HDL IIT Guwahati 15


Ports in Verilog
▪ Provides an interface by which a module can communicate with its environment
▪ If output port has to hold a value, then it must be declared as reg
▪ All port declarations are implicitly declared as wire
▪ Input/output ports can be declared as reg
▪ When modules are instantiated within another
▪ Input must always be a wire (net), it can be externally connected to a reg or net
▪ Output can be net or reg, it must externally connect to a net
▪ Inout must be a net, it must externally connect to a net

Verilog HDL IIT Guwahati 16


Ports in Verilog
▪ port
▪ input, output
▪ inout – bi-directional (can drive, can be driven)

Verilog HDL IIT Guwahati 17


Reserved Keywords

Verilog HDL IIT Guwahati


IIT Guwahati 18

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