Vlsi 1096
Vlsi 1096
• Introduction
• VLSI Design Methodology
• Modeling Styles
• Levels Of Abstraction
• Verilog Module Declaration
Verilog® HDL • Elements of Verilog Module
• Instantiation
• Testbench and Simulation Technique
• Ports and Signal Pins
• Reserved Keywords
Hardware Modeling
Structural
The structural aspect tells us about the hardware construction. The design is
comprised of which parts and how the design is constructed from these parts i.e. how
they have been interconnected.
▪ Top-Down Design:
Realizing the desired behavior by partitioning Top-Level Block
it into an interconnection of simpler sub-
behaviors. The designer controls the partitioning
and specifies the sub-behavior of each partition.
Sub-Block1 / Sub-Block 2 /
macro cell 1 macro cell 2
▪ Bottom-Up Design
Realizing the desired behavior by
interconnecting available parts
components. Leaf Leaf Leaf Leaf
cell cell cell cell
Switch Level
(Synthesis Only)
Custom ASIC
Technology
Gate Level Independent
(Synthesis Only)
ASIC/PLD
Technology
Specific
RTL Level (Synthesis
Only) ASIC/PLD
Behavioral Level
ASIC/PLD
Lower Level Of
Abstraction More Abstract
Level
Analysis Synthesis
Less Abstract
Level
Next Level Of
Abstraction
module module_name(port_list);
{module item}
endmodule
module MY_MODULE
Port declaration Initial
Module Parameter declaration
Always
Type declaration
-Procedural assignment
Event declaration
-Non-blocking assignment
Verilog Continuous assignment
-Procedural continous assignment
HDL Primitive declaration
Program -Loops(for, repeat, while, forever)
Module instantiation
Specify block -Flow control (if, conditional,
case, wait, disable)
Task declaration
-system task and functions
Function declaration
-Event trigger
End Module Behavioral Statements
-Task calls
-Fucntion calls
endmodule
Verilog HDL IIT Guwahati 9
Gate Level Half Adder
// Adder Module
module half_adder(sum,carry,A,B);
output sum;
output carry;
input A, B;
xor my_xor(sum,A,B);
and my_and(carry,A,B);
endmodule
// Adder Module
module half_adder(sum,carry,A,B);
output sum;
output carry;
input A, B;
assign sum = (~A&B) + (A&~B);
assign carry = A&B;
endmodule
// Adder Module
module half_adder(sum,carry,A,B);
output sum; reg sum;
output carry; reg carry;
input A, B;
always @(A or B)
begin
{carry, sum} = A + B;
end
endmodule
A module provides a template from which you can create actual objects. When a module is invoked,
Verilog creates a unique object from the template. Each object has its own name, variables,
parameters, and I/O interface. The process of creating objects from a module template is called
instantiation, and the objects are called instances.