Outline

Part 2 (Behavior Verilog for design)

• Finite State Machine Design
• Behavior level modeling
• Tools and hardware specific
– Simulator and race conditions
• SystemVerilog for design
• Verilog Modeling Style for Synthesis
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• Gotchas

1
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 Digital Circuits and Systems
Lecture 2-2 Model Finite State Machine
Tian Sheuan Chang
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有了記憶，人生變彩色

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 SEQUENTIAL CIRCUIT
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 Sequential logic has state

Output = f(input)

Combinational Logic
Sequential Logic
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*without storage elements, the

CL circuits with feedback may
Become unstable! => oscillator

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 D Flip-Flop
• Input: D
• Output: Q
• Clock

• Q outputs a steady value

• changes Q to be D at clock edge
• Flip-flop stores state
• Allows sequential circuits to iterate
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*D-type FF is often exploited

as “register” due to simple connectivity; 一般數位電路不用latch
Latch is exploited as well but level sensitive; Why?
thus only half period is available.
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 Timing Diagram of Sequential Circuit
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輸入變，輸出就跟著變

輸入變，輸出等到
Clock edge 才變
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 CODING STYLE FOR FSM
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Source: C. Cummings, Synthesizable Finite State Machine Design Techniques

Using the New SystemVerilog 3.1 Enhancements
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 Moore v.s. Mealy
• Mealy and Moore FSM
– A Moore FSM is a state machine where the outputs are only a function
of the present state.
– A Mealy FSM is a state machine where one or more of the outputs is a
function of the present state and one or more of the inputs.
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 FSM Implementation: Moore/Mealy trade-off
• Remember that the difference is in the output:
– Moore outputs are based on state only
– Mealy outputs are based on state and input
– Therefore, Mealy outputs generally occur one cycle earlier than a Moore
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• Compared to a Moore FSM, a Mealy FSM might...

– Be more difficult to conceptualize and design
– Have fewer states

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 Asynchronous Mealy
• Registered output to ease logic synthesis
Logic will not be minimized across module boundaries
unless specified in synthesis tools
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 FSM: Simple Moore Machine Example
• 4-State Moore State Machine
!rst_n go=0
• Asynchronous low-true reset IDLE
rst_n rd=0
ds=0
go=1
• Clock signal name
clk
DONE READ
rd=0 rd=1
• Two inputs ds=1 ds=0
go, ws (wait-state)
ws =0
DLY
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• Two Moore outputs rd=1

rd, ds (read & done-strobe) ds=0 ws=1
(rd=0 & ds=0 on reset)

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 Moore State Machine Two Always Blocks
• Next state and output logic use one always_comb block
• Present state FF use always_ff
Next State Clocked Present Output combinational
combinational logic State logic logic

inputs
combinational sequential combinational
logic logic logic
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next state outputs

Next Present
Output
state State State
Logic
Logic FF's

clock

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 Two always block
always_combbegin //next state and output logic
next= 'bx;
rd =1'b0;
ds =1'b0;
case(state)
module fsm_cc1_2 IDLE: if (go) next = READ;
(output logic rd, ds, else next = IDLE;
input go, ws, clk, rst_n); READ : begin
//binary encoding rd = 1'b1;
parameter IDLE = 2'b00, next = DLY;
READ = 2'b01, end
DLY = 2'b11, DLY : begin
DONE = 2'b10; rd = 1'b1;
if (!ws) next = DONE;
logic [1:0] state, next; else next = READ;
end
always_ff@(posedge clk, negedge rst_n)
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DONE : begin
if (!rst_n) state <= IDLE; ds = 1'b1;
else state <= next; next = IDLE;
end
endcase
end
endmodule
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 1. State definition
module fsm_cc1_2
(output logic rd, ds,
input go, ws, clk, rst_n);

parameter IDLE = 2'b00,

READ = 2'b01, State assignment? Synopsys FSM compiler can help
DLY = 2'b11,
DONE = 2'b10;

logic [1:0] state, next;

always_ff@(posedge clk, negedge rst_n)

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if (!rst_n) state <= IDLE;

else state <= next;

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 Why not use define? It’s a global varaible
`define IDLE 3'b000
`define B1 3'b001 `define IDLE 2'b00
"Re-definition" `define READ 2'b01
`define B2 3'b010
warnings! `define S2 2'b10
`define B3 3'b101
`define READ 3'b100
module fsm2 ( ... );
module fsm1 ( ... ); ...
Multiple FSMs with
... endmodule
the same state names Bad coding
endmodule style!!

IDLE IDLE
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READ B1

`define creates a
global definition
B3 B2 S2 READ

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 State definition: use parameter (local
variable)
module fsm1 ( ... ); module fsm2 ( ... );
... No state definition ...
parameter problems! parameter IDLE = 2'b00,
IDLE = 3'b000,
READ = 2'b01,
B1 = 3'b001,
S2 = 2'b10;
B2 = 3'b010, ...
Multiple FSMs with
B3 = 3'b101, endmodule
the same state names Good coding
READ = 3'b100;
... style!!
endmodule
IDLE IDLE
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READ B1

parameters create
local definitions
B3 B2 S2 READ

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 2. Present state DFF
module fsm_cc1_2
(output logic rd, ds,
input go, ws, clk, rst_n);

parameter IDLE = 2'b00,

READ = 2'b01,
DLY = 2'b11,
DONE = 2'b10;

logic [1:0] state, next; State variable

always_ff@(posedge clk, negedge rst_n)

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if (!rst_n) state <= IDLE; Remember to add reset state

else state <= next;

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 3. Next state/ always_comb begin //next state and output logic
next = 'bx;

output logic Use ’bx for logic min ds = 1'b0;

Default case rd = 1'b0;

case (state)
IDLE : if (go) next = READ;
else next = IDLE;
每個case item放不同state READ : begin
Test each state rd = 1'b1;
next = DLY;
end
DLY : begin
rd = 1'b1;
Test input conditions if (!ws) next = DONE;
else next = READ;
end
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DONE : begin
Output logic ds = 1'b1;
next = IDLE;
end
endcase
end
endmodule Assign next state output
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 Two Always Coding Styles
• One of the best Verilog coding
parameter [1:0]
IDLE=2'b00, BBUSY=2'b01,BFREE=2'b10;

styles reg [1:0] state, next;

• Code the FSM design using two

always @(posedge clk or negedge rst_n)
if (!rst_n) state <= IDLE;

always blocks,
else state <= next;

– One for the sequential state register

always @(state or in1 or in2) begin
next = 2'bx; out1 = 1'b0;

– One for the combinational next-state

case (state)
IDLE : if (in1) next = BBUSY;
and combinational output logic. else next = IDLE;
BBUSY: begin
out1 = 1'b1;
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if (in2) next = BBUSY;

else next = BFREE;
end
//...
endcase
end

Combinational logic 和sequential logic 分開

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 One Always Block FSM Style (Avoid This Style!)
• One of the most common FSM
parameter [1:0]
IDLE=2'b00, BBUSY=2'b01,BFREE=2'b10;

coding styles in use today

reg [1:0] state;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
– It is more verbose state <= IDLE;
out1 <= 1'b0;
– It is more confusing end
else begin
– It is more error prone (comparable state <= 2'bx; out1 <= 1'b0;

two always block coding style)

case (state)
IDLE : if (in1) begin
state <= BBUSY;
out1 <= 1'b1;
end
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else state <= IDLE;

BBUSY: if (in2) begin
state <= BBUSY;
out1 <= 1'b1;
end
else state <= BFREE;
endcase

Combinational logic 和sequential logic 放在一起

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 One Always Block FSM Style (Avoid This Style!)
parameter [1:0]
1. A declaration is made for state. IDLE=2'b00, BBUSY=2'b01,BFREE=2'b10;
Not for next. reg [1:0] state;
always @(posedge clk or negedge
1

2. The state assignments do not rst_n) if (!rst_n) begin

state <= IDLE;
correspond to the current state of out1 <= 1'b0;
end
the case statement, but the state else begin
state <= 2'bx; out1 <= 1'b0;
that case statement is case (state)
IDLE : if (in1) begin
transitioning to. state <= BBUSY; 2
out1 <= 1'b1;
end
else state <= IDLE;
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BBUSY: if (in2) begin

• This is error prone (but it does state <= BBUSY;
out1 <= 1'b1;
work if coded correctly). end
else state <= BFREE;
endcase
end

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 One Always Block FSM Style (Avoid This Style!)
3. There is just one sequential always parameter [1:0]
block, coded using nonblocking IDLE=2'b00, BBUSY=2'b01,BFREE=2'b10;
reg [1:0] state;
assignments. always @(posedge clk or negedge
rst_n) if (!rst_n) begin
4. All outputs will be registered state <= IDLE;
(unless the outputs are placed out1 <= 1'b0;
end
into a separate combinational else begin
always block or assigned using state <= 2'bx; out1 <= 1'b0;
case (state)
3
continuous assignments). IDLE : if (in1) begin
state <= BBUSY;
out1 <= 1'b1;
end
• No asynchronous Mealy outputs else state <= IDLE;
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BBUSY: if (in2) begin

can be generated from a single state <= BBUSY;
synchronous always block. out1 <= 1'b1; 4
end
else state <= BFREE;
endcase
end

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 TLDR
• Use two always or three always coding style
– Two always: one for state DFF, one for next state and output
– Three always: one for state DFF, one for next state, one for output
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 如何在DEBUSSY / VERDI顯示STATE名稱幫
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助DEBUG

http://www.cnblogs.com/oomusou/archive/2011/06/14/verdi_fsm_state.html N Y C U . E E , Hsinchu, Taiwan

 使用前，讀進*.fsdb檔後，FSM state信號，預設只會顯示
state encoding所代表的數值

若能顯示state名稱，相信可讀性更高，更方便debug
Tools –> Extract Interactive FSM…
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