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programmic logic

The document describes three types of programmable logic devices: PROM, PLA, and PAL. PROM consists of n-input lines and m-output lines, allowing for the selection of output words based on binary addresses, while PLA uses programmable AND and OR gates for more complex logic functions without full decoding. PAL features a fixed OR array with a programmable AND array, simplifying programming while maintaining functionality across multiple inputs and outputs.

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2 views

programmic logic

The document describes three types of programmable logic devices: PROM, PLA, and PAL. PROM consists of n-input lines and m-output lines, allowing for the selection of output words based on binary addresses, while PLA uses programmable AND and OR gates for more complex logic functions without full decoding. PAL features a fixed OR array with a programmable AND array, simplifying programming while maintaining functionality across multiple inputs and outputs.

Uploaded by

jsaravanann
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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PROM(Programmable Read Only Memory)

*It consists of n-input lines and output lines. ​

*Each combination of the input variable is called an address.

*Each bit combination that comes out of the output lines is called a word.

*The number of bits per word is equal to the number of output lines , m.

*The address specified in binary number denotes one of the minterms of n


variables.

*An output word can be selected by a unique address and since there are 2n
distinct address in PROM.

*Six input variables are decoded in 64 lines by means of 64 AND gates and 6
inverters.

*Output of the decoder represents one of the minterms of a function of six


variables.

*The PROM is a two level implementation In terms minterms form.

Combinational Logic Implementation using PROM


*We can realize that each output provides the sum of all the minterms of
n-input variables.
*Each PROM output can be made to represent the Boolean function of one
of the output variables in the combinational circuit.

*For an n-output, m-output combinational circuit, we need a 2nx m PROM.


PLA(Programmable Logic Array)
*For cases where the number of don’t care condition is excessive, it is more
economical to use a second
type of LSI component called a programmable Logic Array(PLA).

*A PLA is similar to a PLA in concept.

*It does not provide full decoding of the variable and does not generate the
minterms.

*PLA replaces decoder by group of AND gates.

*In PLA, both AND and OR gates are programmable.

*It consists of n-inputs, output buffer with m outputs, m product terms,


input and output buffers.

*The product terms constitute a group of m AND gates and the sum terms
constitute a group of m OR

Gates, called OR matrix.

*Fuses are inserted between all n-inputs and their complement values.

*Fuses are also provided between the outputs of the AND gates and the
inputs of the OR gates.
Input Buffer
*Input Buffers are provided in the PLA to limit loading of the sources.
*They also provide inverted and non-inverted form of inputs.

Output Buffer

*The driving capacity of PLA is increased by providing buffers at the output.

*They are usually TTL compatible.

*Output buffer may provide totem-pole, open collector or tri-state output.

Output through Flip-Flop


*The implementation of sequential circuits we need memory elements,
flip-flops and combinational circuitry.
*Some PLAs are provided with flip-flop at each output. Implementation of
Combinational Logic Circuit using
Programmable Logic Array(PLA)
*PLAs can be mask-programmable or field-programmable.
*A second type of PLA available is called a Field Programmable Logic Array
or FPLA.

Programmable Array Logic(PAL)

*PAL programmable array logic is a programmable logic


device with a fixed OR array and a

Programmable AND array.

*Only AND gates are programmable , the PAL is easier to


program.

*It has four inputs and four outputs.

*Each input Ahas buffer and an inverter gate.

*There are four sections.

*Each section has three programmable AND gates and one


fixed OR gate.

*Output section 1 is connected to a buffer-inverter gate and


then fed back into the inputs of the

AND gates , through fuses.

*PAL integrated circuit may have eight inputs , eight


outputs , and eight sections.

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