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Mod 4 - Serial Adder Using FSM

The document describes the design of a serial adder using a finite state machine (FSM) approach, detailing the state diagram and transitions based on the inputs A and B. It outlines the states S0, S1, S2, and S3, which correspond to different conditions of the inputs and the resulting outputs F and Cout. Additionally, it provides Verilog code for implementing the FSM, including state definitions, next state logic, and output logic.

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20 views

Mod 4 - Serial Adder Using FSM

The document describes the design of a serial adder using a finite state machine (FSM) approach, detailing the state diagram and transitions based on the inputs A and B. It outlines the states S0, S1, S2, and S3, which correspond to different conditions of the inputs and the resulting outputs F and Cout. Additionally, it provides Verilog code for implementing the FSM, including state definitions, next state logic, and output logic.

Uploaded by

synisterflare02
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Serial Adder

Using a Finite State Machine


Module 4 - FSM & Memory Modeling

Taken from: https://digilent.com/reference/learn/courses/digital-projects/serial-


adder/start?srsltid=AfmBOopemfwkyd014AaWmYcsd49H4mpmx1hnAzY6fMntN432k5ju3O8G
Serial Adder
• A serial adder is a circuit that performs binary addition bit by bit
(i.e., instead of presenting both operands at the inputs of an adder
at the same time, the operands are fed into the serial adder bit by
bit and it generates the answer on the fly).
• To design such a circuit, we are going to use the state diagram as
the mode of describing the behavior of the circuit and translate
the state diagram into Verilog code.
Step 1: Describe the Serial Adder
Using the State Diagram
Defining inputs & outputs
• We have two data inputs named A and B.
• Both of them are 1-bit wires.
• As with the adder we described in the arithmetic circuit, we have a
data output F and another output called Cout (Carry Out).
• We also need a clock signal (named clk here) to provide the
timing reference for both the inputs and the outputs and a reset
signal (named rst) to bring the circuit into initial state.
• Every state diagram starts from an initial state. So we will draw a
circle to represent the initial state and we will name it S0.
• When rst is asserted, the circuit should reset to this initial state
S0, and we will define that both outputs will be initialized to be 0,
as shown in Fig. 1 below.
• Now, we will try to see where we will go from the initial state when
inputs come.
• Let's consider the case when neither A or B are asserted. If A is 0, and B
is 0, the the result of the current bit will be 0 with no carry generated.
• And it is exactly the initial state. We just need to draw an arrow from S0
to S0 (self loop) and label it A’B’ as shown in Fig. 2 below.
• Now let's consider the case when one of the inputs (A, B) is asserted.
• The result of the current bit should be '1' with no carry out generated.
Circuits will certainly be in a different state than the initial state. So we
will create another state by drawing another circle and labeling it S1.
The condition that the circuit will go from S0 to S1 is that one of A and B
is '1'. We can draw an arrow from S0 to S1 and label it A⊕B
• When the circuit arrives at state S1, output F should be driven high and
Cout remains low. Thus, we label F=1 and Cout=0beside state S1. The
new state diagram is shown below in Fig. 3.
• Now, starting from initial state, we have one case left that we have
not yet considered—both A and B are asserted. In this case, the
output F is '0' and a carry will be generated. This is certainly
another state that is different from either S0 or S1. So we will need
to create another state and label it S2. The transition from S0 to S2
should be described as an arrow starting with S0 and ending at S2
with a label A⋅B as shown in Fig. 4 below.
• Now we have three states in the state diagram S0, S1, S2 and we
have considered all the transitions starting from S0.
• Let's start from state S1 and repeat the previous three steps. Fig.
5 shown below.
• We have covered all of the transitions starting from S0 and S1. Now assume that we start from S2.
• When you are in S2, and both A and B are asserted, you need to add the carry generated by the previous bit
together with current A and B together, resulting in F =1 and Cout=1.
• This is a state that is different from S0, S1, and S2. So we have the fourth state in the state machine and we
will label it S3.
• We need to consider all the input patterns starting from S3.

S3
Step 2: Code a State Machine in
Verilog HDL
State Machine
Inputs and outputs description
• module SA(
input A,
input B,
output F,
output Cout,
input clk,
input rst );
Instead of using numbers to directly represent states, it is
always a good practice to define state codes as constant
variables so that you can change the state encoding easily in
the future.
In Verilog, we will use the localparam statement to define
constant variables.

// Define State Codes


localparam S0 = 2'b00;
localparam S1 = 2'b01;
localparam S2 = 2'b10;
localparam S3 = 2'b11;
Declare internal signals for the next state and the
present state.
In this example, we only have four states. As we defined
the state code to be 2 bits, our next state and present
state signals should be two-bits wide.

• reg [1:0] pState, nState;


Code the next state logic: Combinational
// Combinational Logic: Next State Logic
S2:
always @ (pState, A, B)
if (A == 1'b0 && B == 1'b0)
begin
nState = S1;
case (pState)
else if (A == 1'b1 && B == 1'b1)
S0:begin
nState = S3;
if (A == 1'b0 && B == 1'b0)
else
nState = S0;
nState = S2;
else if (A == 1'b1 && B == 1'b1)
S3:
nState = S2;
if (A == 1'b0 && B == 1'b0)
else
nState = S1 ;
nState = S1;
else if (A == 1'b1 && B == 1'b1)
end
nState = S3;
S1:
else
if (A == 1'b0 && B == 1'b0)
nState = S2;
nState = S0;
default:
else if (A == 1'b1 && B == 1'b1)
nState = S0;
nState = S2;
endcase
else
end
nState = S1;
The state registers are just D flip-flops with reset signals.

• // State Registers
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
pState <= S0;
else
pState <= nState;
end
The output logic drives the outputs based on present state and Mealy
inputs.
In our case, we do not have Mealy inputs. You can use the case
statement similar to the next state logic to code the output logic here. In
this example, the assign statement is used to show that various syntaxes
can be used to describe combinational circuits.
• // Output Logic
assign F = (pState == S1 || pState == S3) ? 1'b1 : 1'b0;
assign Cout = (pState == S2 || pState == S3) ? 1'b1 : 1’b0;
endmodule

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