Mod 4 - Serial Adder Using FSM
Mod 4 - Serial Adder Using FSM
S3
Step 2: Code a State Machine in
Verilog HDL
State Machine
Inputs and outputs description
• module SA(
input A,
input B,
output F,
output Cout,
input clk,
input rst );
Instead of using numbers to directly represent states, it is
always a good practice to define state codes as constant
variables so that you can change the state encoding easily in
the future.
In Verilog, we will use the localparam statement to define
constant variables.
• // State Registers
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
pState <= S0;
else
pState <= nState;
end
The output logic drives the outputs based on present state and Mealy
inputs.
In our case, we do not have Mealy inputs. You can use the case
statement similar to the next state logic to code the output logic here. In
this example, the assign statement is used to show that various syntaxes
can be used to describe combinational circuits.
• // Output Logic
assign F = (pState == S1 || pState == S3) ? 1'b1 : 1'b0;
assign Cout = (pState == S2 || pState == S3) ? 1'b1 : 1’b0;
endmodule