PIC18FXX20

Flash Microcontroller Programming Specification

1.0 DEVICE OVERVIEW 2.1 Hardware Requirements
This document includes the programming In high voltage ICSP mode, the PIC18FXX20 requires
specifications for the following devices: two programmable power supplies: one for VDD and
one for MCLR/VPP. Both supplies should have a
• PIC18F6520
minimum resolution of 0.25V. Refer to Section 6.0 for
• PIC18F6620 additional hardware parameters.
• PIC18F6720
• PIC18F8520 2.1.1 LOW VOLTAGE ICSP
• PIC18F8620 PROGRAMMING
• PIC18F8720 In low voltage ICSP mode, the PIC18FXX20 can be
programmed using a VDD source in the operating
2.0 PROGRAMMING OVERVIEW range. This only means that MCLR/VPP does not have
to be brought to a different voltage, but can instead be
OF THE PIC18FXX20 left at the normal operating voltage. Refer to
PIC18FXX20 devices can be programmed using either Section 6.0 for additional hardware parameters.
the high voltage In-Circuit Serial ProgrammingTM
(ICSPTM) method, or the low voltage ICSP method. 2.2 Pin Diagrams
Both of these can be done with the device in the users’ The pin diagrams for the PIC18FXX20 family are
system. The low voltage ICSP method is slightly shown in Figure 2-1. The pin descriptions of these
different than the high voltage method, and these diagrams do not represent the complete functionality of
differences are noted where applicable. This the device types. Users should refer to the appropriate
programming specification applies to PIC18FXX20 device data sheet for complete pin descriptions.
devices in all package types.

TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18FXX20

During Programming
Pin Name
Pin Name Pin Type Pin Description

MCLR/VPP/RA5 VPP P Programming Enable

VDD(2) VDD P Power Supply
VSS(2) VSS P Ground
AVDD AVDD P Analog Power Supply
AVSS AVSS P Analog Ground
RB5 PGM I Low Voltage ICSP™ Input when LVP Configuration bit equals ‘1’ (1)
RB6 SCLK I Serial Clock
RB7 SDATA I/O Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: See Section 5.3 for more detail.
2: All power supply and ground must be connected.

 2010 Microchip Technology Inc. DS39583C-page 1

PIC18FXX20
FIGURE 2-1: PIC18FXX20 FAMILY PIN DIAGRAMS

RD0

RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE2
RE3
RE4
RE5
RE6
RE7

VDD
VSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

RE1 1 48 RB0
RE0 2 47 RB1
RG0 3 46 RB2
RG1 4 45 RB3
PIC18F6520 RB4
RG2 5 44
RG3 6 PIC18F6620 43 RB5
MCLR/VPP 7 PIC18F6720 42 RB6
RG4 8 41 VSS
VSS 9 64L TQFP 40 OSC2/RA6
VDD 10 39 OSC1
RF7 11 38 VDD
RF6 12 37 RB7
RF5 13 36 RC5
RF4 14 35 RC4
RF3 15 34 RC3
RF2 16 33 RC2

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RF1
RF0

RA3
RA2

RA5

RC1
RC0
RC6
RC7
AVSS

VSS
AVDD

RA1
RA0

VDD

RA4

RD0

RD1
RD2
RD3
RD4
RD5
RD6
RD7
RH0
RH1

RE2
RE3
RE4
RE5
RE6
RE7

VDD

RJ0
RJ1
VSS

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2 1 60 RJ2
RH3 2 59 RJ3
RE1 3 58 RB0
RE0 4 57 RB1
RG0 5 56 RB2
RG1 6 55 RB3
RG2 7 PIC18F8520 54 RB4
RG3 8 53 RB5
MCLR/VPP 9 PIC18F8620 52 RB6
RG4 10 51 VSS
PIC18F8720
VSS 11 50 OSC2/RA6
VDD 12 49 OSC1
RF7 13 80L TQFP 48 VDD
RF6 14 47 RB7
RF5 15 46 RC5
RF4 16 45 RC4
RF3 17 44 RC3
RF2 18 43 RC2
RH7 19 42 RJ7
RH6 20 41 RJ6
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RF1
RF0

RJ4
RJ5
RA3
RA2

RA5

RC1

RC6
RC7
RH5
RH4

AVDD

RA1
RA0

VDD

RA4
AVSS

VSS

RC0

Note: Not all multiplexed pin definitions are shown. Refer to the appropriate data sheet for complete pin descriptions.

DS39583C-page 2  2010 Microchip Technology Inc.

 PIC18FXX20
2.3 Memory Map TABLE 2-2: IMPLEMENTATION OF CODE
MEMORY
The code memory space extends from 0000h to
1FFFFh (128 Kbytes) in eight 16-Kbyte blocks. Device Code Memory Size (Bytes)
Addresses 0000h through 01FFh, however, define a PIC18F6520
“Boot Block” region that is treated separately from 000000h - 007FFFh (32K)
PIC18F8520
Block 1. All of these blocks define code protection
boundaries within the code memory space. PIC18F6620
000000h - 00FFFFh (64K)
In contrast, code memory panels are defined in 8-Kbyte PIC18F8620
boundaries. Panels are discussed in greater detail in PIC18F6720
Section 3.2. 000000h - 01FFFFh (128K)
PIC18F8720

FIGURE 2-2: MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FXX20 DEVICES

000000h
Code Memory
01FFFFh MEMORY SIZE / DEVICE

32 Kbytes Address 64 Kbytes 128 Kbytes Address

(PIC18FX520) Range (PIC18FX620) (PIC18FX720) Range
000000h 000000h
Boot Block Boot Block Boot Block
0007FFh 0001FFh
Unimplemented 000800h 000200h
Read as ‘0’ Block 0 Block 0 Block 0
001FFFh 003FFFh
002000h 004000h
Block 1 Block 1 Block 1
003FFFh 007FFFh
004000h 008000h
Block 2 Block 2 Block 2
005FFFh 00BFFFh
006000h 00C000h
1FFFFFh Block 3 Block 3 Block 3
007FFFh 00FFFFh
008000h 010000h
Block 4
013FFFh
014000h
Configuration
Block 5
and ID
Unimplemented Unimplemented 017FFFh
Space
Read ‘0’s Read ‘0’s 018000h
Block 6
01BFFFh
01C000h
Block 7
1FFFFFh 01FFFFh

3FFFFFh

Note: Sizes of memory areas not to scale.

 2010 Microchip Technology Inc. DS39583C-page 3

PIC18FXX20
In addition to the code memory space, there are three 2.3.1 MEMORY ADDRESS POINTER
blocks in the configuration and ID space that are
accessible to the user through Table Reads and Table Memory in the address space 0000000h to 3FFFFFh is
Writes. Their locations in the memory map are shown addressed via the Table Pointer, which is comprised of
in Figure 2-3. three pointer registers:

Users may store identification information (ID) in eight • TBLPTRU, at RAM address 0FF8h
ID registers. These ID registers are mapped in • TBLPTRH, at RAM address 0FF7h
addresses 200000h through 200007h. The ID locations • TBLPTRL, at RAM address 0FF6h
read out normally, even after code protection is applied.
Locations 300000h through 30000Dh are reserved for TBLPTRU TBLPTRH TBLPTRL
the Configuration bits. These bits select various device
Addr[21:16] Addr[15:8] Addr[7:0]
options, and are described in Section 5.0. These
Configuration bits read out normally, even after code
protection. The 4-bit command, ‘0000’ (Core Instruction), is used
Locations 3FFFFEh and 3FFFFFh are reserved for the to load the Table Pointer prior to using many Read or
Device ID bits. These bits may be used by the Write operations.
programmer to identify what device type is being
programmed, and are described in Section 5.0. These
Device ID bits read out normally, even after code
protection.

FIGURE 2-3: CONFIGURATION AND ID LOCATIONS FOR PIC18FXX20 DEVICES

000000h
Code Memory
01FFFFh ID Location 1 200000h
ID Location 2 200001h
ID Location 3 200002h
ID Location 4 200003h
ID Location 5 200004h
ID Location 6 200005h
Unimplemented
Read as ‘0’ ID Location 7 200006h
ID Location 8 200007h

CONFIG1L 300000h
CONFIG1H 300001h
CONFIG2L 300002h
CONFIG2H 300003h
1FFFFFh CONFIG3L 300004h
CONFIG3H 300005h
Configuration CONFIG4L 300006h
and ID CONFIG4H 300007h
Space CONFIG5L 300008h
CONFIG5H 300009h
CONFIG6L 30000Ah
2FFFFFh CONFIG6H 30000Bh
CONFIG7L 30000Ch
CONFIG7H 30000Dh

Device ID1 3FFFFEh

Device ID2 3FFFFFh

3FFFFFh

Note: Sizes of memory areas are not to scale.

DS39583C-page 4  2010 Microchip Technology Inc.

 PIC18FXX20
2.4 High Level Overview of the FIGURE 2-4: HIGH LEVEL
Programming Process PROGRAMMING FLOW
Figure 2-4 shows the high level overview of the
Start
programming process. First, a bulk erase is performed.
Next, the Code Memory, ID Locations, and Data
EEPROM are programmed. These memories are then Perform Bulk
verified to ensure that programming was successful. If Erase
no errors are detected, the Configuration bits are then
programmed and verified.
Program Memory
2.5 Entering High Voltage ICSP
Program/Verify Mode
Program IDs
The high voltage ICSP Program/Verify mode is entered
by holding SCLK and SDATA low and then raising
MCLR/VPP to VIHH (high voltage). Once in this mode,
the Code Memory, Data EEPROM, ID Locations, and Program Data
Configuration bits can be accessed and programmed in
serial fashion.
The sequence that enters the device into the Verify Program
Program/Verify mode places all unused I/Os in the high
impedance state.

2.5.1 ENTERING LOW VOLTAGE ICSP Verify IDs

PROGRAM/VERIFY MODE
When the LVP configuration bit is ‘1’ (see Section 5.3), Verify Data
the low voltage ICSP mode is enabled. Low voltage
ICSP Program/Verify mode is entered by holding SCLK
and SDATA low, placing a logic high on PGM, and then
Program
raising MCLR/VPP to VIH. In this mode, the RB5/PGM
Configuration Bits
pin is dedicated to the programming function and
ceases to be a general purpose I/O pin.
The sequence that enters the device into the Verify
Program/Verify mode, places all unused I/Os in the Configuration Bits
high impedance state.
Done

FIGURE 2-5: ENTERING HIGH FIGURE 2-6: ENTERING LOW

VOLTAGE PROGRAM/ VOLTAGE PROGRAM/
VERIFY MODE VERIFY MODE
P15 P12
P13 P12
VIH
P1 MCLR/VPP
D110

MCLR/VPP
VDD

VDD VIH
PGM

SDATA
SDATA

SCLK
SCLK
SDATA = Input
SDATA = Input

 2010 Microchip Technology Inc. DS39583C-page 5

PIC18FXX20
2.6 Serial Program/Verify Operation TABLE 2-3: COMMANDS FOR
PROGRAMMING
The SCLK pin is used as a clock input pin and the
SDATA pin is used for entering command bits and data 4-Bit
Description
input/output during serial operation. Commands and Command
data are transmitted on the rising edge of SCLK, Core Instruction
latched on the falling edge of SCLK, and are Least 0000
(Shift in16-bit instruction)
Significant bit (LSb) first.
Shift out TABLAT register 0010
2.6.1 4-BIT COMMANDS Table Read 1000
All instructions are 20-bits, consisting of a leading 4-bit Table Read, post-increment 1001
command followed by a 16-bit operand, which depends Table Read, post-decrement 1010
on the type of command being executed. To input a
command, SCLK is cycled four times. The commands Table Read, pre-increment 1011
needed for programming and verification are shown in Table Write 1100
Table 2-3.
Table Write, post-increment by 2 1101
Depending on the 4-bit command, the 16-bit operand
Table Write, post-decrement by 2 1110
represents 16 bits of input data, or 8 bits of input data
and 8 bits of output data. Table Write, start programming 1111
Throughout this specification, commands and data are
presented as illustrated in Figure 2-4. The 4-bit
command is shown MSb first. The command operand, TABLE 2-4: SAMPLE COMMAND
or “Data Payload”, is shown <MSB><LSB>. Figure 2-7
SEQUENCE
demonstrates how to serially present a 20-bit
command/operand to the device. 4-Bit Data
Core Instruction
Command Payload
2.6.2 CORE INSTRUCTION
1101 3C 40 Table Write,
The core instruction passes a 16-bit instruction to the post-increment by 2
CPU core for execution. This is needed to setup
registers as appropriate for use with other commands.

FIGURE 2-7: TABLE WRITE, POST-INCREMENT TIMING (1101)

P2 P2A
P2B
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
SCLK
P5 P5A

P4

P3

SDATA 1 0 1 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 n n n n

0 4 C 3
4-bit Command 16-bit Data Payload Fetch Next 4-bit Command

SDATA = Input

DS39583C-page 6  2010 Microchip Technology Inc.

 PIC18FXX20
3.0 DEVICE PROGRAMMING Note: A bulk erase is the only way to reprogram
code protect bits from an on-state to an
3.1 High Voltage ICSP Bulk Erase off-state.
Erasing Code or Data EEPROM is accomplished by Non-code protect bits are not returned to
writing an “erase option” to address 3C0004h. Code default settings by a bulk erase. These bits
memory may be erased portions at a time, or the user should be programmed to ones, as out-
may erase the entire device in one action. “Bulk Erase” lined in Section 3.6, "Configuration Bits
operations will also clear any code protect settings Programming".
associated with the memory block erased. Erase
options are detailed in Table 3-1. FIGURE 3-1: BULK ERASE COMMAND
SEQUENCE
TABLE 3-1: BULK ERASE OPTIONS 4-Bit Data
Core Instruction
Description Data Command Payload

Chip Erase 80h 0000 0E 3C MOVLW 3Ch

0000 6E F8 MOVWF TBLPTRU
Erase Data EEPROM 81h 0000 0E 00 MOVLW 00h
Erase Boot Block 83h 0000 6E F7 MOVWF TBLPTRH
Erase Block 1 88h 0000 0E 04 MOVLW 04h
0000 6E F6 MOVWF TBLPTRL
Erase Block 2 89h 1100 00 80 Write 80h TO 3C0004h to
Erase Block 3 8Ah erase entire device.
0000 00 00 NOP
Erase Block 4 8Bh
0000 00 00 Hold SDATA low until
Erase Block 5 8Ch erase completes.
Erase Block 6 8Dh
Erase Block 7 8Eh FIGURE 3-2: BULK ERASE FLOW
Erase Block 8 8Fh Start

The actual Bulk Erase function is a self-timed

operation. Once the erase has started (falling edge of Load Address
the 4th SCLK after the NOP command), serial execution Pointer to
3C0004h
will cease until the erase completes (parameter P11).
During this time, SCLK may continue to toggle, but
SDATA must be held low. Write 80h
To Erase
The code sequence to erase the entire device is shown Entire Device
in Figure 3-1 and the flowchart is shown in Figure 3-2.

Delay P11+P10
Time

Done

FIGURE 3-3: BULK ERASE TIMING

P10
1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 1 2 3 4 1 2
SCLK
P5 P5A P5 P5A P11

SDATA 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n n

4-bit Command 16-bit 4-bit Command 16-bit 4-bit Command Erase Time 16-bit
Data Payload Data Payload Data Payload

SDATA = Input

 2010 Microchip Technology Inc. DS39583C-page 7

PIC18FXX20
3.1.1 LOW VOLTAGE ICSP BULK ERASE 3.1.2 ICSP MULTI-PANEL SINGLE ROW
ERASE
When using low voltage ICSP, the part must be
supplied by the voltage specified in parameter #D111, Irrespective of whether high or low voltage ICSP is
if a bulk erase is to be executed. All other bulk erase used, it is possible to erase single row (64 bytes of
details as described above apply. data) in all panels at once. For example, in the case of
If it is determined that a program memory erase must a 64-Kbyte device (8 panels), 512 bytes through 64
be performed at a supply voltage below the bulk erase bytes in each panel can be erased simultaneously dur-
limit, refer to the erase methodology described in ing each erase sequence. In this case, the offset of the
Sections 3.1.2 and 3.2.2. erase within each panel is the same (see Figure 3-6).
Multi-panel single row erase is enabled by appropri-
If it is determined that a data EEPROM erase must be ately configuring the Programming Control register
performed at a supply voltage below the bulk erase located at 3C0006h.
limit, follow the methodology described in Section 3.3
and write ones to the array. The multi-panel single row erase duration is externally
timed and is controlled by SCLK. After a “Start Pro-
gramming” command is issued (4-bit, ‘1111’), a NOP is
issued, where the 4th SCLK is held high for the
duration of the programming time, P9.
After SCLK is brought low, the programming sequence
is terminated. SCLK must be held low for the time spec-
ified by parameter P10 to allow high voltage discharge
of the memory array.
The code sequence to program a PIC18FXX20 device
is shown in Table 3-2. The flowchart shown in
Figure 3-4 depicts the logic necessary to completely
erase a PIC18FXX20 device. The timing diagram that
details the “Start Programming” command, and
parameters P9 and P10 is shown in Figure 3-7.
Note: The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.

DS39583C-page 8  2010 Microchip Technology Inc.

 PIC18FXX20
TABLE 3-2: ERASE CODE MEMORY CODE SEQUENCE
4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to config memory.

0000 8E A6 BSF EECON1, EEPGD

0000 8C A6 BSF EECON1, CFGS
0000 86 A6 BSF EECON1, WREN

Step 2: Configure device for multi-panel writes.

0000 0E 3C MOVLW 3Ch

0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 06 MOVLW 06h
0000 6E F6 MOVWF TBLPTRL
1100 00 40 Write 40h to 3C0006h to enable multi-panel erase.

Step 3: Direct access to code memory and enable erase.

0000 8E A6 BSF EECON1, EEPGD

0000 9C A6 BCF EECON1, CFGS
0000 88 A6 BSF EECON1, FREE
0000 6A F8 CLRF TBLPTRU
0000 6A F7 CLRF TBLPTRH
0000 6A F6 CLRF TBLPTRL

Step 4: Erase single row of all panels at an offset.

1111 <DummyLSB> Write 2 dummy bytes and start programming.

<DummyMSB>
0000 00 00 NOP - hold SCLK high for time P9.

Step 5: Repeat step 4, with Address Pointer incremented by 64 until all panels are erased.

FIGURE 3-4: MULTI-PANEL SINGLE ROW ERASE CODE MEMORY FLOW

Start

Addr = 0
Configure
Device for
Multi-Panel Erase

Start Erase Sequence

and hold SCLK High
Until Done

Addr = Addr + 64
Delay P9 + P10
Time for Erase
to occur

All
No Panels
Done?

Yes

Done

 2010 Microchip Technology Inc. DS39583C-page 9

PIC18FXX20
3.2 Code Memory Programming The programming duration is externally timed and is
controlled by SCLK. After a “Start Programming”
Programming code memory is accomplished by first command is issued (4-bit command, ‘1111’), a NOP is
loading data into the appropriate write buffers and then issued, where the 4th SCLK is held high for the
initiating a programming sequence. Each panel in the duration of the programming time, P9.
code memory space (see Figure 2-2) has an 8-byte
deep write buffer that must be loaded prior to initiating After SCLK is brought low, the programming sequence
a write sequence. The actual memory write sequence is terminated. SCLK must be held low for the time
takes the contents of these buffers and programs the specified by parameter P10 to allow high voltage
associated EEPROM code memory. discharge of the memory array.

Typically, all of the program buffers are written in The code sequence to program a PIC18FXX20 device
parallel (Multi-Panel Write mode). In other words, in the is shown in Figure 3-3. The flowchart shown in
case of a 128-Kbyte device (16 panels with an 8-byte Figure 3-6 depicts the logic necessary to completely
buffer per panel), 128 bytes will be simultaneously write a PIC18FXX20 device. The timing diagram that
programmed during each programming sequence. In details the “Start Programming” command, and
this case, the offset of the write within each panel is the parameters P9 and P10, is shown in Figure 3-7.
same (see Figure 3-5). Multi-Panel Write mode is Note: The TBLPTR register must contain the
enabled by appropriately configuring the Programming same offset value when initiating the pro-
Control register located at 3C0006h. gramming sequence as it did when the
write buffers were loaded.

DS39583C-page 10  2010 Microchip Technology Inc.

 PIC18FXX20
FIGURE 3-5: ERASE AND WRITE BOUNDARIES

Panel n
TBLPTR<21:13> = (n – 1)

TBLPTR<2:0> = 7 Erase Region

8-byte Write Buffer

TBLPTR<2:0> = 6 (64 bytes)

TBLPTR<2:0> = 5
TBLPTR<2:0> = 4
TBLPTR<2:0> = 3
TBLPTR<2:0> = 2
TBLPTR<2:0> = 1
TBLPTR<2:0> = 0
Offset = TBLPTR<12:3> Offset = TBLPTR<12:6>

Panel 3
TBLPTR<21:13> = 2

TBLPTR<2:0> = 7 Erase Region

8-byte Write Buffer

TBLPTR<2:0> = 6 (64 bytes)

TBLPTR<2:0> = 5
TBLPTR<2:0> = 4
TBLPTR<2:0> = 3
TBLPTR<2:0> = 2
TBLPTR<2:0> = 1
TBLPTR<2:0> = 0
Offset = TBLPTR<12:3> Offset = TBLPTR<12:6>

Panel 2
TBLPTR<21:13> = 1

TBLPTR<2:0> = 7 Erase Region

8-byte Write Buffer

TBLPTR<2:0> = 6 (64 bytes)

TBLPTR<2:0> = 5
TBLPTR<2:0> = 4
TBLPTR<2:0> = 3
TBLPTR<2:0> = 2
TBLPTR<2:0> = 1
TBLPTR<2:0> = 0
Offset = TBLPTR<12:3> Offset = TBLPTR<12:6>

Panel 1
TBLPTR<21:13> = 0

TBLPTR<2:0> = 7 Erase Region

8-byte Write Buffer

TBLPTR<2:0> = 6 (64 bytes)

TBLPTR<2:0> = 5
TBLPTR<2:0> = 4
TBLPTR<2:0> = 3
TBLPTR<2:0> = 2
TBLPTR<2:0> = 1
TBLPTR<2:0> = 0
Offset = TBLPTR<12:3> Offset = TBLPTR<12:6>

Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL.

 2010 Microchip Technology Inc. DS39583C-page 11

PIC18FXX20
TABLE 3-3: WRITE CODE MEMORY CODE SEQUENCE
4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to config memory.

0000 8E A6 BSF EECON1, EEPGD

0000 8C A6 BSF EECON1, CFGS
0000 86 A6 BSF EECON1, WREN

Step 2: Configure device for multi-panel writes.

0000 0E 3C MOVLW 3Ch

0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 06 MOVLW 06h
0000 6E F6 MOVWF TBLPTRL
1100 00 40 Write 40h to 3C0006h to enable multi-panel writes.

Step 3: Direct access to code memory.

0000 8E A6 BSF EECON1, EEPGD

0000 9C A6 BCF EECON1, CFGS

Step 4: Load write buffer for Panel 1.

0000 0E <Addr[21:16]> MOVLW <Addr[21:16]>

0000 6E F8 MOVWF TBLPTRU
0000 0E <Addr[15:8]> MOVLW <Addr[15:8]>
0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1100 <LSB><MSB> Write 2 bytes

Step 5: Repeat for Panel 2.

Step 6: Repeat for all but the last panel (N – 1).

Step 7: Load write buffer for last panel.

0000 0E <Addr[21:16]> MOVLW <Addr[21:16]>

0000 6E F8 MOVWF TBLPTRU
0000 0E <Addr[15:8]> MOVLW <Addr[15:8]>
0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1111 <LSB><MSB> Write 2 bytes and start programming
0000 00 00 NOP - hold SCLK high for time P9

To continue writing data, repeat steps 2 through 5, where the Address Pointer is incremented by 8 in each panel at each iteration of
the loop.

DS39583C-page 12  2010 Microchip Technology Inc.

 PIC18FXX20
FIGURE 3-6: PROGRAM CODE MEMORY FLOW

Start
N=1
LoopCount = 0
Configure
Device for
Multi-Panel Writes

Panel Base Address =

(N – 1) x 2000h
Addr = Panel Base Address
+ (8 x LoopCount)

Load 8 Bytes
N=N+1 to Panel N Write
Buffer at <Addr>

All
No Panel Buffers
Written?

N=1 Yes
LoopCount =
LoopCount + 1 Start Write Sequence
and Hold SCLK
High Until Done

Delay P9+P10 Time

for Write to Occur

No All
Locations
Done?

Yes

Done

FIGURE 3-7: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111)
P10
1 2 3 4 1 2 3 4 5 6 15 16 1 2 3 4 1 2 3
SCLK P9
P5 P5A

SDATA 1 1 1 1 n n n n n n n n 0 0 0 0 0 0 0

4-bit Command 16-bit Data Payload 4-bit Command Programming Time 16-bit
Data Payload
SDATA = Input

 2010 Microchip Technology Inc. DS39583C-page 13

PIC18FXX20
3.2.1 SINGLE PANEL PROGRAMMING The minimum amount of code memory that may be
erased at a given time is 64 bytes. Again, the device
The programming example presented in Section 3.2 must be placed in Single Panel Write mode. The
utilizes multi-panel programming. This technique EECON1 register must then be used to erase the
greatly decreases the total amount of time necessary to 64-byte target space prior to writing the data.
completely program a device and is the recommended
method of completely programming a device. When using the EECON1 register to act on
code memory, the EEPGD bit must be set
There may be situations, however, where it is (EECON1<7> = 1) and the CFGS bit must be cleared
advantageous to limit writes to a single panel. In such (EECON1<6> = 0). The WREN bit must be set
cases, the user only needs to disable the multi-panel (EECON1<2> = 1) to enable writes of any sort (e.g.,
write feature of the device by appropriately configuring erases), and this must be done prior to initiating a
the programming control register located at 3C0006h. write sequence. The FREE bit must be set
The single panel that will be written will automatically (EECON1<4> = 1) in order to erase the program
be enabled based on the value of the Table Pointer. space being pointed to by the Table Pointer. The
erase sequence is initiated by the setting the WR bit
Note: Even though multi-panel writes are dis-
(EECON1<1> = 1). It is strongly recommended that
abled, the user must still fill the 8-byte write
the WREN bit be set only when absolutely necessary.
buffer for the given panel.
To help prevent inadvertent writes when using the
3.2.2 MODIFYING CODE MEMORY EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
All of the programming examples up to this point have and then AAh, immediately prior to asserting the WR bit
assumed that the device has been bulk erased prior to in order for the write to occur.
programming (see Section 3.1). It may be the case,
however, that the user wishes to modify only a section The erase will begin on the falling edge of the 4th
of an already programmed device. SCLK, after the WR bit is set. After the erase sequence
terminates, SCLK must still be held low for the time
The minimum amount of data that can be written to the specified by parameter #P10 to allow high voltage
device is 8 bytes. This is accomplished by placing the discharge of the memory array.
device in Single Panel Write mode (see Section 3.2.1),
loading the 8-byte write buffer for the panel, and then
initiating a write sequence. In this case, however, it is
assumed that the address space to be written already
has data in it (i.e., it is not blank).

DS39583C-page 14  2010 Microchip Technology Inc.

 PIC18FXX20
TABLE 3-4: MODIFYING CODE MEMORY
4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to config memory.

0000 8E A6 BSF EECON1, EEPGD

0000 8C A6 BSF EECON1, CFGS

Step 2: Configure device for single panel writes.

0000 0E 3C MOVLW 3Ch

0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 06 MOVLW 06h
0000 6E F6 MOVWF TBLPTRL
1100 00 00 Write 00h to 3C0006h to enable single panel writes.

Step 3: Direct access to code memory.

0000 8E A6 BSF EECON1, EEPGD

0000 9C A6 BCF EECON1, CFGS

Step 4: Set the Table Pointer for the block to be erased.

0000 0E <Addr[21:16]> MOVLW <Addr[21:16]>

0000 6E F8 MOVWF TBLPTRU
0000 0E <Addr[8:15]> MOVLW <Addr[8:15]>
0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL

Step 5: Enable memory writes and set up an erase.

0000 84 A6 BSF EECON1, WREN

0000 88 A6 BSF EECON1, FREE

Step 6: Perform required sequence.

0000 0E 55 MOVLW 55h

0000 6E A7 MOVWF EECON2
0000 0E AA MOVLW 0AAh
0000 6E A7 MOVWF EECON2

Step 7: Initiate erase.

0000 82 A6 BSF EECON1, WR

0000 00 00 NOP

Step 8: Wait for P11+P10 and then disable writes.

0000 94 A6 BCF EECON1, WREN

Step 9: Load write buffer for panel. The correct panel will be selected based on the Table Pointer.

0000 0E <Addr[8:15]> MOVLW <Addr[8:15]>

0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1111 <LSB><MSB> Write 2 bytes and start programming
0000 00 00 NOP - hold SCLK high for time P9

To continue writing data, repeat step 8, where the Address Pointer is incremented by 8 at each iteration of the loop.

 2010 Microchip Technology Inc. DS39583C-page 15

PIC18FXX20
3.3 Data EEPROM Programming FIGURE 3-8: PROGRAM DATA FLOW
Data EEPROM is accessed one byte at a time via an
Start
Address Pointer (register pair EEADR:EEADRH) and a
data latch (EEDATA). Data EEPROM is written by
loading EEADR:EEADRH with the desired memory Set Address
location, EEDATA with the data to be written, and
initiating a memory write by appropriately configuring
the EECON1 and EECON2 registers. A byte write Set Data
automatically erases the location and writes the new
data (erase-before-write).
Enable Write
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
Unlock Sequence
be set (EECON1<2> = 1) to enable writes of any sort, 55h - EECON2
and this must be done prior to initiating a write AAh - EECON2
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended
Start Write
that the WREN bit be set only when absolutely Sequence
necessary.
To help prevent inadvertent writes when using the WR bit No
EECON1 register, EECON2 is used to “enable” the WR Clear ?
bit. This register must be sequentially loaded with 55h
Yes
and then AAh, immediately prior to asserting the WR bit
in order for the write to occur. No Done
The write begins on the falling edge of the 4th SCLK ?
after the WR bit is set. It ends when the WR bit is Yes
cleared by hardware.
Done
After the programming sequence terminates, SCLK
must still be held low for the time specified by
parameter P10 to allow high voltage discharge of the
memory array.

FIGURE 3-9: DATA EEPROM WRITE TIMING

P10
1 2 3 4 1 2 15 16 1 2

SCLK
P5 P5A

0 0 0 0 n n
SDATA
4-bit Command BSF EECON1, WR Poll WR bit, Repeat Until Clear 16-bit Data
(see below) Payload

SDATA = Input

1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16
SCLK
P5 P5A P5 P5A

Poll WR bit
0 0 0 0 0 0 0 0
SDATA

4-bit Command MOVF EECON1, W, 0 4-bit Command MOVWF TABLAT Shift Out Data
(see Figure 4-6)

SDATA = Input SDATA = Output

DS39583C-page 16  2010 Microchip Technology Inc.

 PIC18FXX20
TABLE 3-5: PROGRAMMING DATA MEMORY
4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to data EEPROM.

0000 9E A6 BCF EECON1, EEPGD

0000 9C A6 BCF EECON1, CFGS

Step 2: Set the data EEPROM Address Pointer.

0000 0E <Addr> MOVLW <Addr>

0000 6E A9 MOVWF EEADR
0000 OE <AddrH> MOVLW <AddrH>
0000 6E AA MOVWF EEADRH

Step 3: Load the data to be written.

0000 0E <Data> MOVLW <Data>

0000 6E A8 MOVWF EEDATA

Step 4: Enable memory writes.

0000 84 A6 BSF EECON1, WREN

Step 5: Perform required sequence.

0000 0E 55 MOVLW 0X55

0000 6E A7 MOVWF EECON2
0000 0E AA MOVLW 0XAA
0000 6E A7 MOVWF EECON2

Step 6: Initiate write.

0000 82 A6 BSF EECON1, WR

Step 7: Poll WR bit, repeat until the bit is clear.

0000 50 A6 MOVF EECON1, W, 0

0000 6E F5 MOVWF TABLAT
0010 <LSB><MSB> Shift out data(1)

Step 8: Disable writes.

0000 94 A6 BCF EECON1, WREN

Repeat steps 2 through 8 to write more data.

Note 1: See Figure 4-4 for details on Shift Out Data timing.

 2010 Microchip Technology Inc. DS39583C-page 17

PIC18FXX20
3.4 ID Location Programming
The ID Locations are programmed much like the code
memory, except that multi-panel writes must be
disabled. The single panel that will be written will
automatically be enabled, based on the value of the
Table Pointer. The ID registers are mapped in
addresses 200000h through 200007h. These locations
read out normally, even after code protection.

Note: Even though multi-panel writes are dis-

abled, the user must still fill the 8-byte data
buffer for the panel.
Figure 3-6 demonstrates the code sequence required
to write the ID locations.

TABLE 3-6: WRITE ID SEQUENCE

4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to config memory.

0000 8E A6 BSF EECON1, EEPGD

0000 8C A6 BSF EECON1, CFGS

Step 2: Configure device for single panel writes.

0000 0E 3C MOVLW 3Ch

0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 06 MOVLW 06h
0000 6E F6 MOVWF TBLPTRL
1100 00 00 Write 00h to 3C0006h to enable single panel writes.

Step 3: Direct access to code memory.

0000 8E A6 BSF EECON1, EEPGD

0000 9C A6 BCF EECON1, CFGS

Step 4: Load write buffer. Panel will be automatically determined by address.

0000 0E 20 MOVLW 20h

0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 00 MOVLW 00h
0000 6E F6 MOVWF TBLPTRL
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1101 <LSB><MSB> Write 2 bytes and post-increment address by 2
1111 <LSB><MSB> Write 2 bytes and start programming
0000 00 00 NOP - hold SCLK high for time P9

In order to modify the ID locations, refer to the

methodology described in Section 3.2.2, “Modifying
Code Memory”. As with code memory, the ID locations
must be erased before modified.

DS39583C-page 18  2010 Microchip Technology Inc.

 PIC18FXX20
3.5 Boot Block Programming 3.6 Configuration Bits Programming
The Boot Block segment is programmed in exactly the Unlike code memory, the configuration bits are
same manner as the ID locations (see Section 3.4). programmed a byte at a time. The “Table Write, Begin
Multi-panel writes must be disabled so that only Programming” 4-bit command (1111) is used, but only
addresses in the range 0000h to 01FFh will be written. 8 bits of the following 16-bit payload will be written. The
The code sequence detailed in Figure 3-6 should be LSB of the payload will be written to even addresses,
used, except that the address data used in “Step 2” will and the MSB will be written to odd addresses. The
be in the range 000000h to 0001FFh. code sequence to program two consecutive
configuration locations is shown in Figure 3-7.

TABLE 3-7: SET ADDRESS POINTER TO CONFIGURATION LOCATION

4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to config memory.

0000 8E A6 BSF EECON1, EEPGD

0000 8C A6 BSF EECON1, CFGS

Step 2: Position the program counter(1).

0000 EF 00 GOTO 100000h

0000 F8 00

Step 3(2): Set Table Pointer for config byte to be written. Write even/odd addresses.

0000 0E 30 MOVLW 30h

0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPRTH
0000 0E 00 MOVLW 00h
0000 6E F6 MOVWF TBLPTRL
1111 <LSB><MSB ignored> Load 2 bytes and start programming
0000 00 00 NOP - hold SCLK high for time P9
0000 2A F6 INCF TBLPTRL
1111 <LSB ignored><MSB> Load 2 bytes and start programming
0000 00 00 NOP - hold SCLK high for time P9

Note 1: If the code protection bits are programmed while the program counter resides in the same block, then the interaction of
code protection logic may prevent further table write. To avoid this situation, move the program counter outside the code
protection area (e.g., GOTO 100000h).
2: Enabling the write protection of configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of configuration
bits. Always write all the configuration bits before enabling the write protection for configuration bits.

FIGURE 3-10: CONFIGURATION PROGRAMMING FLOW

Start Start

Load Even Load Odd

Configuration Configuration
Address Address

Program Program
LSB MSB

Delay P9 Time Delay P9 Time

for Write for Write

Done Done

 2010 Microchip Technology Inc. DS39583C-page 19

PIC18FXX20
4.0 READING THE DEVICE The 4-bit command is shifted in LSb first. The Table
Read is executed during the next 8 clocks, then shifted
4.1 Read Code Memory, ID Locations, out on SDATA during the last 8 clocks, LSb to MSb. A
and Configuration Bits delay of P6 must be introduced after the falling edge of
the 8th SCLK of the operand to allow SDATA to
Code memory is accessed one byte at a time via the transition from an input to an output. During this time,
4-bit command, ‘1001’ (Table Read, post-increment). SCLK must be held low (see Figure 4-1). This operation
The contents of memory pointed to by the Table Pointer also increments the Table Pointer by one, pointing to the
(TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the next byte in code memory for the next read.
Table Latch and then serially output on SDATA. This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to the reading of the ID and Configuration registers.

TABLE 4-1: READ CODE MEMORY SEQUENCE

4-Bit
Data Payload Core Instruction
Command

Step 1: Set Table Pointer.

0000 0E <Addr[21:16]> MOVLW Addr[21:16]

0000 6E F8 MOVWF TBLPTRU
0000 0E <Addr[15:8]> MOVLW <Addr[15:8]>
0000 6E F7 MOVWF TBLPTRH
0000 0E <Addr[7:0]> MOVLW <Addr[7:0]>
0000 6E F6 MOVWF TBLPTRL

Step 2: Read memory into Table Latch and then shift out on SDATA, LSb to MSb.

1001 00 00 TBLRD *+

FIGURE 4-1: TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)

1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
SCLK
P5 P6 P5A

P14

SDATA 1 0 0 1 LSb 1 2 3 4 5 6 MSb n n n n

Shift Data Out Fetch Next 4-bit Command

SDATA = Input SDATA = Output SDATA = Input

DS39583C-page 20  2010 Microchip Technology Inc.

 PIC18FXX20
4.2 Verify Code Memory and ID The Table Pointer must be manually set to 200000h
locations (base address of the ID locations), once the code
memory has been verified. The post-increment feature
The verify step involves reading back the code memory of the Table Read 4-bit command may not be used to
space and comparing against the copy held in the increment the Table Pointer beyond the code memory
programmer’s buffer. Memory reads occur a single byte space. In a 32-Kbyte device, for example, a
at a time, so two bytes must be read to compare post-increment read of address 7FFFh will wrap the
against the word in the programmer’s buffer. Refer to Table Pointer back to 0000h, rather than point to
Section 4.1 for implementation details of reading code unimplemented address 8000h.
memory.

FIGURE 4-2: VERIFY CODE MEMORY FLOW

Start

Set Pointer = 0 Set Pointer = 200000h

Read Low Byte Read Low Byte

Read High byte Read High byte

Does Does
No No
Word = Expect Failure, Word = Expect Failure,
Data? Report Data? Report
Error Error
Yes Yes

All All
No No ID Locations
Code Memory
Verified? Verified?

Yes Yes

Done

 2010 Microchip Technology Inc. DS39583C-page 21

PIC18FXX20
4.3 Verify Configuration Bits FIGURE 4-3: READ DATA EEPROM
FLOW
A configuration address may be read and output on
SDATA via the 4-bit command, ‘1001’. Configuration
data is read and written in a byte-wise fashion, so it is Start
not necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
Set
compared to the appropriate configuration data in the Address
programmer’s memory for verification. Refer to
Section 4.1 for implementation details of reading
configuration data. Read
Byte
4.4 Read Data EEPROM Memory
Data EEPROM is accessed one byte at a time via an
Move to TABLAT
Address Pointer (register pair EEADR:EEADRH) and a
data latch (EEDATA). Data EEPROM is read by loading
EEADR:EEADRH with the desired memory location
and initiating a memory read by appropriately Shift Out Data
configuring the EECON1 register. The data will be
loaded into EEDATA, where it may be serially output on
SDATA via the 4-bit command, ‘0010’ (Shift Out Data
Holding register). A delay of P6 must be introduced No Done
?
after the falling edge of the 8th SCLK of the operand to
allow SDATA to transition from an input to an output. Yes
During this time, SCLK must be held low (see
Done
Figure 4-4).
The command sequence to read a single byte of data
is shown in Figure 4-2.

DS39583C-page 22  2010 Microchip Technology Inc.

 PIC18FXX20
TABLE 4-2: READ DATA EEPROM MEMORY
4-Bit
Data Payload Core Instruction
Command

Step 1: Direct access to data EEPROM.

0000 9E A6 BCF EECON1, EEPGD

0000 9C A6 BCF EECON1, CFGS

Step 2: Set the data EEPROM Address Pointer.

0000 0E <Addr> MOVLW <Addr>

0000 6E A9 MOVWF EEADR
0000 OE <AddrH> MOVLW <AddrH>
0000 6E AA MOVWF EEADRH

Step 3: Initiate a memory read.

0000 80 A6 BSF EECON1, RD

Step 4: Load data into the Serial Data Holding register.

0000 50 A8 MOVF EEDATA, W, 0

0000 6E F5 MOVWF TABLAT
0010 <LSB><MSB> Shift Out Data(1)

Note 1: The <LSB> is undefined. The <MSB> is the data.

FIGURE 4-4: SHIFT OUT DATA HOLDING REGISTER TIMING (0010)

1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
SCLK
P5 P6 P5A

P14

SDATA 0 1 0 0 LSb 1 2 3 4 5 6 MSb n n n n

Shift Data Out Fetch Next 4-bit Command

SDATA = Input SDATA = Output SDATA = Input

 2010 Microchip Technology Inc. DS39583C-page 23

PIC18FXX20
4.5 Verify Data EEPROM Given that “Blank Checking” is merely code and data
EEPROM verification with FFh expect data, refer to
A data EEPROM address may be read via a sequence Section 4.4 and Section 4.2 for implementation details.
of core instructions (4-bit command, ‘0000’) and then
output on SDATA via the 4-bit command, ‘0010’ (Shift
FIGURE 4-5: BLANK CHECK FLOW
Out Data Holding register). The result may then be
immediately compared to the appropriate data in the
programmer’s memory for verification. Refer to Start
Section 4.4 for implementation details of reading data
EEPROM.
Blank Check Device
4.6 Blank Check
The term “Blank Check” means to verify that the device Is
has no programmed memory cells. All memories must Device Yes
Continue
be verified: Code Memory, Data EEPROM, ID Blank?
Locations, and Configuration bits. The Device ID
registers (3FFFFEh:3FFFFFh) should be ignored. No

A “blank” or “erased” memory cell will read as a ‘1’. So, Abort

“Blank Checking” a device merely means to verify that
all bytes read as FFh, except the Configuration bits.
Unused (reserved) Configuration bits will read ‘0’
(programmed). Refer to Table 5-2 for blank
configuration expect data for the various PIC18FXX20
devices.

DS39583C-page 24  2010 Microchip Technology Inc.

 PIC18FXX20
5.0 CONFIGURATION WORD 5.3 Low Voltage Programming (LVP)
Bit
The PIC18FXX20 devices have several configuration
words. These bits can be set or cleared to select The LVP bit in Configuration register, CONFIG4L,
various device configurations. All other memory areas enables low voltage ICSP programming. The LVP bit
should be programmed and verified prior to setting defaults to a ‘1’ from the factory.
configuration words. These bits may be read out
If Low Voltage Programming mode is not used, the LVP
normally, even after read or code protection.
bit can be programmed to a ‘0’ and RB5/PGM becomes
a digital I/O pin. However, the LVP bit may only be
5.1 ID Locations
programmed by entering the high voltage ICSP mode,
A user may store identification information (ID) in eight where MCLR/VPP is raised to VIHH. Once the LVP bit is
ID locations mapped in 200000h:200007h. It is programmed to a ‘0’, only the high voltage ICSP mode
recommended that the Most Significant nibble of each is available and only the high voltage ICSP mode can
ID be 0Fh. In doing so, if the user code inadvertently be used to program the device.
tries to execute from the ID space, the ID data will
Note 1: The normal ICSP mode is always avail-
execute as NOP.
able, regardless of the state of the LVP
bit, by applying VIHH to the MCLR/VPP
5.2 Device ID Word
pin.
The device ID word for the PIC18FXX20 is located at 2: While in low voltage ICSP mode, the RB5
3FFFFEh:3FFFFFh. These bits may be used by the pin can no longer be used as a general
programmer to identify what device type is being purpose I/O.
programmed and read out normally, even after code or
read protection.

TABLE 5-1: DEVICE ID VALUES

Device ID Value
Device
DEVID2 DEVID1
PIC18F6520 0Bh 001x xxxx
PIC18F6620 06h 011x xxxx
PIC18F6720 06h 001x xxxx
PIC18F8520 0Bh 000x xxxx
PIC18F8620 06h 010x xxxx
PIC18F8720 06h 000x xxxx
Note: The ‘x’s in DEVID1 contain the device revision code.

 2010 Microchip Technology Inc. DS39583C-page 25

PIC18FXX20
TABLE 5-2: PIC18FXX20 CONFIGURATION BITS AND DEVICE IDS
Default/
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed
Value

300001h CONFIG1H — — OSCSEN — — FOSC2 FOSC1 FOSC0 0010 0111

300002h CONFIG2L — — — — BORV1 BORV0 BODEN PWRTEN 0000 1111
300003h CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN 0000 1111
300004h(1) CONFIG3L WAIT — — — — — PM1 PM0 1000 0011
300005h CONFIG3H — — — — — — T1OSCMX(3) CCP2MX 0000 0001
300006h CONFIG4L DEBUG — — — — LVP — STVREN 1000 0101
300008h CONFIG5L CP7(2) CP6(2) CP5(2) CP4(2) CP3 CP2 CP1 CP0 1111 1111
300009h CONFIG5H CPD CPB — — — — — — 1100 0000
(2) (2) (2) (2)
30000Ah CONFIG6L WRT7 WRT6 WRT5 WRT4 WRT3 WRT2 WRT1 WRT0 1111 1111
30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 1110 0000
30000Ch CONFIG7L EBTR7(2) EBTR6(2) EBTR5(2) EBTR4(2) EBTR3 EBTR2 EBTR1 EBTR0 1111 1111
30000Dh CONFIG7H — EBTRB — — — — — — 0100 0000
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplemented in PIC18F6X20 devices; maintain this bit set.
2: Unimplemented in PIC18FX620 and PIC18FX520 devices; maintain this bit set.
3: PIC18F8520/8620 devices only.

DS39583C-page 26  2010 Microchip Technology Inc.

 PIC18FXX20
TABLE 5-3: PIC18FXX20 CONFIGURATION BIT DESCRIPTIONS
Configuration
Bit Name Description
Words

OSCEN CONFIG1H Low Power System Clock Option (Timer1) Enable bit
1 = Disabled
0 = Timer1 oscillator system clock option enabled
FOSC2:FOSC0 CONFIG1H Oscillator Selection bits
111 = RC oscillator w/ OSC2 configured as RA6
110 = HS oscillator w/ PLL enabled
101 = EC oscillator w/ OSC2 configured as RA6
100 = RC oscillator w/ OSC2 configured as “divide by 4 clock output”
011 = RC oscillator
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
BORV1:BORV0 CONFIG2L Brown-out Reset Voltage bits
11 = VBOR set to 2.0V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
BOREN CONFIG2L Brown-out Reset Enable bit
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
PWRTEN CONFIG2L Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTPS2:WDTPS0 CONFIG2H Watchdog Timer Postscaler Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
WDTEN CONFIG2H Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
WAIT(1) CONFIG3L External Bus Data Wait Enable bit
1 = Wait selections unavailable
0 = Wait selections determined by WAIT1:WAIT0 bits of MEMCOM
register
PM1:PM0(1) CONFIG3L Processor Mode Select bits
11 = Microcontroller mode
10 = Microprocessor mode
01 = Microprocessor with Boot Block mode
00 = Extended Microcontroller mode
Note 1: Unimplemented in PIC18F6X20 (64-pin) devices; maintain this bit set.
2: Unimplemented in PIC18FX620 devices; maintain this bit set.
3: PIC18F8520/8620 devices only.

 2010 Microchip Technology Inc. DS39583C-page 27

PIC18FXX20
TABLE 5-3: PIC18FXX20 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Configuration
Bit Name Description
Words

T1OSCMX(3) CONFIG3H Timer1 Oscillator MUX bit

1 = Legacy Timer1 oscillator selected
0 = Low power Timer1 oscillator selected
CCP2MX CONFIG3H CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
DEBUG CONFIG4L Background Debugger Enable bit
1 = Background debugger disabled
0 = Background debugger enabled
LVP CONFIG4L Low Voltage Programming Enable bit
1 = Low voltage programming enabled
0 = Low voltage programming disabled
STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit
1 = Stack overflow/underflow will cause RESET
0 = Stack overflow/underflow will not cause RESET
CP0 CONFIG5L Code Protection bits (Block 0)
1 = Code memory not code protected
0 = Code memory code protected
CP1 CONFIG5L Code Protection bits (Block 1)
1 = Code memory not code protected
0 = Code memory code protected
CP2 CONFIG5L Code Protection bits (Block 2)
1 = Code memory not code protected
0 = Code memory code protected
CP3 CONFIG5L Code Protection bits (Block 3)
1 = Code memory not code protected
0 = Code memory code protected
CP4(2) CONFIG5L Code Protection bits (Block 4)
1 = Code memory not code protected
0 = Code memory code protected
CP5(2) CONFIG5L Code Protection bits (Block 5)
1 = Code memory not code protected
0 = Code memory code protected
CP6(2) CONFIG5L Code Protection bits (Block 6)
1 = Code memory not code protected
0 = Code memory code protected
CP7(2) CONFIG5L Code Protection bits (Block 7)
1 = Code memory not code protected
0 = Code memory code protected
Note 1: Unimplemented in PIC18F6X20 (64-pin) devices; maintain this bit set.
2: Unimplemented in PIC18FX620 devices; maintain this bit set.
3: PIC18F8520/8620 devices only.

DS39583C-page 28  2010 Microchip Technology Inc.

 PIC18FXX20
TABLE 5-3: PIC18FXX20 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Configuration
Bit Name Description
Words

CPD CONFIG5H Code Protection bits (Data EEPROM)

1 = Data EEPROM not code protected
0 = Data EEPROM code protected
CPB CONFIG5H Code Protection bits (Boot Block)
1 = Boot block not code protected
0 = Boot block code protected
WRT0 CONFIG6L Table Write Protection bit (Block 0)
1 = Code memory not write protected
0 = Code memory write protected
WRT1 CONFIG6L Table Write Protection bit (Block 1)
1 = Code memory not write protected
0 = Code memory write protected
WRT2 CONFIG6L Table Write Protection bit (Block 2)
1 = Code memory not write protected
0 = Code memory write protected
WRT3 CONFIG6L Table Write Protection bit (Block 3)
1 = Code memory not write protected
0 = Code memory write protected
WRT4(2) CONFIG6L Table Write Protection bit (Block 4)
1 = Code memory not write protected
0 = Code memory write protected
WRT5(2) CONFIG6L Table Write Protection bit (Block 5)
1 = Code memory not write protected
0 = Code memory write protected
WRT6(2) CONFIG6L Table Write Protection bit (Block 6)
1 = Code memory not write protected
0 = Code memory write protected
WRT7(2) CONFIG6L Table Write Protection bit (Block 7)
1 = Code memory not write protected
0 = Code memory write protected
WRTD CONFIG6H Table Write Protection bit (Data EEPROM)
1 = Data EEPROM not write protected
0 = Data EEPROM write protected
WRTB CONFIG6H Table Write Protection bit (Boot Block)
1 = Boot block not write protected
0 = Boot block write protected
WRTC CONFIG6H Table Write Protection bit (Configuration registers)
1 = Configuration registers not write protected
0 = Configuration registers write protected
Note 1: Unimplemented in PIC18F6X20 (64-pin) devices; maintain this bit set.
2: Unimplemented in PIC18FX620 devices; maintain this bit set.
3: PIC18F8520/8620 devices only.

 2010 Microchip Technology Inc. DS39583C-page 29

PIC18FXX20
TABLE 5-3: PIC18FXX20 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Configuration
Bit Name Description
Words

EBTR0 CONFIG7L Table Read Protection bit (Block 0)

1 = Code memory not protected from table reads executed in other
blocks
0 = Code memory protected from table reads executed in other blocks
EBTR1 CONFIG7L Table Read Protection bit (Block 1)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTR2 CONFIG7L Table Read Protection bit (Block 2)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTR3 CONFIG7L Table Read Protection bit (Block 3)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTR4(2) CONFIG7L Table Read Protection bit (Block 4)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTR5(2) CONFIG7L Table Read Protection bit (Block 5)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTR6(2) CONFIG7L Table Read Protection bit (Block 6)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTR7(2) CONFIG7L Table Read Protection bit (Block 7)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTRB CONFIG7H Table Read Protection bit (Boot Block)
1 = Boot block not protected from Table Reads executed in other blocks
0 = Boot block protected from Table Reads executed in other blocks
DEV10:DEV3 DEVID2 Device ID bits
These bits are used with the DEV2:DEV0 bits in the DEVID1 register to
identify part number.
DEV2:DEV0 DEVID1 Device ID bits
These bits are used with the DEV10:DEV3 bits in the DEVID2 register to
identify part number.
REV4:REV0 DEVID1 These bits are used to indicate the revision of the device.
Note 1: Unimplemented in PIC18F6X20 (64-pin) devices; maintain this bit set.
2: Unimplemented in PIC18FX620 devices; maintain this bit set.
3: PIC18F8520/8620 devices only.

DS39583C-page 30  2010 Microchip Technology Inc.

 PIC18FXX20
5.4 Embedding Configuration Word 5.5 Checksum Computation
Information in the HEX File The checksum is calculated by summing the following:
To allow portability of code, a PIC18FXX20 • The contents of all code memory locations
programmer is required to read the configuration word • The configuration word, appropriately masked
locations from the HEX file. If configuration word
• ID locations
information is not present in the HEX file, then a simple
warning message should be issued. Similarly, while The Least Significant 16-bits of this sum are the
saving a HEX file, all configuration word information checksum.
must be included. An option to not include the Table 5-4 (pages 32 through 37) describes how to
configuration word information may be provided. When calculate the checksum for each device.
embedding configuration word information in the HEX
file, it should start at address 300000h. Note 1: The checksum calculation differs depend-
ing on the code protect setting. Since the
Microchip Technology Inc. feels strongly that this
code memory locations read out differ-
feature is important for the benefit of the end customer.
ently, depending on the code protect set-
ting, the table describes how to
manipulate the actual code memory val-
ues to simulate the values that would be
read from a protected device. When cal-
culating a checksum by reading a device,
the entire code memory can simply be
read and summed. The configuration
word and ID locations can always be
read.

 2010 Microchip Technology Inc. DS39583C-page 31

PIC18FXX20
TABLE 5-4: CHECKSUM COMPUTATION
0xAA at 0
Code Blank
Device Checksum and Max
Protect Value
Address
None SUM(0000:07FF)+SUM(0800:1FFF)+SUM(2000:3FFF)+ 05A8 04FE
SUM(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0000)+(CFGW3H & 0002)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 00FF)+(CFGW5H & 00C0)+
(CFGW6L & 00FF)+(CFGW6H & 00E0)+(CFGW7L & 00FF)+
(CFGW7H & 0040)
Boot SUM(0800:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+ 077F 734
Block SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+
(CFGW2L & 000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+
(CFGW3H & 0002)+(CFGW4L & 0085)+(CFGW4H & 0000)+
(CFGW5L & 00FF)+(CFGW5H & 00C0)+(CFGW6L & 00FF)+
PIC18F6520 (CFGW6H & 00E0)+(CFGW7L & 00FF)+(CFGW7H & 0040)+
SUM(IDs)
Boot/ SUM(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+ 857C 8531
Block1/ (CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
Block2 (CFGW3L & 0000)+(CFGW3H & 0002)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 00FF)+(CFGW5H & 00C0)+
(CFGW6L & 00FF)+(CFGW6H & 00E0)+(CFGW7L & 00FF)+
(CFGW7H & 0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+ 480 048A
(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H & 0002)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)+SUM(IDs)

Legend: Item Description

CFGW = Configuration Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND

DS39583C-page 32  2010 Microchip Technology Inc.

 PIC18FXX20
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
0xAA at 0
Code Blank
Device Checksum and Max
Protect Value
Address
None SUM(0000:01FF)+SUM(0200:3FFF)+SUM(4000:7FFF)+ 02D8 022E
SUM(8000:BFFF)+SUM(C000:FFFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+
(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+
(CFGW7H & 0040)
Boot SUM(0200:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+ 04AF 455
Block SUM(C000:FFFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+
(CFGW2L & 000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+
(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H & 0000)+
(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L & 000F)+
PIC18F6620 (CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)+
SUM(IDs)
Boot/ SUM(8000:BFFF)+SUM(C000:FFFF)+(CFGW1L & 0000)+ 82AC 8252
Block1/ (CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
Block2 (CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+
(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+
(CFGW7H & 0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+ 02A0 029B
(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 000F)+
(CFGW5H & 00C0)+(CFGW6L & 000F)+(CFGW6H & 00E0)+
(CFGW7L & 000F)+(CFGW7H & 0040)+SUM(IDs)

Legend: Item Description

CFGW = Configuration Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND

 2010 Microchip Technology Inc. DS39583C-page 33

PIC18FXX20
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
0xAA at 0
Code Blank
Device Checksum and Max
Protect Value
Address
None SUM(0000:01FF)+SUM(0200:3FFF)+SUM(4000:7FFF)+ 05A8 04FE
SUM(8000:BFFF)+SUM(C000:FFFF)+SUM(10000:13FFF)+
SUM(14000:17FFF)+SUM(18000:1BFFF)+SUM(1C000:1FFFF)+
(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)
Boot SUM(0200:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+ 077F 0734
Block SUM(C000:FFFF)+SUM(10000:13FFF)+SUM(14000:17FFF)+
SUM(18000:1BFFF)+SUM(1C000:1FFFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 00FF)+(CFGW5H & 00C0)+
PIC18F6720 (CFGW6L & 00FF)+(CFGW6H & 00E0)+(CFGW7L & 00FF)+
(CFGW7H & 0040)+SUM(IDs)
Boot/ SUM(8000:BFFF)+SUM(C000:FFFF)+SUM(10000:13FFF)+ 857C 8531
Block1/ SUM(14000:17FFF)+SUM(18000:1BFFF)+SUM(1C000:1FFFF)+
Block2 (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+ 480 048A
(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)+SUM(IDs)

Legend: Item Description

CFGW = Configuration Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND

DS39583C-page 34  2010 Microchip Technology Inc.

 PIC18FXX20
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
0xAA at 0
Code Blank
Device Checksum and Max
Protect Value
Address
None SUM(0000:07FF)+SUM(0800:1FFF)+SUM(2000:3FFF)+ 05AA 500
SUM(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0000)+(CFGW3H & 0002)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 00FF)+(CFGW5H & 00C0)+
(CFGW6L & 00FF)+(CFGW6H & 00E0)+(CFGW7L & 00FF)+
(CFGW7H & 0040)
Boot SUM(0800:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+ 783 071A
Block SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+
(CFGW2L & 000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+
(CFGW3H & 0002)+(CFGW4L & 0085)+(CFGW4H & 0000)+
(CFGW5L & 00FF)+(CFGW5H & 00C0)+(CFGW6L & 00FF)+
PIC18F8520 (CFGW6H & 00E0)+(CFGW7L & 00FF)+(CFGW7H & 0040)+
SUM(IDs)
Boot/ SUM(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+ 8580 8517
Block1/ (CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
Block2 (CFGW3L & 0000)+(CFGW3H & 0002)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 00FF)+(CFGW5H & 00C0)+
(CFGW6L & 00FF)+(CFGW6H & 00E0)+(CFGW7L & 00FF)+
(CFGW7H & 0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+ 484 470
(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H & 0002)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)+SUM(IDs)

Legend: Item Description

CFGW = Configuration Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND

 2010 Microchip Technology Inc. DS39583C-page 35

PIC18FXX20
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
0xAA at 0
Code Blank
Device Checksum and Max
Protect Value
Address
None SUM(0000:01FF)+SUM(0200:3FFF)+SUM(4000:7FFF)+ 035B 02B1
SUM(8000:BFFF)+SUM(C000:FFFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0083)+(CFGW3H & 0001)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+
(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+
(CFGW7H & 0040)
Boot SUM(0200:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+ 052E 04D4
Block SUM(C000:FFFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+
(CFGW2L & 000F)+(CFGW2H & 000F)+(CFGW3L & 0083)+
(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H & 0000)+
(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L & 000F)+
PIC18F8620 (CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)+
SUM(IDs)
Boot/ SUM(8000:BFFF)+SUM(C000:FFFF)+(CFGW1L & 0000)+ 832B 82D1
Block1/ (CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
Block2 (CFGW3L & 0083)+(CFGW3H & 0001)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+
(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+
(CFGW7H & 0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+ 031F 031A
(CFGW2H & 000F)+(CFGW3L & 0083)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 000F)+
(CFGW5H & 00C0)+(CFGW6L & 000F)+(CFGW6H & 00E0)+
(CFGW7L & 000F)+(CFGW7H & 0040)+SUM(IDs)

Legend: Item Description

CFGW = Configuration Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND

DS39583C-page 36  2010 Microchip Technology Inc.

 PIC18FXX20
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
0xAA at 0
Code Blank
Device Checksum and Max
Protect Value
Address
None SUM(0000:01FF)+SUM(0200:3FFF)+SUM(4000:7FFF)+ 062B 581
SUM(8000:BFFF)+SUM(C000:FFFF)+SUM(10000:13FFF)+
SUM(14000:17FFF)+SUM(18000:1BFFF)+SUM(1C000:1FFFF)+
(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0083)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)
Boot SUM(0200:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+ 07FE 07A4
Block SUM(C000:FFFF)+SUM(10000:13FFF)+SUM(14000:17FFF)+
SUM(18000:1BFFF)+SUM(1C000:1FFFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0083)+(CFGW3H & 0001)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 00FF)+(CFGW5H & 00C0)+
PIC18F8720 (CFGW6L & 00FF)+(CFGW6H & 00E0)+(CFGW7L & 00FF)+
(CFGW7H & 0040)+SUM(IDs)
Boot/ SUM(8000:BFFF)+SUM(C000:FFFF)+SUM(10000:13FFF)+ 85FB 85A1
Block1/ SUM(14000:17FFF)+SUM(18000:1BFFF)+SUM(1C000:1FFFF)+
Block2 (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0083)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)+SUM(IDs)
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+ 04FF 04FA
(CFGW2H & 000F)+(CFGW3L & 0083)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)+SUM(IDs)

Legend: Item Description

CFGW = Configuration Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND

5.6 Embedding Data EEPROM

Information In the HEX File
To allow portability of code, a PIC18FXX20
programmer is required to read the data EEPROM
information from the HEX file. If data EEPROM
information is not present, a simple warning message
should be issued. Similarly, when saving a HEX file, all
data EEPROM information must be included. An option
to not include the data EEPROM information may be
provided. When embedding data EEPROM information
in the HEX file, it should start at address F00000h.
Microchip Technology Inc. believes that this feature is
important for the benefit of the end customer.

 2010 Microchip Technology Inc. DS39583C-page 37

PIC18FXX20
6.0 AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: 25C is recommended
Param
Sym Characteristic Min Max Units Conditions
No.
D110 VIHH High Voltage Programming Voltage on 9.00 13.25 V
MCLR/VPP
D110A VIHL Low Voltage Programming Voltage on 2.00 5.50 V
MCLR/VPP
D111 VDD Supply Voltage During Programming 2.00 5.50 V Normal programming
4.50 5.50 V Bulk erase operations
D112 IPP Programming Current on MCLR/VPP — 300 A
D113 IDDP Supply Current During Programming — 10 mA
D031 VIL Input Low Voltage VSS 0.2 VDD V
D041 VIH Input High Voltage 0.8 VDD VDD V
D080 VOL Output Low Voltage — 0.6 V IOL = 8.5 mA @ 4.5V
D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA @ 4.5V
D012 CIO Capacitive Loading on I/O pin (SDATA) — 50 pF To meet AC specifications

P1 TR MCLR/VPP Rise Time to enter — 1.0 s (Note 1)

Program/Verify mode
P2 Tsclk Serial Clock (SCLK) Period 100 — ns
P2A TsclkL Serial Clock (SCLK) Low Time 40 — ns
P2B TsclkH Serial Clock (SCLK) High Time 40 — ns
P3 Tset1 Input Data Setup Time to Serial Clock  15 — ns
P4 Thld1 Input Data Hold Time from SCLK 15 — ns
P5 Tdly1 Delay between 4-bit Command and 40 — ns
Command Operand
P5A Tdly1a Delay between 4-bit Command 40 — ns
Operand and next 4-bit Command
P6 Tdly2 Delay between Last SCLK  of 20 — ns
Command Byte to First SCLK  of Read
of Data Word
P9 Tdly5 SCLK High Time 1 — ms
(minimum programming time)
P10 Tdly6 SCLK Low Time after Programming 5 — s
(high voltage discharge time)
P11 Tdly7 Delay to allow Self-Timed Data Write or 10 — ms
Bulk Erase to occur
P11A Tdrwt Data Write Polling Time 4 — ms
P12 Thld2 Input Data Hold Time from MCLR/VPP  2 — s
P13 Tset2 VDD Setup Time to MCLR/VPP  100 — ns
P14 Tvalid Data Out Valid from SCLK  10 — ns
P15 Tset3 PGM Setup Time to MCLR/VPP  2 — s

Note 1: Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program
executions to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL, and XT modes only)
+ 2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only)
where TCY is the Instruction Cycle Time, TPWRT is the Power-up Timer Period, and TOSC is the Oscillator Period.
For specific values, refer to the Electrical Characteristics section of the Device Data Sheet for the particular device.

DS39583C-page 38  2010 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
rfPIC and UNI/O are registered trademarks of Microchip
MICROCHIP MAKES NO REPRESENTATIONS OR
Technology Incorporated in the U.S.A. and other countries.
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip
QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard,
arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
hold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
intellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2010 Microchip Technology Inc. DS39583C-page 39

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01/05/10

DS39583C-page 40  2010 Microchip Technology Inc.