A B C D E

c_res_clk

CLOCK clock clock2 CLOCK2

i_n_reset N_RESET_OUT
n_reset
4 4

PHI PHI
phi n_modes
mode_reset

res_clk

i_n_modes
mode_reset
c_modes97

n_modes mode_reset
phi
n_reset Latches mode at reset time.
n_mreq
Could use pins of the bigger XC2S200
n_wr
I/O should not be a problem.
D_MEM_0[7-0]

kbd_col[4-0] c_busses
mode_rom0 oe_cpu
mode_rom0 mode_rom0 oe_cpu
mode_romp[1-0] oe_mem
mode_romp[1-0] mode_romp[1-0] oe_mem
mode_ram[1-0]
mode_ram[1-0] mode_ram[1-0]
addr[15-0] mode_chr13
data[7-0] mode_v_inv
3 3
modes97 a_mem_h[14-13] A_MEM_H[14-13]
A[15-0] a_cpu[15-0] a_mem_l[8-0] A_MEM_L[8-0]
D_CPU_I[7-0]
D_CPU_O[7-0] d_cpu_o[7-0]
d_mem_i[7-0] D_MEM_I[7-0]
c_io81
KBD_COL[4-0] d_kbd[7-0]
kbd_col[4-0] d_kbd[7-0] d_kbd[7-0]
USA_UK d_kbd_enable
usa_uk d_kbd_enable d_kbd_enable
TAPE_IN tape_in
A[1-0]
address[1-0]

n_reset
n_iorq
n_rd vsync
n_wr nmi_enable

io81
n_rom_cs N_ROM_CS

n_ram_cs N_RAM_CS
N_RFSH n_rfsh
N_MREQ n_mreq
N_IORQ n_iorq
N_RD n_rd
N_WR n_wr
N_M1 n_m1
2 2
nmi_enable
video_address[8-0]
vsync
video_mem
mode_v_inv
fake_cpu
mode_chr13
busses
d_mem[7-0]
This is a rough sketch showing signal paths inside the FPGA for Kai's LCD-enhanced ZX81 design.
Do not take as an exact representation!
Inputs generally on left of blocks, outputs on the right.
c_video81 Extra processes in zx97.vhd multiplex data moving from the CPU to memory.
video_address[8-0]
d_mem[7-0] video_address[8-0]
video_mem
mode_chr13 video_mem
fake_cpu
mode_video_inv fake_cpu
vsync
nmi_enable n_nmi N_NMI
n_m1
n_iorq n_wait N_WAIT
n_mreq
phi i_video VIDEO
phi video
clock
N_HALT n_halt i_n_sync N_SYNC
n_halt n_sync

c_lcd97
A[15-13] LCD_D[3-0]
a_cpu[15-13] video d_lcd[3-0]
1 n_sync cp1 LCD_CP1 1
video81 cp2 LCD_CP2
clock s LCD_S

lcd97
Optional, for LCD output.

Title
ZX81 FPGA VHDL Architecture

Size Document Number Rev

A3 ZX97 0.1

Date: Wednesday, December 19, 2001 Sheet 1 of 1

A B C D E