Register popular ■ 256bytes of RAM

A (Accumulator): For all arithmetic and logic instructions • 4 timers

B, R0, R1, R2, R3, R4, R5, R6, R7 ■ One serial port
DPTR (data pointer) ■ 8 interrupt sources
MOV destination, source ;copy source to dest. ■ 8K bytes of on-chip ROM
➤ Value (#)loaded directly registers A, B, or RO - R7 OTP (one-time-programmable) version of 8051
The unit of data size The 8051 family has the largest number of diversified (multiple source) suppliers:
Bit: a binary digit that can have the value 0 or 1 Intel (original); Atmel; Philips/Signetics; AMD; Infineon (formerly Siemens); Matra;
➤ Byte : 8 bits Dallas Semiconductor/Maxim
Nibble: half of a bye, or 4 bits AT89C51 from Atmel Corporation
Word: two bytes, or 16 bits Flash (erase before write)
The terms used to describe amounts of memory in IBM PCs and ■ ROM burner that supports flash
compatibles ■ A separate eraser is not needed
➤ Kilobyte (K): 210 bytes 8751(UV-EPROM)
Megabyte (M): 220 bytes, over 1 million • PROM burner
Gigabyte (G): 230 bytes, over 1 billion • eraser takes 20
Terabyte (T): 240 bytes, over 1 trillion PC 16 bits wide
CPU (Central Processing Unit) can access program addresses 0000 to FFFFH, total 64K bytes of code
➤ Execute information stored in memory 8751,AT89C51(4KB);DS89C420/30(16KB);DS5000-32(32KB)
I/O (Input/output) devices ORG to indicate the beginning of the address
➤ Provide a means of communicating with CPU END indicates to the assembler the end of the source (asm) file
■ Memory EQU (equate): to define a constant without occupying a memory location
RAM (Random Access Memory) -temporary storage of programs that program status word (PSW) register, referred the flag register, is an 8 bit register:
computer is running • 4: CY (carry), AC (auxiliary carry), P (parity), and OV (overflow)
• The data is lost when computer is off PSW3 and PSW4 are designed as RSO and RS1, and are used to change the bank
ROM (Read Only Memory) - contains programs and information 128 bytes of RAM /8051: 00 to 7FH. Divided -> 3:
essential to operation of the computer •00->1F(32byte): for register banks and the stack
• The information cannot be changed by use, and is not lost when •20H->2FH(16byte): for bit-addressable read/write memory
power is off •90H->7FH(80byte): for read and write storage, called scratch pad
-It is called nonvolatile memory D4 and D3 / PSW to select the desired register bank
The CPU is connected to memory and I/O through strips of wire called Use bit-addressable SETB and CLR to access PSW.3,4
a bus➤ Carries information from place to place Stack(8bit:00->FFH) is a section / RAM used by CPU to store in4(data or addr)
• Address bus((memory or I/O) recognized by CPU, it must be assigned temporarily; Access by SP R;
an address, address assigned to a given device must be unique,The 8051 is powered up ->SP value 07
CPU puts the address on the address bus, and the decoding circuitry storing / CPU R. / stack : PUSH
finds the device,2^x, unidirectional) Subroutines used to perform tasks need performed frequently
• Data bus(The CPU gets data from the device or sends data to it, #ACALL&LCALL: (use A > L to save numb of program ROM space
bidirectional) •LCALL anywhere within the 64K byte address
 • Control bus(Provides read or write signals to device to indicate if the •ACALL a 2K-byte range
CPU is asking for information or sending it information). The length /machine cycle depends frequency / crystal oscillator connected to
 ROM provides information that is fixed and permanent 8051(12 oscillator periods)
Registers: to store inf4 temporarily 2 factors can affect the accuracy / delay:crystal freq, 8051 design
embedded system is to decrease power consumption &space PIN
Meeting hand efficiently and cost effectively: Speed; Packaging; PSEN-program store enable(output pin)+OE/ROM
Power consumption; The amount of RAM and ROM on chip; The ALE-addr latch enable(active-high):
number of I/O pins and the timer on chip; How easy to upgrade to • P0 provide addr & data
higher-performance or lower power-consumption versions; Cost per •ALE=0->data D0-D7
unit •ALE=1->addr D0-A7
8051 -8-bit processor PO is an open drain, unlike P1, P2, and P3
64K Code (ROM);64k data (RAM) P0 an input, the port by writing 1 to all the bits
8051 had bit-addressable:TCON, IE, PSW, P0,1,2,3
■ 128 bytes of RAM P0 (Port 0) ✓ A dual – purpose port on32-9
■ 4K bytes of on-chip ROM A multiplexed address anddata bus
• Two 16bit timers TMOD is a 8-bit register
■ One serial port ➤ lower 4 bits for Timer 0
• Four I/O ports, each 8 bits wide ➤ upper 4 bits for Timer 1
■ 6 interrupt sources •lower 2 bits are used to set the timer mode
8052 had •upper 2 bits to specify the operation
TIMER generate time delay