10/7/2024

MICROPROCESSOR

MICROPROCESSOR
 Microprocessor is a logic device is used in digital
systems and perform

Arthematic
logic
Control

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MICROPROCESSOR UNIT

ALU

AC

PC CS

ID
AR

DR

MICROPROCESSOR UNIT

AC
 Accumulator

 It is the most important unit as it holds the

output of ALU operations and hold the final
results of arthematic or logic operations.

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MICROPROCESSOR UNIT

DR
 Data Register

 It is a temporary register to store data going or

coming to data bus (data bus must be connected
to the data register).

MICROPROCESSOR UNIT

AR
 Address Register

 It is a temporary storage for the address going to

address bus (address bus must be connected to
the address register).

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MICROPROCESSOR UNIT

PC
 Program Counter

 It controls the sequence in which instructions in

the program are performed

MICROPROCESSOR UNIT

ID
 Instruction Decoder

 It decides which operation is to be performed

(opcode, operand).

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MICROPROCESSOR UNIT

CS
 Controller Sequencer

 It arranges all operations that required to

perform the specific program to be done.

MICROPROCESSOR UNIT

ALU Arthematic logic unit

 perform Arthematic and logic operations on the

data word that are delivered to it.

 It has two main inputs AC

DR

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MICROCOMPUTER

Microprocessor

Memory

Microcomputer

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MICROCOMPUTER UNIT

ALU

AC

PC CS

ID
AR

RAM
DR

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MICROPROCESSOR UNIT

RAM
 Random Access Memory

 The memory consists from no of registers used to

store data.
 Each register consists

from no of digits.

Memory

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MICROPROCESSOR UNIT
 The memory need to work
Address Bus :- select which of registers “ memory
location” to get the data from it.

Data Bus :- get the data from the specified location

loaded previously on the address bus.
Location--- 0 0
Address Bus 1 25 Data Bus
“1“ 2 “25”
3
4
5

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MEMORY SIZE
= NO. OF LOCATIONS * NO. OF BITS OF EACH
LOCATION

0 1 2 3 4 5 6
0
1
2
3
4
5
6
7
8

9 locations * 7 bits
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FETCH & EXECUTE

Fetch phase : - it means reading &decoding of the
instructions.
- it consists of same series of
operations.

Execute phase:- it means the way of Microprocessor

will perform the program.
- it consists of different sequences of
operations which depend on the type of instruction that
will be executed.

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ADDRESSING MODES
it refers to the methods by which the instructions
addresses it’s operand

1 •Inherent
2 •Immediate
3 •Direct

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ADDRESSING MODES
Inherent Immediate Direct
Op-code doesn't Operand after op- Address of operand
need to operand code directly after op-code directly
1-byte (location) 2-byte (location) 2-byte (location)

Fetch decode Fetch decode Fetch decode

Obtain operand Obtain

Execute address operand

Execute Decode Address

Obtain operand

Execute

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INSTRUCTIONS SET
- is the orders or operations that computer can be
told to perform as (mov, add, sub, mul)

Move ADD

• Mov the • Add the

content of the content of the
memory memory
location or location to the
register accumulator

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MOVE INSTRUCTION
- data transfer instruction -

Immediate Direct
• Mov Des, # Data • Mov Des, address of data

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ADD INSTRUCTION
- used for addition operation

AC+DR→AC

ADD A , Memory location

#Data
@Address

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PROGRAM
- Mov a, #20h
- Add a,#20h
- Mov 20h,a

To run this program let’s see first how it could be written

through the memory:-

Assume -the op-code of Mov Instruction=50h (Immediate)

- the op-code of Add Instruction=64h (Immediate)
- the op-code of Mov Instruction=51h (Direct)

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PROGRAM
M.Loc Machine Code
00 50 Mov op-code
01 20 operand
02 64 Add op-code
03 20 operand
04 51 Mov op-code
05 20 address

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FETCHING PHASE

ALU

AC

PC 00 50 CS

20
ID
AR
64

20 DR

51

20

25

FETCHING PHASE

ALU

AC PCAR Inc PC

PC 01 50 CS

20
ID
AR 00
64

20 DR

51

20

26

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FETCHING PHASE

ALU

AC M[AR]DR

PC 01 50 CS

20
ID
AR 00
64

20 DR 50

51

20

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FETCHING PHASE

ALU

AC DRID

PC 01 50 CS

20
ID 50
AR 00
64

20 DR 50

51

20

28

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FETCHING PHASE

ALU
CS will perform
what will be need
AC
to move data

PC 01 50 CS Mov(Im)

20
ID 50
AR 00
64

20 DR 50

51

20

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EXECUTION PHASE

ALU

AC

PC 02 50 CS

20
ID
AR 01
64

20 DR

51

20

30

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EXECUTION PHASE

ALU

AC M[AR]DR

PC 02 50 CS

20
ID
AR 01
64

20 DR 20

51

20

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EXECUTION PHASE

ALU

AC 20 DRAC

PC 02 50 CS

20
ID
AR 01
64

20 DR 20

51

20

32

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FETCHING PHASE

ALU

AC 20 PCAR Inc PC

PC 03 50 CS

20
ID
AR 02 64

20 DR

51

20

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FETCHING PHASE

ALU

AC 20 M[AR]DR

PC 03 50 CS

20
ID
AR 02
64

20 DR 64

51

20

35

FETCHING PHASE

ALU

AC 20 DRID

PC 03 50 CS

20
ID 64
AR 02
64

20 DR 64

51

20

36

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FETCHING PHASE

ALU
CS will perform
what will be need
AC 20
to ADD data

PC 03 50 CS Add(Im)

20
ID 64
AR 02
64

20 DR 64

51

20

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EXECUTION PHASE

ALU

AC 20 M[AR]DR

PC 04 50 CS

20
ID
AR 03
64

20 DR 20

51

20

38

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EXECUTION PHASE

20
ALU

20 AC,DRALU
AC 20

PC 04 50 CS

20
ID
AR 03
64

20 DR 20

51

20

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EXECUTION PHASE

ALU 20+20=40

AC 40

PC 04 50 CS

20
ID
AR 03
64

20 DR 20

51

20

40

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FETCHING PHASE

ALU

AC 40 PCAR Inc PC

PC 05 50 CS

20
ID
AR 04
64

20 DR

51

20

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FETCHING PHASE

ALU

AC 40 M[AR]DR

PC 05 50 CS

20
ID
AR 04
64

20 DR 51

51

20

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FETCHING PHASE

ALU

AC DRID

PC 05 50 CS

20
ID 51
AR 04
64

20 DR 51

51

20

44

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FETCHING PHASE

ALU
CS will perform
what will be need
AC 40
to move data

PC 05 50 CS Mov(D)

20
ID 51
AR 04
64

20 DR 51

51

20

45

EXECUTION PHASE

ALU

AC PCAR Inc PC

PC 06 50 CS

20
ID
AR 05
64

20 DR

51

20

46

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EXECUTION PHASE

ALU

AC 40

PC 06 50 CS

20
ID
AR 05
64

20 DR

51

20

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EXECUTION PHASE

ALU

M[AR]AR ACDR
AC 40

PC 06 50 CS

20
ID
AR 20
64

20 DR 40

51

20

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EXECUTION PHASE

ALU

AC 40
DRM[AR]

PC 06 CS

ID
AR 20

DR 40

20 40

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