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HW 1 Sol S04

The document contains solutions to various homework problems related to computer architecture and performance metrics from CS152 Spring 2004. Key calculations include yield equations, cycles per instruction (CPI), and MIPS for different machines, highlighting improvements in performance and defect rates over time. Additionally, it discusses state transitions and logic equations for a machine's operation, demonstrating how to optimize performance through careful analysis and calculations.

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22 views5 pages

HW 1 Sol S04

The document contains solutions to various homework problems related to computer architecture and performance metrics from CS152 Spring 2004. Key calculations include yield equations, cycles per instruction (CPI), and MIPS for different machines, highlighting improvements in performance and defect rates over time. Additionally, it discusses state transitions and logic equations for a machine's operation, demonstrating how to optimize performance through careful analysis and calculations.

Uploaded by

yoursugardaddy229
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CS152 Homework 1 Solutions – Spring 2004

1.51

Yield = 1 / ((1 + (Defects per area * Die Area / 2))^2)

Thus, if die area increases, defects per area must decrease.

1.52

Solving the yield equation for Defects per area, we get:

Defects per area = (1 / (sqrt(yield) – 1) * (2 / Die Area)

1.53

In 1980, the yield = 48% and the Die Area = 0.16 from figure 1.31.
In 1992, the yield = 48% and the Die Area = 0.97 from figure 1.31.

Thus,

Defects per area in 1980 = (1 / (sqrt(0.48) – 1) * (2 / .16) = 5.5 / unit area (in sq. cm)
Defects per area in 1992 = (1 / (sqrt(0.48) – 1) * (2 / .97) = .914 / unit area (in sq. cm)

Improvement = 5.5 / .914 = 601.7% improvement.

2.3

If you get confused in these questions, just remember to do unit analysis.

CPI M1 = 10 seconds * (200e6 cycles / sec) * (1 / 200e6 instructions) = 10 cycles per


instruction

CPI M2 = 5 seconds * (300e6 cycles / sec) * (1 / 160e6 instructions) = 9.375 cycles per
instruction

2.15

MIPS = Instruction Count / (Execution time * 10^6)

Since Execution Time = Instruction Count * CPI * (1 / Clock Cycle)

MIPS = Clock Cycle / (CPI * 10^6)

First we need to find CPI of each machine.


CPI MFP = .1 * 6 + .15 * 4 + .05 * 20 + .7 * 2 = 3.6

CPI MNFP = .1 * 60 + .15 * 40 + .05 *100 + .7 *2 = 18.4

Note that for CPI MNFP, we used 60, 40, and 100 rather than 30, 20, and 50. This is
because it takes 30 integer instructions for a FP multiply, and each of those 30 integer
instructions takes 2 clock cycles. Thus 30 * 2 = 60. This holds for FP add and divide as
well.

MIPS MFP = 1000e6 / (3.6 * 10^6) = 277.78

MIPS MNFP = 1000e6(18.4*10^6) = 54.3

2.16

Since 10% of the instructions are FP mults, we know that there are .1 * 300e6 number of
floating point multiply instructions. We can similarily find the number of FP add, FP
divide, and integer instructions.

= (.1 * 300e6 * 30) + (.15 * 300e6 * 20) + (.05 * 300e6 * 40) + (.7 * 300e6) = 2.76e6.

2.18

CPI a = (2 * .4) + (3 * .25) + (3 * .25) + (5 *.1) = 2.8 CPI


CPI b = (2 * .4) + (2 * .25) + (3 * .25) + (4 * .1) = 2.45 CPI

Note that CPI does not include clock cycles at all!!

2.24

Only calculated for the hardware improvement (2.18);

Performance of Mbase = 500e6 / (2.8 * 10^6) = 178 MIPS


Performance of Mopt = 600e6 / (2.45 * 10^6) = 245 MIPS

This is a performance gain of 245 / 178 = 1.37, or 37% improvement in 6 months.

In the 6 months necessary to optimize, CPI performance will increase by 1.034 ^ 6 = 1.22,
or 22%. Since the performance gain is more than the normal growth rate of performance,
the optimizations should be done.

2.32

Performance = Inst Count * CPI * Cycle Time


In this case, Inst count is the same for both, so we can drop it. (Assume 1 instruction…or
100…or any number so long as it’s the same, since it’ll cancel out anyway).
It is easier to pick an arbitrary value for Clock Cycle. The easiest number would be 1 Hz,
so the cycle time = 1.

Performance(old) = (.1 * 12 + .9 *4) * 1 = 4.8 seconds


Performance(new) = (.1 * 6 + .9 * 4) * 1.2 = 5.04 seconds

Since performance is worse, we should not proceed with the modification.

2.41

Execution time after improvement = ( 5 sec / 5) + 5 sec = 6 sec.


Speedup = 10 sec / 6 sec = 1.67

2.44

Multiplication: (20 sec / 4) + 80 = 85 sec, Speedup = 100 sec / 85 sec = 1.18


Memory Access: (50 sec / 2) + 50 = 75 sec, Speedup = 100 sec / 75 sec= 1.33
Both: (20 sec / 4) + (50 sec / 2) + 30 = 60 sec, Speedup = 100 sec / 60 sec = 1.67

B.15

The even parity function will output a 1 whenever there are an even numbers of 1 in the
input, and 0 otherwise.

A B C D Out
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
B.21

Note that the machine simply changes state every clock cycle.

Mid1State
Left = 0
Middle =1
Right = 0

RightState
LeftState
Left = 0
Left = 1 Middle =0
Middle =0 Right = 1
Right = 0

Mid2State
Left = 0
Middle =1
Right = 0

B.22

First, we do state assignments:


LeftState = 00
Mid1State = 01
RightState = 11
Mid2State = 10

Note that we picked RightState to be 11. This makes it so that each transition only
involves one of the 2 state bits to change. This will make our logic simpler later. If you
picked 10 for RightState and 11 for Mid2State, your logic equations may be more
complex (and require more gates).

CS1 CS0 NS1 NS0


0 0 0 1
0 1 1 1
1 0 0 0
1 1 1 0

Solving for NS1 and NS0, we get as our next state equations:

NS1 = CS0, and NS0 = ~CS1.


Our output table looks like this:
CS1 CS0 Left Middle Right
0 0 1 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1

Thus (by inspection),

Left = ~CS1 • ~CS0


Middle = CS1 ⊕ CS0
Right = CS1 • CS0

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