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Cst202 Computer Organization and Architecture May 2024

The document is an examination paper for a B.Tech course on Computer Organization and Architecture, consisting of multiple parts with questions on various topics such as instruction execution cycles, addressing modes, processor organization, and control units. It includes both short answer questions and detailed questions requiring diagrams and explanations. The exam covers multiple modules, each focusing on different aspects of computer architecture.

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axecharlie785
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0% found this document useful (0 votes)
198 views3 pages

Cst202 Computer Organization and Architecture May 2024

The document is an examination paper for a B.Tech course on Computer Organization and Architecture, consisting of multiple parts with questions on various topics such as instruction execution cycles, addressing modes, processor organization, and control units. It includes both short answer questions and detailed questions requiring diagrams and explanations. The exam covers multiple modules, each focusing on different aspects of computer architecture.

Uploaded by

axecharlie785
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

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B 0200csT20205240L C^\
;a lu \*6

Reg No.:

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSI


B.Tech Degree 54 (R,S) / 54 (WP) (n) ISZ (PT) (S, FE) Examination May

Course Code: CST 202


Course Name: Computer Organization and Architecture
Max. Marks: 100 Duration:3 Hours

PART A
(Ansuter oll questions; each question carries 3 marks) Marks

Explain how the PC, IR, MAR and MDR registers are used during the instruction -3

execution cycle.

What information is conveyed by the addressing mode used in an instruction? 3

List any four addressing modes.


Explain shift microoperation with help of examples. 3

Illustrate the processor organisation using scratchpad memory with help of a 3

diagram.
5 Illustrate divide overflow condition in rdstoring division u'ith help of an example. 3
6 Differentiate between unifunction and multifunctionpipelines. 3

7 Draw the block diagram for a control unit using PLA based organization. 3

8. What is the role of next address generator in microprogrammed control 3

organization?
9. Does Direct Memory Access increase the efficiency of processor? Justiff your 3

answer.

l0
" Explain the need for using cache memory within the computer system. .3
PART B
(Answer onefull questionfrom each module, eoch question carries 14 marks)

Module -1
ll a) What do you mean by byte addressable memory? Explain the two different types 7

of byte assignment using diagrams.


b) Illustrate processor organisation using a single bus with help of a diagram. 7

Explain how register transfers and ALU operations are carried out in the single
bus organisation.

Page 1 of 3
0200csr20205240t

12 a) Describe the following addressing modes. giving an example for each: 7

i) Indirect Addressing mode


ii) Immediate Addrdssing mode
iii) Indexed Addressing mode
b) Discuss how instructions are classified based on number of operands or addresses 7

thev use.

Module -2
13 a) What is the role of status register within the processor? Draw the circuit diagram 7

for a basic status register for an 8-bit ALU and explain how the carry and
'
. overflow status bits are set.

b) What is a control word? Explain, using an example, how a control word can be 7

used to speciff a complete instruction.

14 a) Draw the circuit diagram and function table for one stage of the logic unit for a 7

4-bit ALU with following logic operations - AND, O& XOR and NOT. Explain
the working.
b) Illustrate the use of accumulator register. Explain processor organization using 7

accumulator register with help of a diagram.

Module -3
l5 a) Explain the advantage of using an array multiplier. Design a3x2 array multiplier. 7

b) Briefly describe the following with reference to pipelining: 7

I i) Clock period
ii) Speedup

. iii) Efficiency
iv) Throughput
16 . a) Illustrate Booth's Multiplication algorithq with help of a flowchart and an 7

example.
b) Summarize the different techniques used for pipeline hazard resolution. 7

Module -4
17 a) Are
.there
any advantages in using PLA based or microprogrammed control 7
organizations when compared to the hardwired organizations? Explain your
answer.

b) Illustrate, with a diagram, how a microprogram sequencer helps to generate next 7

address in a microprogrammed control organization.

Page 2 of 3
ffif;ffiE24o.t
lE Surunsize, with help of urexunple, the steps involved in dcigning e hsdwired 14

conhol organizaion u*qg ur ffip fbp p€r state rnetlrod.


irr"auu -s
19 a) Explain the basic structrre of a DRAM cell. Why does DRAMs rrccd €onsurt 7

refreshing?
b) Hon, fu the processor rcact wlren an intemrpt is raised by an I/O d€r,be? 7
20 - a) WhafisaR0M?ListardexplainfrreditrerenttypesofROMs. 7
b) What atc two rrofu in u/tich Direct Memory Transfer can operaF? ExplEin 7

their diftrences.
. ri**

{l

Page 3 of3 ?

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