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Cst202 Computer Organization and Architecture, June 2022

This document outlines the examination structure for the Fourth Semester B.Tech Degree in Computer Organization and Architecture, including course code, maximum marks, and duration. It consists of two parts: Part A with short answer questions and Part B with detailed questions from different modules. Topics covered include addressing modes, processor organization, multiplication algorithms, pipeline hazards, and memory organization.

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axecharlie785
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76 views2 pages

Cst202 Computer Organization and Architecture, June 2022

This document outlines the examination structure for the Fourth Semester B.Tech Degree in Computer Organization and Architecture, including course code, maximum marks, and duration. It consists of two parts: Part A with short answer questions and Part B with detailed questions from different modules. Topics covered include addressing modes, processor organization, multiplication algorithms, pipeline hazards, and memory organization.

Uploaded by

axecharlie785
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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B 02000csr2020s2toL

RegNo.:
,ffi s,* UCA r

APJ ABDUL KALAIV{ TECHNOLOGICAL


,mY"\?,
Fourth Semester B.Tech Degree Examination June 2022 (201

.)s"--' i''
\Sii;= .'''
Course Code: CST202
Course Name: Computer Organization and Architecture
Max. Marks: 100 Duration:3 Hours
PART A
(Answer all questions; each question carries 3 marks) Marks

I Describe auto increment and decrement addressing mode with help of 3

example?
2 Name the registers which are connected to both external and internal bus? What 3

are the signals associated with these registers?


3 Write the register transfer logic format for a conditional control statement, Give 3

an example?
4 Discuss the logic used behind the booth multiplication algorithm J

5 Draw a3X2 array multiplier? 3

6 Discuss aboirt pipeline hazards? J


a
7 Write a note on micro-program control? J

8 What are different types of control organization? J


a
9 What are intemrpts, List the sequence of steps following an intemrpt request? J
a
l0 Which design feature of SRAM cells helps in value retention without refresh? J

r PART B
(Answer onefull qaestionfrom each module, eoch question carries 14 marks)
Module -1
I I a) Compare and contrast single bus and multi-bus organization of CPU? 4

b) Write the three-address, two-address and one-address representations of the l0


operation below with relevant assumptions; evi{uate following: '
i, (A+B) * (C+D)
ii, c<- [A] + [B]
12 a) With the help of a neat figure, describe the data path inside the processor? 6

b) Draw the diagram of single bus organization, write the control sequence for the 8
instruction ADD [R2],R3 for the above mentioned single bus organization.
Module -2
13 a) Describe processor organization with diagram using i) scratchpad memory 10

ii) Two-port memory iii) Accumulator register

b) Draw and e;plain about true/complement circuit? 4

Page 1 of 2
02000csr202052LOt

14 a) Give the structure of status register, which is connected to Sbit ALU ' 8

b) Design 4-bit combinationallogic shifter which'will perform the


operation given 6

below with 2 control variable HI&HO?


i) Shrl
ii) clear
iii) Load all bits with I
Module -3

15 a) Draw the flowchart and explain restoring division method with an


example? 6

b) Describe in detail about datahazards and resolution techniques?


8

L6 a) Draw the flowchart of Booth's multiplication


algorithm and multiply -5 X -4 8

using booths algorithm?


execution of the 6
b) Identiff the various types of hazards occuning during the
following program in a pipelined system. Where the pipeline consist
of five
,f
store the
stages, opcode fetch , instruction decode, operand fetch, execution,
result. All stages take equal time duration

MOV [Rl],[R2l
MOV R3,[Rl]
SUB R2,R3
.
ADD R1,R3
CALL 5OOO
MOV R2.R3
Module 4
17 a) With the help of a diagram explain the functioning of a micro-program l0
sequencer in a micro-programmed controlled processor?

b) Compare instruction formats of horizontal and vertical microinstructions? 4

18 a) Explain the organization of micro-programmed computer with a block


8

--r'
dialram?
b) Explain with an example one flip-flop per state method of control
organization? 6

Modulg-S r

19 a) Explain in detail about the mechanisms for accessing VO devices? 9

b) Discuss about different types of read only memories? 5

20 a) Explain internal organization of I K X 8 memory chip with suitable diagram 5

b) How does the various mapping scheme present in cache memory differ from each 9

other.
***

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