ELECTRONICS AND COMMUNICATION ENGINEERING

Lecture Notes on

VLSI DESIGN

Year III Semester VI

 Unit 1: INTRODUCTION

Introduction: Introduction to VLSI and VLSI fabrication- Introduction to power reduction

techniques-Dynamic Power Reduction-Static Power Reduction- CMOS inverter– propagation
delays – power dissipation - Stick Diagram. MOS layers - design rules and layout- choice of layers.

Introduction to VLSI
 It means packing a very large number of transistors into an IC.
 VLSI – Very Large Scale Integration.
 Maximum of 10,00,000 transistors per chip can be fabricated in VLSI technology.
 Classification of IC
o SSI – Small Scale Integration
o MSI – Medium Scale Integration
o LSI – Large Scale Integration
o VLSI - Very Large Scale Integration
o ULSI – Ultra Large Scale Integration
o GSI – Gaint Scale Integration
Transistors
1. BJT
a. NPN
b. PNP
2. UJT
a. JFET
b. MOSFET
i. N – Channel
1. Enhancement mode
2. Depletion mode
ii. P – Channel
1. Enhancement mode
2. Depletion mode

Basics of transistors
NMOS
• Gate oxide body stack looks like a capacitor
• Gate and body are conductors
• SiO2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor, even
though gate material changed to poly silicon
• Recent gate material in nano scale processes is back to metal
Operation
 Body (bulk) is commonly tied to Ground (0 V)
When the gate is at a low voltage gate is at a low voltage
• P-type body is at low voltage
• Source-body and drain-body diodes are OFF
• No current flows, transistor is OFF
When the gate is at a high voltage
• Positive charge on gate of MOS capacitor
• Negative charge attracted to body
• Inverts a channel under gate to n-type
• Now electrons can flow through n-type
• Silicon from source through channel to drain, transistor is ON
PMOS transistor
• Similar to MOS transistor, but doping and voltages reversed
• Body tied to high voltage (VDD)
• Gate low: transistor ON
• Gate high: transistor OFF
• Bubble indicates inverted behavior

IC Fabrication Process Steps

The fabrication of integrated circuits consists basically of the following process steps:
• Lithography: The process for pattern definition by applying thin uniform layer of viscous liquid
(photo-resist) on the wafer surface. The photo-resist is hardened by baking and than selectively
removed by projection of light through a reticle containing mask information.
• Etching: Selectively removing unwanted material from the surface of the wafer. The pattern of the
photo-resist is transferred to the wafer by means of etching agents.
• Deposition: Films of the various materials are applied on the wafer. For this purpose mostly two
kind of processes are used, physical vapor deposition (PVD) and chemical vapor deposition (CVD).
• Chemical Mechanical Polishing: A planarization technique by applying a chemical slurry with
etchant agents to the wafer surface.
• Oxidation: In the oxidation process oxygen (dry oxidation) or H 2O(wet oxidation) molecules
convert silicon layers on top of the wafer to silicon dioxide.
• Ion Implantation: Most widely used technique to introduce dopant impurities into semiconductor.
The ionized particles are accelerated through an electrical field and targeted at the semiconductor
wafer.
• Diffusion: A diffusion step following ion implantation is used to anneal bombardment-induced
lattice defects.
CMOS FABRICATION
Silicon technology
• CMOS transistors are fabricated on silicon wafer
• Lithography process similar to printing press
• On each step, different materials are deposited or etched
• Easiest to understand by viewing both top and cross-section
• of wafer in a simplified manufacturing process
Example inverter cross-section
• Typically use p-type substrate for nMOS transistors
• Requires n-well for body of pMOS transistors

Well and substrate taps

Substrate contacts are critical to correct operation of CMOS
• Substrate must be tied to GND, n-well to VDD(reverse-biased diodes isolate regions)
• Metal to lightly-doped semiconductor forms poor connection called Schottky Diode { use heavily
doped well and substrate contacts/taps
CMOS technology
• N well process
• P well process
• SOI process
• Twintub process
N well Technology
1) Substrate Preparation
• Cover wafer with protective layer of SiO2 (oxide)
• Remove layer where n-well should be built
• Implant use n dopants into exposed wafer
• Strip off SiO2

2) Oxidation
• Grow SiO2 on top of Si wafer
• 900 -- 1200_C with H2O or O2 in oxidation furnace

3) Photoresist
Photoresist is a light-sensitive organic polymer which softens where exposed to light (positive
resist)

4) Lithography
• Use light to transfer a pattern to the wafer
• Expose photo resist through n-well mask (using UV light {example 193 nm wavelength)
• \Immersion lithography" used in some nano scale processes
• Strip off exposed photo resist

5) Etching and a strip photo resist

• Etch oxide with Hydrouoric acid (HF)
• Only attacks oxide where resist has been exposed

• Strip remaining photo resist using mixture of acids (\piranha" etch)

• Necessary so resist does not melt in the next step
6) N well formation (ion implantation)

7) Gate formation
• Very thin layer of gate oxide is grown on wafer
• Gate oxide thickness is < 20A (few atomic layers)
• One of the most critical steps in fabrication process
• Polysilicon deposited on top of gate oxide
• Grown using Chemical vapor deposition (CVD)
• Wafer placed in furnace with Silane (SiH) gas
• Small crystals (polysilicon) formed on wafer
• Heavily doped to be a good conductor

8) Polysilicon Patterning

 Use same lithography processing to pattern polysilicon

 Reactive Ion Etch (RIE) process
 Charge buildup on un-etched polysilicon can lead to antenna effects" and damage gate oxide
Self-aligned process : Polysilicon \blocks" dopants where the channel should be formed
9) N+ diffusion
• nMOS transistors are formed
• Oxide is patterned to form the n+ regions
• N+ diffusion forms nMOS source, drain, and n-well contact

Ion implantation used to dope silicon

• n+ regions are formed
• Oxide is stripped off to complete patterning step

10) P+ diffusion
A similar set of steps is used to form the p+ diffusion regions for the pMOS transistor source and
drain as well as the substrate contact
11) Contact cut
• Used to wire the devices together
• Wafer is covered with thick _eld oxide
• Oxide is etched where the contact cuts are needed

11) Metallization

Used to interconnect internal nodes

• Aluminum was the traditional metal
• Switch to Copper for high performance processes
• Aluminum is sputtered over the entire wafer
• Patterned to remove excess metal, leaving the wires

TWIN TUB PROCESS

1. Provide separate optimization of the n-type and p-type transistors
2. Make it possible to optimize "Vt", "Body effect", and the "Gain" of n, p devices,
independently.
3. Steps:
A. Starting material: an n+ or p+ substrate with lightly doped -> "epitaxial" or "epi" layer -
> to protect "latch up"
B. Epitaxy"
a. Grow high-purity silicon layers of controlled thickness
b. With accurately determined dopant concentrations
c. Electrical properties are determined by the dopant and its concentration in Si
C. Process sequence
a. Tub formation
b. Thin-Oxide construction
c. Source & drain implantations
d. Contact cut definition
e. Metallization
Balanced performance of n and p devices can be constructed.

SOI Process
Advantages
• Reduced Source and Drain to Substrate Capacitance.
• Absence of Latchup.
• Lower Passive current.
• Denser Layout Low cost.
STEP 1: SIO2 or Sapphire is used as an insulators

STEP 2: thin flim of thightly doped n-type Si is grown over an insulator.

STEP 3: Anisotropic etch (creation of n island)

STEP 4: Boron implantation

One island is masked. Then P – Island is formed by boron implantation

STEP 5: Phosporous implantation

 P- Island are protected with Photo resist then phosphorous is implemented in island
which is not protected

STEP 6:

 Grow gate oxide through thermal oxidation

- Deposit Doped Polysilicon
STEP 7: Formation of Polysilicon gate
 By etching and masking process polysilicon gate is formed.

Step 8: n-implantation for source & drain

Step 9: p-implantation

Step 10:
 Grow phosphorus glass
 Etch glass to form contact cut
 Evaporating alumni
BICMOS TECHNOLOGY

 It is the technology, where MOS transistors can be added to Bipolar process or Bipolar
transistor can be added to MOS process.
 CMOS+ Bipolar = BICMOS
 BICMOS structure

 Advantages:
o Richer device set.
o Bipolars are easier to make high frequency analog circuits,
o precision references,

Comparision between CMOS and BICMOS

CMOS BIPOLAR
Low static power dissipation High power dissipation
High input impedance Low input impedance
High noise margin Low voltage swing logic
High package density Low package density
High delay sensitivity to load Low delay sensitivity to load
Low input drive current High output drive current
Bidirectional capability Unidirectional capability
 CMOS INVERTER
Complementary metal–oxide–semiconductor (CMOS) inverter
• It is a technology for constructing integrated circuits. CMOS technology is used
in microprocessors, microcontrollers, static RAM, and other digital logic circuits.
• CMOS technology is also used for several analog circuits such as image sensors (CMOS
sensor), data converters, and highly integrated transceivers for many types of communication.
• Two important characteristics of CMOS devices are
High noise immunity
Low static power consumption.
• Since one transistor of the pair is always off, the series combination draws significant power only
momentarily during switching between on and off states.
• Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for
example transistor–transistor logic (TTL) or NMOS logic, which normally have some standing
current even when not changing state.
• CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that
CMOS became the most used technology to be implemented in VLSI chips.

• CMOS circuits are constructed in such a way that all PMOS transistors must have either an input
from the voltage source or from another PMOS transistor.
• Similarly, all NMOS transistors must have either an input from ground or from another NMOS
transistor.
• The composition of a PMOS transistor creates low resistance between its source and drain contacts
when a low gate voltage is applied and high resistance when a high gate voltage is applied.
• On the other hand, the composition of an NMOS transistor creates high resistance between source
and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied.
• When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state.
This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a low
resistance state and much more current can flow from the supply to the output. Because the
resistance between the supply voltage and Q is low, the voltage drop between the supply voltage
and Q due to a current drawn from Q is small. The output therefore registers a high voltage.
• On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high
resistance) state so it would limit the current flowing from the positive supply to the output, while
the NMOS transistor is in an ON (low resistance) state, allowing the output from drain to ground.

• In short, the outputs of the PMOS and NMOS transistors are complementary such that when the
input is low, the output is high, and when the input is high, the output is low. Because of this
behaviour of input and output, the CMOS circuits' output is the inverse of the input.

• The power supplies for CMOS are called VDD and VSS, or VCC and Ground(GND).

Circuit diagram of CMOS NAND gate

• A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will
conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be
established between the output and Vss(ground), bringing the output low.

• If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while
both of the PMOS transistors will conduct, establishing a conductive path between the output
and Vdd (voltage source), bringing the output high.

• If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the
PMOS transistors will, and a conductive path will be established between the output andVdd (voltage
source), bringing the output high

Propagation delay
 if the pass transistors are connected in series logic signals must pass through a no of
transistors
 A chain of four transistors, in which all gates connected to Vdd(logic 1), which the signal to
be propagated to the output.

 The delay through the network is evaluated , the response at node V2 with respect to time is given
by
dv 2
C=(I 1−I 2)
dv 1

dv 2 [ (V 1−V 2 ) −( V 2−V 3 ) ]
C=
dv 1 R
 As the number of sections in a network becomes large, the expression reduces to
dv d2v
RC =
dv dx 2
 Where,
o R – resistance per unit length
o C – Capacitance per unit length
o X – distance along network from input

Power dissipation techniques

• Total Power dissipated in a CMOS circuit is sum total of dynamic power, short circuit power
and static or leakage power.
Figure 3.Components of Power in CMOS circuit
Power and energy
• Power is drawn from a voltage source attached to the VDD pin(s) of a chip.
P (t ) iDD (t )VDD
• Instantaneous Power:
T T
E P (t )dt iDD (t )VDD dt
• 0 0 Energy:

T
E 1
T T
Pavg   iDD (t )VDD dt
• 0 Average Power:
Dynamic power
Charging and discharging of load capacitances

o CMOS circuits dissipate power by charging the various load capacitances (mostly gate and
wire capacitance, but also drain and some source capacitances) whenever they are switched.
o In one complete cycle of CMOS logic, current flows from V DD to the load capacitance to
charge it and then flows from the charged load capacitance (CL) to ground during discharge.
o Therefore in one complete charge/discharge cycle, a total of Q=C LVDD is thus transferred from
VDD to ground. Multiply by the switching frequency on the load capacitances to get the current
used, and multiply by the average voltage again to get the characteristic switching power
dissipated by a CMOS device: P= 0.5CV2.
o Since most gates do not operate/switch at every clock cycle, they are often accompanied by a

factor , called the activity factor. Now, the dynamic power dissipation may be re-written as
P = αCV2f .
 o A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data
has an activity factor of 0.1. [6] If correct load capacitance is estimated on a node together with
its activity factor, the dynamic power dissipation at that node can be calculated effectively.

VDD
iDD(t)

C
fsw

• Dynamic power is required to charge and discharge load capacitances when transistors switch.
• One cycle involves a rising and falling output.
• On rising output, charge Q = CVDD is required
• On falling output, charge is dumped to GND
• This repeats Tfsw times over an interval of T

• Suppose the system clock frequency = f

• Let fsw = af,
where a = activity factor
• If the signal is a clock, a = 1
• If the signal switches once per cycle, a = ½
• Dynamic gates:
Switch either 0 or 2 times per cycle, a = ½
• Static gates:
Depends on design, but typically a = 0.1
Pdynamic  CVDD 2 f
• Dynamic power:
Short circuit current
• When transistors switch, both nMOS and pMOS networks may be momentarily ON at once
• Leads to a blip of “short circuit” current.
• < 10% of dynamic power if rise/fall times are comparable for input and output
Static power
Short-circuit power dissipation

• Since there is a finite rise/fall time for both pMOS and nMOS, during transition, for example, from
off to on, both the transistors will be on for a small period of time in which current will find a path
directly from VDD to ground, hence creating a short circuit current. Short circuit power dissipation
increases with rise and fall time of the transistors.

• An additional form of power consumption became significant in the 1990s as wires on chip
became narrower and the long wires became more resistive. CMOS gates at the end of those
resistive wires see slow input transitions. During the middle of these transitions, both the NMOS
and PMOS logic networks are partially conductive, and current flows directly from VDD to VSS.

• The power thus used is called crowbar power. Careful design which avoids weakly driven long
skinny wires ameliorates this effect, but crowbar power can be a substantial part of dynamic CMOS
power.

• To speed up designs, manufacturers have switched to constructions that have lower voltage
thresholds but because of this a modern NMOS transistor with a V th of 200 mV has a
significant subthreshold leakage current. Designs (e.g. desktop processors) which include vast
numbers of circuits which are not actively switching still consume power because of this leakage
current.

• Leakage power is a significant portion of the total power consumed by such designs. Multi-
threshold CMOS (MTCMOS), now available from foundries, is one approach to managing leakage
power. With MTCMOS, high Vth transistors are used when switching speed is not critical, while low
Vth transistors are used in speed sensitive paths. Further technology advances that use even thinner
gate dielectrics have an additional leakage component because of current tunnelling through the
extremely thin gate dielectric. Using high-k dielectrics instead of silicon dioxide that is the
conventional gate dielectric allows similar device performance, but with a thicker gate insulator,
thus avoiding this current.

• Leakage power reduction using new material and system designs is critical to sustaining scaling of
CMOS

• Static power is consumed even when chip is quiescent.

• Ratioed circuits burn power in fight between ON transistors
• Leakage draws power from nominally OFF devices
Vgs  Vt  Vds
nvT
 v

I ds  I ds 0e 1  e T 
 
Vt Vt 0  Vds    s  Vsb  s 
Reduction techniques
• Dynamic power reduction
a: clock gating, sleep mode
C: small transistors (esp. on clock), short wires
VDD: lowest suitable voltage
f: lowest suitable frequency
• Reduce static power
Selectively use ratioed circuits
Selectively use low Vt devices
Leakage reduction:
stacked devices, body bias, low temperature
Stick diagram

Objectives:

• To know what is meant by stick diagram.

• To understand the capabilities and limitations of stick diagram.

• To learn how to draw stick diagrams for a given MOS circuit.

Stick definition

• VLSI design aims to translate circuit concepts onto silicon.

• Stick diagrams are a means of capturing topography and layer information using simple diagrams.

• Stick diagrams convey layer information through colour codes (or monochrome encoding).

• Acts as an interface between symbolic circuit and the actual layout

It shows

• Exact placement of components

• Transistor sizes
• Wire lengths, wire widths, tub boundaries.

• Any other low level details such as parasitics

• It shows relative placement of components.

• Goes one step closer to the layout

• Helps plan the layout and routing

Notations

P diffusion : Yellow/Brown Metal1 : Blue

N diffusion : Green Metal2 : Magenta/Purple
Polysilicon : Red Metal3 : Cyan/L.Blue
Contacts & Taps : Black

Stick rules

Rule 1

• When two or more ‘sticks’ of the same type cross or touch each other that represents electrical
contact.

Rule 2
• When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection explicitly).

Rule 3

• When a poly crosses diffusion it represents a transistor.

Rule 4

• In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie
on one side of the line and all nMOS will have to be on the other side.

CMOS NOR gate

Example 2: F=(AB+AC+BC)’ = (AB + C(A+B))’
Layout

• Layout can be very time consuming

Design gates to fit together nicely
Build a library of standard cells
• Standard cell design methodology
VDD and GND should abut (standard height)
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts
Example of inverter

• Stick diagrams help plan layout quickly

Need not be to scale
Draw with color pencils or dry-erase markers
MOS LAYERS

Layout design rules

• The process technology referred to the length of the silicon channel between the source and drain
terminals in field effect transistors.
• The sizes of other features are generally derived as a ratio of the channel length, where some may
be larger than the channel size and some smaller.
• For example, in a 90 nm process, the length of the channel may be 90 nm, but the width of the gate
terminal may be only 50 nm.
• Allow translation of circuits (usually in stick diagram or symbolic form) into actual geometry in
silicon
• Interface between circuit designer and fabrication engineer
• It Compromises the
designer - tighter, smaller
fabricator - controllable, reproducible
Design rules define ranges for features
Examples:
• min. wire widths to avoid breaks
• min. spacing to avoid shorts
• minimum overlaps to ensure complete overlaps
• Measured in microns
• Required for resolution/tolerances of masks
• Fabrication processes defined by minimum channel width
• Also minimum width of poly traces
• Defines “how fast” a fabrication process is
Two major approaches:
i) “Micron” rules: stated at micron resolution.
Rules: simplified micron rules with limited scaling attributes.
 Design rules represents a tolerance which insures very high probability of correct
fabrication
ii) Scalable design rules: lambda parameter
Absolute dimensions (micron rules)
Micron rules
• All minimum sizes and spacing specified in microns.
• Rules don't have to be multiples of λ.
• Can result in 50% reduction in area over λ based rules
• Standard in industry.
Lambda-based
• Lambda-based (scalable CMOS) design rules define scalable rules based on l (which is half of the
minimum channel length)
• classes of MOSIS SCMOS rules:
SUBMICRON
DEEPSUBMICRON
• Stick diagram is a draft of real layout, it serves as an abstract view between the schematic and
layout.
• Circuit designer in general want tighter, smaller layouts for improved performance and decreased
silicon area.
• On the other hand, the process engineer wants design rules that result in a controllable and
reproducible process.
• Generally we find there has to be a compromise for a competitive circuit to be produced at a
reasonable cost.
• All widths, spacing, and distances are written in the form l = 0.5 X minimum drawn transistor
length
• Design rules based on single parameter, λ
• Simple for the designer
• Wide acceptance
• Provide feature size independent way of setting out mask
• If design rules are obeyed, masks will produce working circuits
• Minimum feature size is defined as 2 λ
• Used to preserve topological features on a chip
• Prevents shorting, opens, contacts from slipping out of area to be contacted
Design rules reality
• Manufacturing processes have inherent limitations in accuracy and repeatability
• Design rules specify geometry of masks that provide reasonable yield
• Design rules are determined by experience
Problems in manufacturing
• Photo resist shrinking / tearing
• Variations in material deposition
• Variations in temperature
• Variations in oxide thickness
• Impurities
• Variations between lots
• Variations across the wafer
• Variations in threshold voltage
• oxide thickness
• ion implantation
• poly variations
• Diffusion - changes in doping (variation in R, C)
• Poly, metal variations in height and width
• Shorts and opens
• Via may not be cut all the way through
• Undersize via has too much resistance
• Oversize via may short
Advantages
• Ease of learning because they are scalable, portable, durable
• Long-levity of designs that are simple, abstract and minimal clutter
• Increased designer efficiency
• Automatic translation to final layout
Design rules
• Minimum width of PolySi and diffusion line 2
• Minimum width of Metal line 3 as metal lines run over a more uneven surface than other
conducting layers to ensure their continuity

• PolySi – PolySi space 2

• Metal - Metal space 2
• Diffusion – Diffusion space 3 To avoid the possibility of their associated regions overlapping and
conducting current
• Diffusion – PolySi space To prevent the lines overlapping to form unwanted capacitor
• Metal lines can pass over both diffusion and polySi without electrical effect. Where no separation
is specified, metal lines can overlap or cross

Polysilicon
• Metal lines can pass over both diffusion and polySi without electrical effect
• It is recommended practice to leave between a metal edge and a polySi or diffusion line to which
it is not electrically connected to both the

• Butting contact
The gate and source of a depletion device can be connected by a method known as butting contact.
Here metal makes contact diffusion forming the source of the depletion transistor and to the polySi
forming this device’s gate.
• Advantage:
No buried contact mask required and avoids associated processing
• Buried contact
Here gate length is depend upon the alignment of the buried contact mask relative to the polySi and
therefore vary by .

Contact cut
• Metal connects to polySi/diffusion by contact cut.

• Contact area: 2 l X 2 l

• Metal and polySi or diffusion must overlap this contact area by l so that the two desired conductors
encompass the contact area despite any mis-alignment between conducting layers and the contact
hole
• A wiring track is the space required for a wire
• 4 l width, 4 l spacing from neighbour = 8 l pitch

• Transistors also consume one wiring track

CMOS process layers

CHOICE OF LAYERS
 Vdd and Vss should be distributed on the metal layer.
 Long polysilicon should be used only after careful consideration because of relatively high
Rs.
o Polysilicon is unsuitable for routing Vdd and Vss.
 Resistances associated with transistors are much higher than wiring resistance.
 Capacitive effects must also be carefully considered, particularly where fast signal lines are
required and particularly in relations to signals on wiring having relatively high values of Rs.
Diffusion area have relatively high value of capacitance to substrate and harder to drive.

Layer Resistance capacitance

Metal Low low

Silicide Low Moderate

Polysilicon High Moderate

Diffusion Moderate High