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Lecture # 03 - 04

The document provides an overview of the 8085 microprocessor, detailing its architecture, pin diagram, and various bus types including address, data, and control buses. It explains the functionality of each pin, including power supply, control signals, and interrupt handling, as well as the concept of Direct Memory Access (DMA). Additionally, it covers the types of interrupts, their priorities, and the serial input/output ports.
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0% found this document useful (0 votes)
23 views48 pages

Lecture # 03 - 04

The document provides an overview of the 8085 microprocessor, detailing its architecture, pin diagram, and various bus types including address, data, and control buses. It explains the functionality of each pin, including power supply, control signals, and interrupt handling, as well as the concept of Direct Memory Access (DMA). Additionally, it covers the types of interrupts, their priorities, and the serial input/output ports.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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MICROPROCESSOR AND INTERFACING

TECHNIQUES

Department of Computer Systems Engineering

MEHRAN UET, JAMSHORO.

1
LECTURE # 03- 04

PIN DIAGRAM , AND DESCRIPTION OF


MICROPROCESSOR 8085

2
MICROPROCESSOR ARCHITECTURE:

 The 8085 was first introduced in March1976 is an 8-bit


microprocessor with
 •16-bit address width capable of addressing 64kB of memory.
 •It has 40 pins.
 •Formed with 6500 transistors.
 •Requires a +5 volt power supply.
3

 •operates with a 3 MHz frequency.


MICROPROCESSOR ARCHITECTURE:

The pins can be grouped into 6 categories:


 1. Address bus
 2. Data bus
 3. Control & Status bus
 4. Power supply & frequency
 5. Externally initiated & acknowledgement signals
4

 6. Serial I/O ports


1. Address bus (16)

2. Data bus (8)


.
3. Control &
Status bus (6)

4. Power Supply
& Frequency
Signals (5)

5. Externally
initiated control
signals (11)

6. Serial
input/output
Ports (2) 5
ADDRESS BUS (16)

6
Address Bus (16 Pins):

 Address bus occupied 16 bits wide , therefore 8085 can access 2 raise to the power 16
locations(65,536) with numbers, from 0 to 65,535.
 •These range from 0000 to FFFF and is referred as 64kB of memory space.
 •The 8 signal lines, A8–A15, are unidirectional and used for the most significant bits
,called the high- order address of a16-bit address.
 •The 8 signal lines AD0–AD7 are used for a dual purpose : as a lower-order address
lines and also as a data bus.
7
Address Bus (16 Pins):

 When the 8085 wants to access a peripheral or a memory location ,it places the 16-bit
address on the address bus and then sends the appropriate control signals.
 •The low-order bidirectional address lines (AD0–AD7) are multiplexed with data bus.

WHAT IS MULTIPLEXING?

Multiplexing is a method by which multiple analog or digital


signals are combined into one signal over a shared medium. The
aim is to share an expensive resource. 8
Address Bus (16 Pins):

Why ADRESS BUS IS MULTIPLEXED WITH DATA BUS?


 This is done to reduce the size of microprocessor. Because we do not require address
and data bus at the same time, we can have a common bus for address and data. To select
a memory location, we need address first, when the location is selected after that we have
to transfer the data with that selected location.
 •During the first clock cycle they bring memory address of the low order memory or I/O
address. They then become the data bus during the second and third clock cycle.

9
DATA BUS (8)

10
DATA BUS (8 PINS):

 The signal lines AD0–AD7 are bidirectional : they serve a dual


purpose
 •They are used as the low-order address bus as well as the data
bus . This is known as multiplexing the bus.
 •The data bus is 8 bits wide ,and used for transferring the data
or program instruction.
 •The data flows both ways between the microprocessor & 11

memory or I/O.
CONTROL AND STATUS BUS (6)

12
CONTROL & STATUS BUS (6 PINS) :
 This group is Responsible for overall control & synchronization
of the system.
 Signals which are associated with timing and control unit.
 This group of signals includes:
 1). Two Control Signal (RD/WR)
 2).Two Status Signal (IO/M , S1 and S0)
 3).One Special Signal(ALE) 13
RD
PIN 32 (OUTPUT)
 RD stands for Read.

 It is an active low signal.

 It is a control signal used for Read


operation either from memory or from
Input device.
 A low signal indicates that data on the
data bus must be READ either from
selected memory location or from input
device.
14
WR
PIN 31 (OUTPUT)

 WR stands for Write.


 It is also active low signal.
 It is a control signal used for Write
operation either into memory or into
output device.
 A low signal indicates that data on the
data bus must be written into selected
memory location or into output device. 15
S0 AND S1
PIN 29 (OUTPUT) AND PIN 33 (OUTPUT)

 S0 and S1 are called Status Pins.


 They tell the current operation which is in
progress in 8085.

S0 S1 Operation
0 0 Halt
0 1 Write
1 0 Read
1 1 Opcode Fetch
16
IO/M
PIN 34 (OUTPUT)

 This pin tells whether I/O or


memory operation is being
performed.
 If IO/M = 1 then
 I/O operation is being performed.

 If IO/M = 0 then
 Memory operation is being performed. 17
IO/M
PIN 34 (OUTPUT)

 The operation being performed is indicated by S0 and S1.

 If S0 = 0 and S1 = 1 then
 It indicates WRITE operation.

 If IO/M = 0 then
 It indicates Memory operation.

 Combining these two we get Memory Write Operation.


18
ALE
PIN 30 (OUTPUT)

 It is used to Demultiplex Address and


Data Bus.
 It indicates whether bus functions as
address bus or data bus.
 If ALE = 1 then
 Bus functions as address bus.
 If ALE = 0 then
 Bus functions as data bus. 19
POWER SUPPLY & FREQUENCY SIGNALS (5)

20
X1 & X2
PIN 1 AND PIN 2 (INPUT)

 They are connected with crystal


oscillator.
 These are also called Crystal Input Pins.

 8085 can generate clock signals internally.

 To generate clock signals internally, 8085


requires external inputs from X1 and X2. 21
CLK OUT
PIN 37 (OUTPUT)

 This signal can be used as the system clock for other


devices.

 Sometimes it is necessary to generating clock outputs


from microprocessors so that they can be used for
other peripherals or other digital IC’s .

 This is provided by CLK pin.

 Its frequency is always same as 22

the frequency at which the microprocessor operates .


VSS AND VCC
PIN 20 (INPUT) AND PIN 40 (INPUT)

 +5V power supply is connected to VCC.

 Ground signal is connected to VSS.

23
EXTERNALLY INITIATED CONTROL SIGNALS (11)

24
RESET IN AND RESET OUT
PIN 36 (INPUT) AND PIN 3 (OUTPUT)

 RESET IN:
◦ It is used to reset the
microprocessor.
◦ It is active low signal.
◦ When the signal on this pin is low
for at least 3 clocking cycles, it
forces the microprocessor to reset
itself.
25
RESET IN AND RESET OUT
PIN 36 (INPUT) AND PIN 3 (OUTPUT)

 Resetting the microprocessor means:

◦ Clearing the PC and IR.


◦ Disabling all interrupts (except TRAP).
◦ Disabling the SOD pin.

26
RESET IN AND RESET OUT
PIN 36 (INPUT) AND PIN 3 (OUTPUT)

 RESET OUT:
◦ It is used to reset the peripheral
devices and other ICs on the circuit.
◦ It is an output signal.
◦ It is an active high signal.
.
◦ The output remains high as long as 27

RESET out is kept high.


READY
PIN 35 (INPUT)
 This pin is used to synchronize (Time
Matching) slower peripheral devices with
fast microprocessor.

 A low value causes the microprocessor to


enter into wait state.
Tw Tw

 The microprocessor remains in wait state


until the input at this pin goes high. 28
INTERRUPT PINS

 An interrupt is considered to be an emergency signal that


is to be serviced first.
 The Microprocessor responds to it as soon as possible.

29
What Happen When Interrupt Arrives..

When the interrupt signal arrives:


 The processor will break its routine
 Go to a different routine (interrupt service routine)
 Complete the interrupt service routine(ISR)
 Go back to the “regular” routine

30
Maskable interrupts

 Maskable interrupts are those interrupts which can be enabled


or disabled.

 Enabling and Disabling is done by software instructions .


 EI (Enable Interrupt)
 DI (Disable Interrupt)
31
Maskable interrupts

 List of Maskable Interrupts:

• RST 7.5

• RST 6.5

• RST 5.5

• INTR
32
Non-maskable interrupts
 The interrupts which are always in enabled mode are called non-
maskable interrupts.

 These interrupts CAN NEVER BE DISABLED by any


software instruction.

 TRAP is a non-maskable interrupt.


33
Priority based interrupts
 Priority of interrupts:
Interrupt Priority

TRAP 1

RST 7.5 2

RST 6.5 3

RST 5.5 4

INTR 5

34
TRAP
pin 6 (input)

 It is an non-maskable interrupt.
 It has the highest priority.
 It cannot be disabled.
 TRAP is usually used for power failure
and emergency shutoff.

35
RST 7.5
PIN 7 (INPUT)

 It is a maskable interrupt.
 It has the second highest priority.
 It can be Enabled or Disabled by
Software Instructions (EI and DI).

36

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RST 6.5
PIN 8 (INPUT)

 It is a maskable interrupt.
 It has the third highest priority.
 RST 6.5 can be enabled by EI
instruction.
 It can be disabled by DI instruction.

37
RST 5.5
PIN 9 (INPUT)

 It is a maskable interrupt.
 It has the fourth highest priority.
 It is also level triggered.
 The pin has to be held high for a
specific period of time.
 This interrupt is very similar to RST
6.5.
38
INTR
PIN 10 (INPUT)

It is a maskable
interrupt.
It has the lowest
priority.
39

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INTA
PIN 11 (OUTPUT)

 It stands for interrupt acknowledge.


 It is an active low signal.
 Low output on this pin indicates that
microprocessor has acknowledged the
INTR request.

40
Direct memory access?

 Direct memory access (DMA) is a method that allows


an input/output (I/O) device to send or receive data
directly to or from the main memory, bypassing the
CPU to speed up memory operations. The process is
managed by a chip known as a DMA controller
(DMAC).

41
Direct memory access?
AFTER HOLDA Signal CONNECTION IS BUILD

A0-A15 ADDRESS BUS CONNECTION


DMA CONTROLLER

8085 I/O (IT IS A CHIP USED


MICROPROCESSOR MEMORY
DEVICES TO CONNECT
UNIT PERIPHERAL
DEVICES WITH
DATA BUS CONNECTION MICROPROCESSOR)
D0-D7

HOLDA HOLD CONTROL BUS CONNECTION

DMA CONTROLLER SENDS HOLD SIGNAL TO MICROPROCESSOR


42

It Sends HOLDA Signal To Ensure That It Has Given The Hold Of Busses To Peripheral Devices
HOLD
PIN 38 (INPUT)

 HOLD pin is used to request the


microprocessor for DMA transfer.
 A high signal on this pin is a request to
microprocessor to relinquish
(RELEASE) the hold on buses.
 This request is sent by DMA controller.
43
HLDA
PIN 39 (OUTPUT)

 HLDA stands for Hold Acknowledge.

 The microprocessor uses this pin to


acknowledge the receipt of HOLD signal.
 AFTER HOLDA Signal CONNECTION IS
ESTABLISHED.

44
HLDA
PIN 39 (OUTPUT)

 The control of these buses goes to


DMA Controller.
 Control remains at DMA Controller
until HOLD is held high.
 When HOLD goes low, HLDA also
goes low and the microprocessor takes
control of the buses.
45

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SERIAL INPUT & OUTPUT PORTS (2)

46
SID AND SOD
PIN 4 (INPUT) AND PIN 5 (OUTPUT)

 The 8085 has two signals to implement the


serial transmission :
• SID (Serial Input Data)
• SOD (Serial Output Data)
• In serial transmission, data bits are sent
over a single line, one
bit at a time, such as the transmission over
telephone lines.

47
THE END !!!

48

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