Digital systems

Chapter 5

1 Computer organization
Dr. Iness NEDJI MILAT
[email protected]

First year – 2024/2025

2
Von Neumann Model
3 Von Neumann model
 John von Neumann proposed a fundamental model in 1945, for
processing computer programs.
 It is also known as the Von Neumann Architecture.

 It describes the design architecture for a computer with

these components:
 Central processing unit (CPU)
 Main memory that stores data and instructions (programs),

 Input and output devices,

 All these components are connected via buses.

 Von Neumann model : Two Key
4
Properties
 Von Neumann model is also called stored program computer. It
has two key properties:
 Stored program

 Both Data and Instructions are stored

in a same memory,
 Sequential instruction processing

 The CPU executes one instruction at a time using the Fetch-

Decode-Execute cycle
 Program counter (instruction pointer) identifies the current
instruction
 Program counter is advanced sequentially except for control
 Von Neumann model
5
Processes data and
Monitor,
Central processing instructions
Manages execution of Unit Printer, and
controls
Disk,… the
instructions by sending computer system
control signals to other Control Unit
parts of the CPU.
Registers
Registers
Temporary
Inputstorage Output
locations within the
CPU(Fast).
Arithmetic and Logic
Unit: carries out
Keyboard, ALU arithmetic and logical
Mouse, Busesoperations.
: Wires that are
Disk,… used to transfer data
between components
stores the program
Main Memory (instructions and
data)
6
Buses
7 Von Neumann model : Buses
 Buses are a communication system that transfers information
(Instruction, data, address, control signal) between components
inside a computer,

CPU Main Input/

Memory Output

Buses

 Von-Neumann Architecture comprised of three major bus systems

8 Types of Buses

Main
CPU Input/Output
Memory

Address Bus

Control Bus
1
0

Data Bus 1
0
1
1
1
0
Parallel lines

 A bus structure consists of a set of common lines, one for each bit of a binary
9 Types of Buses
 Data Bus
 Carries the data between the CPU, the memory and the
Input/Output devices
 Bidirectional : Either the CPU writes data to memory, or it read
data from memory
 May consist of 32, 64 or more separate lines
 The number of lines is referred to as the width of the data bus,
 The number of lines determines how many bits can be transferred
at a time
 The width of the data bus is a key factor in determining overall
system performance
10 Types of Buses
 Address Bus
 Carries the address of data between the CPU and the memory
units,
 Unidirectional : the CPU always sets the bus to indicate the address
of memory word being read or written.
 Its width determines the maximum possible memory capacity.

 Control Bus
 Carries control signals (commands) from the CPU in order to control
and coordinate all the activities within the computer,
 Unidirectional : the CPU always sets it to indicate operations to be
11
Main Memory
12 Conceptual view of memory
▪The memory unit that establishes direct communication with the CPU is
called Main Memory. It is often referred to as RAM (Random Access
Memory).
▪A memory unit stores binary information (Instruction or data) Main
in groups
n
of bits called words. n address Memory
lines 2n words
▪The data lines (bus) consists of m lines which CS m bits per
transfer information from or to the memory,
R/W word

▪The address lines consists of n lines that specify which m

word (among the 2n words available) to be selected
m data lines
for reading or writing.
▪The control line Read/Write (1/0) specifies the direction of transfer of
the data (Memory operation).
▪The control line Chip Select (CS) selects the chip box to be read
13 Array Organization of Memory
Main
Memory

2n- Word 2n -1
1

Addres •
• n lines •
s bus
CS • Deepth
R/W (2n)
Data • •
• m lines
bus
2

1 Word 1

@0 Bm-1 ... B3 B2 B1 B0 Word 0

Width (m)
14 Array Organization of Memory : Example
Main
 Address bus : n = 3 lines
memory
 Memory size = 23 words = 8 words 7 0 0 1 1

 Data bus : m = 4 lines (word = 4 bits) 6 1 1 1 0

 Memory size = 23 × 4 bits = 32 bits 5 1 0 0 0

4
 For example, the 4-bit word stored at address 1 0 1 1
Deept
h
3 1 0 1 1
5 is 1000
2 1 0 0 0

1 0 1 1 0

0 0 0 0 1

addresse
s
Width
15 Memory array architecture
Main
 Memory is a 2D array of bits. memory
Cell
Word 2n -1
 Each bit stored in a cell memory.

 Address Decoder selects a word line

Address

Decoder
bus
 R/W selector determines access type

 CS selector determines a chip box

Word 1
R/W
 Word line is then coupled to the data lines
CS Word 0

Data bus
16 Memory: Write and Read Operations

 The Write operation:

 Transfers the address of the desired word to the address lines
 Transfers the data bits (the word) to be stored in memory to the
data input lines
 Activates the Write control line (set Read/Write to 0)

 The Read operation:

 Transfers the address of the desired word to the address lines
 Activates the Read control line (set Read/Write to 1)
 Transfers a copy of the accessed word to the data output lines
17
Implementation of RAM Cells
RAM memory (Random Access Memory) is implemented
as semiconductor memory, where data is stored within memory
cells built from MOS transistors and other components

DRAM (Dynamic RAM) SRAM (Static RAM)

Main memory Cache memory
19 Memory Technology: DRAM
 DRAM bit = 1 transistor + 1 capacitor
 Capacitor charge state indicates bit value
 Whether the capacitor is charged or discharged indicates storage of 1
or 0
 The electric charge on the capacitors gradually leaks away
 DRAM cell loses charge over time
 DRAM cell needs to be refreshed
Refresh : A DRAM controller must By applying an electrical
periodically rewrites the data in the capacitors, pulse to all memory bits
restoring them to their original charge

The need to refresh DRAM demands more complicated circuitry and timing
than SRAM.
20
Central Processing Unit
 Central Processing Unit (CPU) :
21
Registers
 The CPU is responsible for executing the instructions of computer
programs. Its major components are : Control Unit, ALU and a
Program Counter : holds the memory
varietyprocessing
Central of registers.
address of the next instruction to be
Unit executed.
PC
How these
Memory Address Register : holds the
components are
memory address of either the data or the
Control Unit
MAR organized inside
instruction.
the CPU?
Accumulator : holds the results of
ACC
Registers calculations carried out by the ALU

IR Instruction Register : holds the current

instruction to execute
MDR
ALU Memory Data Register : holds the data or
instruction retrieved from main memory.
22 Organization of CPU components
Buse
n lines
General Purpose Registers (Reg File) : s
Central processing
set of temporary registers used for any
purpose. Unit
Program
Ex. Status intermediate
store operands, Word : set of flag Main
Processing bits (carry,ofoverflow,
results or arguments functions…Interrupt, @memory
n bits n
2 -1
R1 supervisor flags)MARand Instruction
unit
R2 pointer,..
@
Rn PSW PC
n lines
ACC
Sequencer d
e
16-bit
(Control logic c
bloc) o
ALU d
e
Instr. r m bits

IR Decoder @0
m bits
MDR Control unit
m bits

m lines m lines
 CPU : Control unit vs Processing
23
unit
 The control unit allows:
 to sequence the execution of the programs’
instructions,
 to ensure the fetching and the decoding of the
instruction to execute (which is encoded in binary form)
 to organize the execution of the instruction,
 to carry out the preparation of the following instruction.

 The processing unit allows:

 to execute the instruction by performing the operation,
 to hold temporally the operands and the results of the
operation into Register File,
24
Machine Instruction
 Converting high-level language to binary
25
machine language
 Programs are written in any high-level languages such : C++,
Python, Java,..
 The CPU can execute only machine instructions in binary
 Therefore, all programs in high-level languages, are first translated
RISC Architecture
(compiled) into a binary machine instructions
Int A=5, B=7, beforeInstruction
CISC Architecture the program can
(Reduced
(Complex Instruction Set Computer) Set Computer)
run. High-level language S; CPU can execute CPUthis
can only execute
program (in C) S=A+B; elementary
complex instruction (4 instructions
CLK (1
… pulses) Clock pulse)
Compiler
RISC :

?
Assembly language
program
CISC :
ADD S, A,
Lw R1, A
Lw R2, B
B ADD R3, R1, Machine
R2 instructions
Assembler
Sw S, R3
0000 1001 1100 0110 1010 1111 0101 1000
Binary Machine 0000 1001 0101 1000 0000 1001 1100 0110
Langage Program 1100 0110 1010 1111 0101 1000 0000 1001
0100 0110 0000 1001 1100 0110 1010 1111
26 Machine instruction
 The machine instruction is simply a sequence of bits that can be directly
decoded and executed by the CPU,
 For executing instruction, the CPU needs to know : the operation, the
operands and their addressing modes,
 The machine instruction consists of two fields :
 Operation Code (Opcode) : specifies the operation to be performed by
CPU,
 Operand (s) : specifies the data to be operated by the CPU. The operand
can either be stored in main memory Constant
or in CPU register.
(immediate addressing mode) Lw R1, 5

OPCODE OPERAND(s) Address memory (Direct addressing mode) ADD S, A, B

Machine instruction
Register (Register addressing mode) ADD R3, R1, R2

 Examples : ADD R3, R1, R2 ; R3= R1+R2

1101 0011 0001 0010
 How to Execute
27
Instructions?
1. First we need to :
 Fetch the instruction
2. Then we need to :
 Decode instruction / fetch operands
3. Then we need to :
 Do the operation

This process is repeated continuously, therefore it is known as

the Fetch – Decode - Execute Cycle.
 It organizes the

28 Fetch - Decode – Execute cycle (CISC)

execution of the complex
Buse
instruction (ADD S,A,B)
into a set of elementary
30 instructions (need a
s
Central processing
complex hardware) :
Lw R0, Unit
$ 0010; Main
R0 Processing
Lw R1, $ 0100; 4 bits memory
ADD ACC,R0, R1;
R1 unitSw MAR 1000
0010
0100
0110
$ 00110, ACC; 8 0110 01100010
ADD S,A,B
R2 @ 0100

R3 PSW PC 1000
1001
S = 6 0000000000000
ACC 000
d
0000000000001 Sequencer e16-bitB = 4 0000000000000
100 EN = 1
(Control logic
0110 010 )
0010bloc
R/W
R/W == 1
0
1 c 111
+ 0 o 3
d
ALU A=2 0000000000000
e 101
Instr. r 1

IR +Decoder
0110 0110 0010 010 0
16 bits 0 16 bits

MDR Control unit 1. It divides the

16 bits instruction into Opcode
16 lines and 16
operands,
lines
2. It decodes the Opcode,
Step 1: Load Step 3: Load IR
3. It sends them to
Step 2: Access Sequencer
MAR and
memory
with the content Decode Execute
increment PC of MDR
29 Fetch - Decode – Execute cycle (RISC)
Buse It organizes the execution of
30 s instruction by
the elementary
Central processing accessing to the operand
Unit Main
registers and activating the
adder circuit (not need a
memory
R0 Processing 4 bits
complex hardware
R1 unit MAR 1000
8
0110 ADD
0011 0001
R2 @ 0010
R3,R1,R2
R3 PSW PC 1000
1001
S = 6 0000000000000
ACC 000
d
0000000000001 Sequencer e16-bitB = 4 0000000000000
100 EN = 1
(Control logic
0011 010 )
0001bloc
R/W = 1 c 111
+ 0 o 3
d
ALU A=2 0000000000000
e 101
Instr. r 1

IR +Decoder
0110 0011 0001 001 0
16 bits 0 16 bits

MDR Control unit 1. It divides the

16 bits instruction into Opcode
16 lines and 16
operands,
lines
2. It decodes the Opcode,
Step 1: Load Step 3: Load IR
3. It sends them to
Step 2: Access Sequencer
MAR and
memory
with the content Decode Execute
increment PC of MDR