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MAVEn
SILICON
VLSITraining Center
Setting standards in VLSI Design

Final Test
Time: 3 Hrs & 30 Mins Total Marks : 100

Part - A
Marks : 40
Digital (12 Marks)
1. Give the minimum count of inverters (NOT gates) & 3 input gates
required for the
implementation of the below expression. Please don't use any 2 input gates. -- (6 Marks)
BC'D' +ABC'+ACD+ABD+A'BD'

2. Generate a divide by 5 fregquency clock from a source clock, using T flipflops. Duty
cycle
should be 80% duty cycle. -- (6 Marks)

Verilog (12 Marks)

3. Design a 4-bit binary counter using RTL which is controlled by the input w. If wis 1, then,
the output of the counter increments by 2 and wraps around to 0 or 1if the output
reaches
to 8 or 9 respectively. If w is 0, then, the counter behaves as a 4bit down counter.
-- (8 Marks)
4. What is the logic that gets synthesized when conditional operators in a single
continuous
assignment are nested as shown below? -- (4 Marks)
input sell,sel2 , sel3, inl,in2, in3,in4;
output outl;
assign outl = (sell == 1'bl) ? inl :
(sel2 = 1'bl) ? in2 :
(sel3 == 1'bl) ? in3 : in4;

Verification(16 Marks)
5. Write a snippet of code to delete the distinct elements of an array. Use array
methods only.
-- (4 Marks)
6. Write at least 4 System Verilog Assertions for validating a 4bit bidirectional shift register
with active low synchronous reset. -- (6 Marks)

7. What is the difference between get and get next item method of seq
item
port?
-- (6 Marks)

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Setting standards in VLSI Design

Part - B
Marks :40

Digital (12 Marks)

8. Design a digital logic circuit which will generate an output signal in such a way that the output
follows the input, but assertion in output happens in synchronism with clock and de-assertion
happens asynchronously as shown below. -- (5 Marks)

CIk

input

output

9. Draw a Moore overlapping FSM for the circuit which follows the following specifications.
This Sequential circuit has two inputs X1, X2 (each is of single bit wide) and one output
(Z). The initial output is 0. The output keeps on toggling value unless one of the input
sequences occurs : -(7 Marks)
The input sequence at (X1, X2} is 01 followed by 11, causes the output to become 0.
The input sequence at {X1, X2} is 10 followed by 11, causes the output to become 1.
The input sequence at (X1, X2} is 10 followed by 01, causes the output to remain
unchanged.

Verilog (12 Marks)

10. Find out the bug in the code & the hardware inferred by the following code. -- (6 Marks)
module XYZ (Data out, Data in, clock, reset);

input Data in, clock, reset;

output Data out;
wire (4:0] Data regi

assign Data out = Data reg [0] ;

always @ (negedge reset or posedge clock)
begin
if (reset == 1'b0)
Data reg <= 'b0;
else

end
Data_reg <= (Data in, Data reg[4:1]):

endmodule

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VLSI Training Center
Setting standards in VLSI Design

-- (6Marks)
11. Draw the waveform for the following code for first four clock cycles.
module test (0:
reg clk, a;
initial
begin
clk = 0;
forever
#5 clk = ~clk;
end
alwayse (posedge clk)
begin
a (= 0:
#5 a <= !a;
end
endmodule

Verification (16 Marks)

all the even
12. Write a System Verilog to calculate the difference between the average of
numbers and average of all odd numbers in a dynamic array which contains some even
and odd numbers at random locations (Do it with & without using array methods)
-- (6 Marks)

13. Predict the output for the following program. -- (4 Marks)

module test (0:
class AB;
int i;
endclass
mailbox # (AB) mbx = new(0;
initial
begin
AB al, a2;
int x;
al = new () ;
£or (int i = 0; i < 1); i++)
begin
al.i = i;
mbx.put (a1) ;
end
Eor (int i = 0; i 10; i++)
begin
mbx. get (a2) ;
if (a2.i > 8)
x++;
end
$display("xt04", x):
end
endmodule

14. Why uvm_sequencer and uvm driverare defined as non-virtual classes? -- (6 Marks)

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Setting standards in VLSI Design

Part -C (Basic Electronics, CMOS, Networks, FPGA, STA)

Marks : 20

15. Show how an op-amp can be used as summing amplifier.

-- (4 Marks)
l6. Explain the difference BJT & MOSFET.
-- (3 Marks)
17. In the below network, determine IL.
-- (5 Marks)
62

18 V 12 2 6S2

12 Q
18. The propagation delays of various components in the below
circuit are as follows.
Tpd-inverter = 3ns, Tpd-mux = 6ns and Tpd-and = Sns. Determine the propagation delay of the
below circuit if pipelining is not implemented. What is the frequency of
below circuit if pipelining registers are added in allthe branches of the cutoperation of the
set represented
by dotted curve. CIk to Q delay, setup and hold times of the
flipflops used in pipelining
process is 4ns, 2ns and lns respectively.
-- (6Marks)
D

Sel

19. What are the logic elements of an FPGA?

-- (2 Marks)

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